clk/mediatek/clk-mt6765-audio.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  * Author: Owen Chen <owen.chen@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt6765-clk.h>
0014
0015 static const struct mtk_gate_regs audio0_cg_regs = {
0016     .set_ofs = 0x0,
0017     .clr_ofs = 0x0,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 static const struct mtk_gate_regs audio1_cg_regs = {
0022     .set_ofs = 0x4,
0023     .clr_ofs = 0x4,
0024     .sta_ofs = 0x4,
0025 };
0026
0027 #define GATE_AUDIO0(_id, _name, _parent, _shift) {  \
0028         .id = _id,              \
0029         .name = _name,              \
0030         .parent_name = _parent,         \
0031         .regs = &audio0_cg_regs,        \
0032         .shift = _shift,            \
0033         .ops = &mtk_clk_gate_ops_no_setclr, \
0034     }
0035
0036 #define GATE_AUDIO1(_id, _name, _parent, _shift) {  \
0037         .id = _id,              \
0038         .name = _name,              \
0039         .parent_name = _parent,         \
0040         .regs = &audio1_cg_regs,        \
0041         .shift = _shift,            \
0042         .ops = &mtk_clk_gate_ops_no_setclr, \
0043     }
0044
0045 static const struct mtk_gate audio_clks[] = {
0046     /* AUDIO0 */
0047     GATE_AUDIO0(CLK_AUDIO_AFE, "aud_afe", "audio_ck", 2),
0048     GATE_AUDIO0(CLK_AUDIO_22M, "aud_22m", "aud_engen1_ck", 8),
0049     GATE_AUDIO0(CLK_AUDIO_APLL_TUNER, "aud_apll_tuner",
0050             "aud_engen1_ck", 19),
0051     GATE_AUDIO0(CLK_AUDIO_ADC, "aud_adc", "audio_ck", 24),
0052     GATE_AUDIO0(CLK_AUDIO_DAC, "aud_dac", "audio_ck", 25),
0053     GATE_AUDIO0(CLK_AUDIO_DAC_PREDIS, "aud_dac_predis",
0054             "audio_ck", 26),
0055     GATE_AUDIO0(CLK_AUDIO_TML, "aud_tml", "audio_ck", 27),
0056     /* AUDIO1 */
0057     GATE_AUDIO1(CLK_AUDIO_I2S1_BCLK, "aud_i2s1_bclk",
0058             "audio_ck", 4),
0059     GATE_AUDIO1(CLK_AUDIO_I2S2_BCLK, "aud_i2s2_bclk",
0060             "audio_ck", 5),
0061     GATE_AUDIO1(CLK_AUDIO_I2S3_BCLK, "aud_i2s3_bclk",
0062             "audio_ck", 6),
0063     GATE_AUDIO1(CLK_AUDIO_I2S4_BCLK, "aud_i2s4_bclk",
0064             "audio_ck", 7),
0065 };
0066
0067 static int clk_mt6765_audio_probe(struct platform_device *pdev)
0068 {
0069     struct clk_hw_onecell_data *clk_data;
0070     int r;
0071     struct device_node *node = pdev->dev.of_node;
0072
0073     clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
0074
0075     mtk_clk_register_gates(node, audio_clks,
0076                    ARRAY_SIZE(audio_clks), clk_data);
0077
0078     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0079
0080     if (r)
0081         pr_err("%s(): could not register clock provider: %d\n",
0082                __func__, r);
0083
0084     return r;
0085 }
0086
0087 static const struct of_device_id of_match_clk_mt6765_audio[] = {
0088     { .compatible = "mediatek,mt6765-audsys", },
0089     {}
0090 };
0091
0092 static struct platform_driver clk_mt6765_audio_drv = {
0093     .probe = clk_mt6765_audio_probe,
0094     .driver = {
0095         .name = "clk-mt6765-audio",
0096         .of_match_table = of_match_clk_mt6765_audio,
0097     },
0098 };
0099
0100 builtin_platform_driver(clk_mt6765_audio_drv);