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0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2712-clk.h>
0014
0015 static const struct mtk_gate_regs venc_cg_regs = {
0016 .set_ofs = 0x4,
0017 .clr_ofs = 0x8,
0018 .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_VENC(_id, _name, _parent, _shift) { \
0022 .id = _id, \
0023 .name = _name, \
0024 .parent_name = _parent, \
0025 .regs = &venc_cg_regs, \
0026 .shift = _shift, \
0027 .ops = &mtk_clk_gate_ops_setclr_inv, \
0028 }
0029
0030 static const struct mtk_gate venc_clks[] = {
0031 GATE_VENC(CLK_VENC_SMI_COMMON_CON, "venc_smi", "mm_sel", 0),
0032 GATE_VENC(CLK_VENC_VENC, "venc_venc", "venc_sel", 4),
0033 GATE_VENC(CLK_VENC_SMI_LARB6, "venc_smi_larb6", "jpgdec_sel", 12),
0034 };
0035
0036 static int clk_mt2712_venc_probe(struct platform_device *pdev)
0037 {
0038 struct clk_hw_onecell_data *clk_data;
0039 int r;
0040 struct device_node *node = pdev->dev.of_node;
0041
0042 clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
0043
0044 mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
0045 clk_data);
0046
0047 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0048
0049 if (r != 0)
0050 pr_err("%s(): could not register clock provider: %d\n",
0051 __func__, r);
0052
0053 return r;
0054 }
0055
0056 static const struct of_device_id of_match_clk_mt2712_venc[] = {
0057 { .compatible = "mediatek,mt2712-vencsys", },
0058 {}
0059 };
0060
0061 static struct platform_driver clk_mt2712_venc_drv = {
0062 .probe = clk_mt2712_venc_probe,
0063 .driver = {
0064 .name = "clk-mt2712-venc",
0065 .of_match_table = of_match_clk_mt2712_venc,
0066 },
0067 };
0068
0069 builtin_platform_driver(clk_mt2712_venc_drv);