clk/mediatek/clk-mt2712-vdec.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2712-clk.h>
0014
0015 static const struct mtk_gate_regs vdec0_cg_regs = {
0016     .set_ofs = 0x0,
0017     .clr_ofs = 0x4,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 static const struct mtk_gate_regs vdec1_cg_regs = {
0022     .set_ofs = 0x8,
0023     .clr_ofs = 0xc,
0024     .sta_ofs = 0x8,
0025 };
0026
0027 #define GATE_VDEC0(_id, _name, _parent, _shift) {   \
0028         .id = _id,              \
0029         .name = _name,              \
0030         .parent_name = _parent,         \
0031         .regs = &vdec0_cg_regs,         \
0032         .shift = _shift,            \
0033         .ops = &mtk_clk_gate_ops_setclr_inv,    \
0034     }
0035
0036 #define GATE_VDEC1(_id, _name, _parent, _shift) {   \
0037         .id = _id,              \
0038         .name = _name,              \
0039         .parent_name = _parent,         \
0040         .regs = &vdec1_cg_regs,         \
0041         .shift = _shift,            \
0042         .ops = &mtk_clk_gate_ops_setclr_inv,    \
0043     }
0044
0045 static const struct mtk_gate vdec_clks[] = {
0046     /* VDEC0 */
0047     GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),
0048     /* VDEC1 */
0049     GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "vdec_sel", 0),
0050     GATE_VDEC1(CLK_VDEC_IMGRZ_CKEN, "vdec_imgrz_cken", "vdec_sel", 1),
0051 };
0052
0053 static int clk_mt2712_vdec_probe(struct platform_device *pdev)
0054 {
0055     struct clk_hw_onecell_data *clk_data;
0056     int r;
0057     struct device_node *node = pdev->dev.of_node;
0058
0059     clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
0060
0061     mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
0062             clk_data);
0063
0064     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0065
0066     if (r != 0)
0067         pr_err("%s(): could not register clock provider: %d\n",
0068             __func__, r);
0069
0070     return r;
0071 }
0072
0073 static const struct of_device_id of_match_clk_mt2712_vdec[] = {
0074     { .compatible = "mediatek,mt2712-vdecsys", },
0075     {}
0076 };
0077
0078 static struct platform_driver clk_mt2712_vdec_drv = {
0079     .probe = clk_mt2712_vdec_probe,
0080     .driver = {
0081         .name = "clk-mt2712-vdec",
0082         .of_match_table = of_match_clk_mt2712_vdec,
0083     },
0084 };
0085
0086 builtin_platform_driver(clk_mt2712_vdec_drv);