clk/mediatek/clk-mt2712-mm.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2712-clk.h>
0014
0015 static const struct mtk_gate_regs mm0_cg_regs = {
0016     .set_ofs = 0x104,
0017     .clr_ofs = 0x108,
0018     .sta_ofs = 0x100,
0019 };
0020
0021 static const struct mtk_gate_regs mm1_cg_regs = {
0022     .set_ofs = 0x114,
0023     .clr_ofs = 0x118,
0024     .sta_ofs = 0x110,
0025 };
0026
0027 static const struct mtk_gate_regs mm2_cg_regs = {
0028     .set_ofs = 0x224,
0029     .clr_ofs = 0x228,
0030     .sta_ofs = 0x220,
0031 };
0032
0033 #define GATE_MM0(_id, _name, _parent, _shift) { \
0034         .id = _id,              \
0035         .name = _name,              \
0036         .parent_name = _parent,         \
0037         .regs = &mm0_cg_regs,           \
0038         .shift = _shift,            \
0039         .ops = &mtk_clk_gate_ops_setclr,    \
0040     }
0041
0042 #define GATE_MM1(_id, _name, _parent, _shift) { \
0043         .id = _id,              \
0044         .name = _name,              \
0045         .parent_name = _parent,         \
0046         .regs = &mm1_cg_regs,           \
0047         .shift = _shift,            \
0048         .ops = &mtk_clk_gate_ops_setclr,    \
0049     }
0050
0051 #define GATE_MM2(_id, _name, _parent, _shift) { \
0052         .id = _id,              \
0053         .name = _name,              \
0054         .parent_name = _parent,         \
0055         .regs = &mm2_cg_regs,           \
0056         .shift = _shift,            \
0057         .ops = &mtk_clk_gate_ops_setclr,    \
0058     }
0059
0060 static const struct mtk_gate mm_clks[] = {
0061     /* MM0 */
0062     GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
0063     GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
0064     GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
0065     GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
0066     GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
0067     GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
0068     GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
0069     GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
0070     GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
0071     GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
0072     GATE_MM0(CLK_MM_MDP_CROP, "mm_mdp_crop", "mm_sel", 10),
0073     GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
0074     GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
0075     GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
0076     GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
0077     GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "clk32k", 15),
0078     GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
0079     GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
0080     GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
0081     GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
0082     GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
0083     GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
0084     GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
0085     GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
0086     GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
0087     GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
0088     GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
0089     GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
0090     GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
0091     GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
0092     /* MM1 */
0093     GATE_MM1(CLK_MM_DISP_PWM0_MM, "mm_pwm0_mm", "mm_sel", 0),
0094     GATE_MM1(CLK_MM_DISP_PWM0_26M, "mm_pwm0_26m", "pwm_sel", 1),
0095     GATE_MM1(CLK_MM_DISP_PWM1_MM, "mm_pwm1_mm", "mm_sel", 2),
0096     GATE_MM1(CLK_MM_DISP_PWM1_26M, "mm_pwm1_26m", "pwm_sel", 3),
0097     GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
0098     GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_lntc", 5),
0099     GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
0100     GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_lntc", 7),
0101     GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "vpll_dpix", 8),
0102     GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
0103     GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "vpll3_dpix", 10),
0104     GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
0105     GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "vpll_dpix", 16),
0106     GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvdstx", 17),
0107     GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
0108     GATE_MM1(CLK_MM_SMI_COMMON1, "mm_smi_common1", "mm_sel", 21),
0109     GATE_MM1(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 22),
0110     GATE_MM1(CLK_MM_MDP_RDMA2, "mm_mdp_rdma2", "mm_sel", 23),
0111     GATE_MM1(CLK_MM_MDP_TDSHP2, "mm_mdp_tdshp2", "mm_sel", 24),
0112     GATE_MM1(CLK_MM_DISP_OVL2, "mm_disp_ovl2", "mm_sel", 25),
0113     GATE_MM1(CLK_MM_DISP_WDMA2, "mm_disp_wdma2", "mm_sel", 26),
0114     GATE_MM1(CLK_MM_DISP_COLOR2, "mm_disp_color2", "mm_sel", 27),
0115     GATE_MM1(CLK_MM_DISP_AAL1, "mm_disp_aal1", "mm_sel", 28),
0116     GATE_MM1(CLK_MM_DISP_OD1, "mm_disp_od1", "mm_sel", 29),
0117     GATE_MM1(CLK_MM_LVDS1_PIXEL, "mm_lvds1_pixel", "vpll3_dpix", 30),
0118     GATE_MM1(CLK_MM_LVDS1_CTS, "mm_lvds1_cts", "lvdstx3", 31),
0119     /* MM2 */
0120     GATE_MM2(CLK_MM_SMI_LARB7, "mm_smi_larb7", "mm_sel", 0),
0121     GATE_MM2(CLK_MM_MDP_RDMA3, "mm_mdp_rdma3", "mm_sel", 1),
0122     GATE_MM2(CLK_MM_MDP_WROT2, "mm_mdp_wrot2", "mm_sel", 2),
0123     GATE_MM2(CLK_MM_DSI2, "mm_dsi2", "mm_sel", 3),
0124     GATE_MM2(CLK_MM_DSI2_DIGITAL, "mm_dsi2_digital", "dsi0_lntc", 4),
0125     GATE_MM2(CLK_MM_DSI3, "mm_dsi3", "mm_sel", 5),
0126     GATE_MM2(CLK_MM_DSI3_DIGITAL, "mm_dsi3_digital", "dsi1_lntc", 6),
0127 };
0128
0129 static int clk_mt2712_mm_probe(struct platform_device *pdev)
0130 {
0131     struct device *dev = &pdev->dev;
0132     struct device_node *node = dev->parent->of_node;
0133     struct clk_hw_onecell_data *clk_data;
0134     int r;
0135
0136     clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
0137
0138     mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
0139             clk_data);
0140
0141     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0142
0143     if (r != 0)
0144         pr_err("%s(): could not register clock provider: %d\n",
0145             __func__, r);
0146
0147     return r;
0148 }
0149
0150 static struct platform_driver clk_mt2712_mm_drv = {
0151     .probe = clk_mt2712_mm_probe,
0152     .driver = {
0153         .name = "clk-mt2712-mm",
0154     },
0155 };
0156
0157 builtin_platform_driver(clk_mt2712_mm_drv);