clk/mediatek/clk-mt2712-mfg.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2712-clk.h>
0014
0015 static const struct mtk_gate_regs mfg_cg_regs = {
0016     .set_ofs = 0x4,
0017     .clr_ofs = 0x8,
0018     .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_MFG(_id, _name, _parent, _shift) { \
0022         .id = _id,              \
0023         .name = _name,              \
0024         .parent_name = _parent,         \
0025         .regs = &mfg_cg_regs,           \
0026         .shift = _shift,            \
0027         .ops = &mtk_clk_gate_ops_setclr,    \
0028     }
0029
0030 static const struct mtk_gate mfg_clks[] = {
0031     GATE_MFG(CLK_MFG_BG3D, "mfg_bg3d", "mfg_sel", 0),
0032 };
0033
0034 static int clk_mt2712_mfg_probe(struct platform_device *pdev)
0035 {
0036     struct clk_hw_onecell_data *clk_data;
0037     int r;
0038     struct device_node *node = pdev->dev.of_node;
0039
0040     clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
0041
0042     mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
0043             clk_data);
0044
0045     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0046
0047     if (r != 0)
0048         pr_err("%s(): could not register clock provider: %d\n",
0049             __func__, r);
0050
0051     return r;
0052 }
0053
0054 static const struct of_device_id of_match_clk_mt2712_mfg[] = {
0055     { .compatible = "mediatek,mt2712-mfgcfg", },
0056     {}
0057 };
0058
0059 static struct platform_driver clk_mt2712_mfg_drv = {
0060     .probe = clk_mt2712_mfg_probe,
0061     .driver = {
0062         .name = "clk-mt2712-mfg",
0063         .of_match_table = of_match_clk_mt2712_mfg,
0064     },
0065 };
0066
0067 builtin_platform_driver(clk_mt2712_mfg_drv);