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0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2712-clk.h>
0014
0015 static const struct mtk_gate_regs img_cg_regs = {
0016 .set_ofs = 0x0,
0017 .clr_ofs = 0x0,
0018 .sta_ofs = 0x0,
0019 };
0020
0021 #define GATE_IMG(_id, _name, _parent, _shift) { \
0022 .id = _id, \
0023 .name = _name, \
0024 .parent_name = _parent, \
0025 .regs = &img_cg_regs, \
0026 .shift = _shift, \
0027 .ops = &mtk_clk_gate_ops_no_setclr, \
0028 }
0029
0030 static const struct mtk_gate img_clks[] = {
0031 GATE_IMG(CLK_IMG_SMI_LARB2, "img_smi_larb2", "mm_sel", 0),
0032 GATE_IMG(CLK_IMG_SENINF_SCAM_EN, "img_scam_en", "csi0", 3),
0033 GATE_IMG(CLK_IMG_SENINF_CAM_EN, "img_cam_en", "mm_sel", 8),
0034 GATE_IMG(CLK_IMG_CAM_SV_EN, "img_cam_sv_en", "mm_sel", 9),
0035 GATE_IMG(CLK_IMG_CAM_SV1_EN, "img_cam_sv1_en", "mm_sel", 10),
0036 GATE_IMG(CLK_IMG_CAM_SV2_EN, "img_cam_sv2_en", "mm_sel", 11),
0037 };
0038
0039 static int clk_mt2712_img_probe(struct platform_device *pdev)
0040 {
0041 struct clk_hw_onecell_data *clk_data;
0042 int r;
0043 struct device_node *node = pdev->dev.of_node;
0044
0045 clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
0046
0047 mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
0048 clk_data);
0049
0050 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0051
0052 if (r != 0)
0053 pr_err("%s(): could not register clock provider: %d\n",
0054 __func__, r);
0055
0056 return r;
0057 }
0058
0059 static const struct of_device_id of_match_clk_mt2712_img[] = {
0060 { .compatible = "mediatek,mt2712-imgsys", },
0061 {}
0062 };
0063
0064 static struct platform_driver clk_mt2712_img_drv = {
0065 .probe = clk_mt2712_img_probe,
0066 .driver = {
0067 .name = "clk-mt2712-img",
0068 .of_match_table = of_match_clk_mt2712_img,
0069 },
0070 };
0071
0072 builtin_platform_driver(clk_mt2712_img_drv);