clk/mediatek/clk-mt2712-bdp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2017 MediaTek Inc.
0004  * Author: Weiyi Lu <weiyi.lu@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2712-clk.h>
0014
0015 static const struct mtk_gate_regs bdp_cg_regs = {
0016     .set_ofs = 0x100,
0017     .clr_ofs = 0x100,
0018     .sta_ofs = 0x100,
0019 };
0020
0021 #define GATE_BDP(_id, _name, _parent, _shift) { \
0022         .id = _id,              \
0023         .name = _name,              \
0024         .parent_name = _parent,         \
0025         .regs = &bdp_cg_regs,           \
0026         .shift = _shift,            \
0027         .ops = &mtk_clk_gate_ops_no_setclr, \
0028     }
0029
0030 static const struct mtk_gate bdp_clks[] = {
0031     GATE_BDP(CLK_BDP_BRIDGE_B, "bdp_bridge_b", "mm_sel", 0),
0032     GATE_BDP(CLK_BDP_BRIDGE_DRAM, "bdp_bridge_d", "mm_sel", 1),
0033     GATE_BDP(CLK_BDP_LARB_DRAM, "bdp_larb_d", "mm_sel", 2),
0034     GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_PXL, "bdp_vdi_pxl", "tvd_sel", 3),
0035     GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_DRAM, "bdp_vdi_d", "mm_sel", 4),
0036     GATE_BDP(CLK_BDP_WR_CHANNEL_VDI_B, "bdp_vdi_b", "mm_sel", 5),
0037     GATE_BDP(CLK_BDP_MT_B, "bdp_fmt_b", "mm_sel", 9),
0038     GATE_BDP(CLK_BDP_DISPFMT_27M, "bdp_27m", "di_sel", 10),
0039     GATE_BDP(CLK_BDP_DISPFMT_27M_VDOUT, "bdp_27m_vdout", "di_sel", 11),
0040     GATE_BDP(CLK_BDP_DISPFMT_27_74_74, "bdp_27_74_74", "di_sel", 12),
0041     GATE_BDP(CLK_BDP_DISPFMT_2FS, "bdp_2fs", "di_sel", 13),
0042     GATE_BDP(CLK_BDP_DISPFMT_2FS_2FS74_148, "bdp_2fs74_148", "di_sel", 14),
0043     GATE_BDP(CLK_BDP_DISPFMT_B, "bdp_b", "mm_sel", 15),
0044     GATE_BDP(CLK_BDP_VDO_DRAM, "bdp_vdo_d", "mm_sel", 16),
0045     GATE_BDP(CLK_BDP_VDO_2FS, "bdp_vdo_2fs", "di_sel", 17),
0046     GATE_BDP(CLK_BDP_VDO_B, "bdp_vdo_b", "mm_sel", 18),
0047     GATE_BDP(CLK_BDP_WR_CHANNEL_DI_PXL, "bdp_di_pxl", "di_sel", 19),
0048     GATE_BDP(CLK_BDP_WR_CHANNEL_DI_DRAM, "bdp_di_d", "mm_sel", 20),
0049     GATE_BDP(CLK_BDP_WR_CHANNEL_DI_B, "bdp_di_b", "mm_sel", 21),
0050     GATE_BDP(CLK_BDP_NR_AGENT, "bdp_nr_agent", "nr_sel", 22),
0051     GATE_BDP(CLK_BDP_NR_DRAM, "bdp_nr_d", "mm_sel", 23),
0052     GATE_BDP(CLK_BDP_NR_B, "bdp_nr_b", "mm_sel", 24),
0053     GATE_BDP(CLK_BDP_BRIDGE_RT_B, "bdp_bridge_rt_b", "mm_sel", 25),
0054     GATE_BDP(CLK_BDP_BRIDGE_RT_DRAM, "bdp_bridge_rt_d", "mm_sel", 26),
0055     GATE_BDP(CLK_BDP_LARB_RT_DRAM, "bdp_larb_rt_d", "mm_sel", 27),
0056     GATE_BDP(CLK_BDP_TVD_TDC, "bdp_tvd_tdc", "mm_sel", 28),
0057     GATE_BDP(CLK_BDP_TVD_54, "bdp_tvd_clk_54", "tvd_sel", 29),
0058     GATE_BDP(CLK_BDP_TVD_CBUS, "bdp_tvd_cbus", "mm_sel", 30),
0059 };
0060
0061 static int clk_mt2712_bdp_probe(struct platform_device *pdev)
0062 {
0063     struct clk_hw_onecell_data *clk_data;
0064     int r;
0065     struct device_node *node = pdev->dev.of_node;
0066
0067     clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
0068
0069     mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
0070             clk_data);
0071
0072     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0073
0074     if (r != 0)
0075         pr_err("%s(): could not register clock provider: %d\n",
0076             __func__, r);
0077
0078     return r;
0079 }
0080
0081 static const struct of_device_id of_match_clk_mt2712_bdp[] = {
0082     { .compatible = "mediatek,mt2712-bdpsys", },
0083     {}
0084 };
0085
0086 static struct platform_driver clk_mt2712_bdp_drv = {
0087     .probe = clk_mt2712_bdp_probe,
0088     .driver = {
0089         .name = "clk-mt2712-bdp",
0090         .of_match_table = of_match_clk_mt2712_bdp,
0091     },
0092 };
0093
0094 builtin_platform_driver(clk_mt2712_bdp_drv);