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0007 #include <linux/clk-provider.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_device.h>
0011 #include <linux/platform_device.h>
0012
0013 #include "clk-cpumux.h"
0014 #include "clk-gate.h"
0015 #include "clk-mtk.h"
0016 #include "clk-pll.h"
0017
0018 #include <dt-bindings/clock/mt2701-clk.h>
0019
0020
0021
0022
0023
0024
0025 #define DUMMY_RATE 0
0026
0027 static DEFINE_SPINLOCK(mt2701_clk_lock);
0028
0029 static const struct mtk_fixed_clk top_fixed_clks[] = {
0030 FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
0031 108 * MHZ),
0032 FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
0033 400 * MHZ),
0034 FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
0035 295750000),
0036 FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
0037 340 * MHZ),
0038 FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
0039 340 * MHZ),
0040 FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
0041 340 * MHZ),
0042 FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
0043 27 * MHZ),
0044 FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
0045 416 * MHZ),
0046 FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
0047 143 * MHZ),
0048 FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
0049 27 * MHZ),
0050 FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
0051 DUMMY_RATE),
0052 FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
0053 DUMMY_RATE),
0054 FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
0055 DUMMY_RATE),
0056 };
0057
0058 static const struct mtk_fixed_factor top_fixed_divs[] = {
0059 FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
0060 FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
0061 FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
0062 FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
0063 FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
0064 FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
0065 FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
0066 FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
0067 FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
0068 FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
0069 FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
0070 FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
0071 FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
0072 FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
0073 FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
0074 FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
0075
0076 FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
0077 FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
0078 FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
0079 FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
0080 FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
0081 FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
0082 FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
0083 FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
0084 FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
0085 FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
0086 FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
0087 FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
0088 FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
0089 FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
0090 FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
0091 FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
0092 FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
0093 FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
0094 FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
0095 FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
0096 FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
0097
0098 FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
0099 FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
0100 FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
0101 FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
0102
0103 FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
0104 FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
0105
0106 FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
0107 FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
0108 FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
0109
0110 FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
0111 FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
0112 FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
0113
0114 FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
0115 FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
0116 FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
0117
0118 FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
0119 FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
0120 FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
0121
0122 FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
0123 FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
0124 FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
0125
0126 FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
0127
0128 FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
0129 FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
0130 FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
0131 FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
0132 FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
0133
0134 FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
0135 FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
0136 FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
0137 FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
0138 FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
0139 FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
0140 FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
0141 FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
0142 FACTOR(CLK_TOP_AXISEL_D4, "axisel_d4", "axi_sel", 1, 4),
0143 };
0144
0145 static const char * const axi_parents[] = {
0146 "clk26m",
0147 "syspll1_d2",
0148 "syspll_d5",
0149 "syspll1_d4",
0150 "univpll_d5",
0151 "univpll2_d2",
0152 "mmpll_d2",
0153 "dmpll_d2"
0154 };
0155
0156 static const char * const mem_parents[] = {
0157 "clk26m",
0158 "dmpll_ck"
0159 };
0160
0161 static const char * const ddrphycfg_parents[] = {
0162 "clk26m",
0163 "syspll1_d8"
0164 };
0165
0166 static const char * const mm_parents[] = {
0167 "clk26m",
0168 "vencpll_ck",
0169 "syspll1_d2",
0170 "syspll1_d4",
0171 "univpll_d5",
0172 "univpll1_d2",
0173 "univpll2_d2",
0174 "dmpll_ck"
0175 };
0176
0177 static const char * const pwm_parents[] = {
0178 "clk26m",
0179 "univpll2_d4",
0180 "univpll3_d2",
0181 "univpll1_d4",
0182 };
0183
0184 static const char * const vdec_parents[] = {
0185 "clk26m",
0186 "vdecpll_ck",
0187 "syspll_d5",
0188 "syspll1_d4",
0189 "univpll_d5",
0190 "univpll2_d2",
0191 "vencpll_ck",
0192 "msdcpll_d2",
0193 "mmpll_d2"
0194 };
0195
0196 static const char * const mfg_parents[] = {
0197 "clk26m",
0198 "mmpll_ck",
0199 "dmpll_x2_ck",
0200 "msdcpll_ck",
0201 "clk26m",
0202 "syspll_d3",
0203 "univpll_d3",
0204 "univpll1_d2"
0205 };
0206
0207 static const char * const camtg_parents[] = {
0208 "clk26m",
0209 "univpll_d26",
0210 "univpll2_d2",
0211 "syspll3_d2",
0212 "syspll3_d4",
0213 "msdcpll_d2",
0214 "mmpll_d2"
0215 };
0216
0217 static const char * const uart_parents[] = {
0218 "clk26m",
0219 "univpll2_d8"
0220 };
0221
0222 static const char * const spi_parents[] = {
0223 "clk26m",
0224 "syspll3_d2",
0225 "syspll4_d2",
0226 "univpll2_d4",
0227 "univpll1_d8"
0228 };
0229
0230 static const char * const usb20_parents[] = {
0231 "clk26m",
0232 "univpll1_d8",
0233 "univpll3_d4"
0234 };
0235
0236 static const char * const msdc30_parents[] = {
0237 "clk26m",
0238 "msdcpll_d2",
0239 "syspll2_d2",
0240 "syspll1_d4",
0241 "univpll1_d4",
0242 "univpll2_d4"
0243 };
0244
0245 static const char * const aud_intbus_parents[] = {
0246 "clk26m",
0247 "syspll1_d4",
0248 "syspll3_d2",
0249 "syspll4_d2",
0250 "univpll3_d2",
0251 "univpll2_d4"
0252 };
0253
0254 static const char * const pmicspi_parents[] = {
0255 "clk26m",
0256 "syspll1_d8",
0257 "syspll2_d4",
0258 "syspll4_d2",
0259 "syspll3_d4",
0260 "syspll2_d8",
0261 "syspll1_d16",
0262 "univpll3_d4",
0263 "univpll_d26",
0264 "dmpll_d2",
0265 "dmpll_d4"
0266 };
0267
0268 static const char * const scp_parents[] = {
0269 "clk26m",
0270 "syspll1_d8",
0271 "dmpll_d2",
0272 "dmpll_d4"
0273 };
0274
0275 static const char * const dpi0_parents[] = {
0276 "clk26m",
0277 "mipipll",
0278 "mipipll_d2",
0279 "mipipll_d4",
0280 "clk26m",
0281 "tvdpll_ck",
0282 "tvdpll_d2",
0283 "tvdpll_d4"
0284 };
0285
0286 static const char * const dpi1_parents[] = {
0287 "clk26m",
0288 "tvdpll_ck",
0289 "tvdpll_d2",
0290 "tvdpll_d4"
0291 };
0292
0293 static const char * const tve_parents[] = {
0294 "clk26m",
0295 "mipipll",
0296 "mipipll_d2",
0297 "mipipll_d4",
0298 "clk26m",
0299 "tvdpll_ck",
0300 "tvdpll_d2",
0301 "tvdpll_d4"
0302 };
0303
0304 static const char * const hdmi_parents[] = {
0305 "clk26m",
0306 "hdmipll_ck",
0307 "hdmipll_d2",
0308 "hdmipll_d3"
0309 };
0310
0311 static const char * const apll_parents[] = {
0312 "clk26m",
0313 "audpll",
0314 "audpll_d4",
0315 "audpll_d8",
0316 "audpll_d16",
0317 "audpll_d24",
0318 "clk26m",
0319 "clk26m"
0320 };
0321
0322 static const char * const rtc_parents[] = {
0323 "32k_internal",
0324 "32k_external",
0325 "clk26m",
0326 "univpll3_d8"
0327 };
0328
0329 static const char * const nfi2x_parents[] = {
0330 "clk26m",
0331 "syspll2_d2",
0332 "syspll_d7",
0333 "univpll3_d2",
0334 "syspll2_d4",
0335 "univpll3_d4",
0336 "syspll4_d4",
0337 "clk26m"
0338 };
0339
0340 static const char * const emmc_hclk_parents[] = {
0341 "clk26m",
0342 "syspll1_d2",
0343 "syspll1_d4",
0344 "syspll2_d2"
0345 };
0346
0347 static const char * const flash_parents[] = {
0348 "clk26m_d8",
0349 "clk26m",
0350 "syspll2_d8",
0351 "syspll3_d4",
0352 "univpll3_d4",
0353 "syspll4_d2",
0354 "syspll2_d4",
0355 "univpll2_d4"
0356 };
0357
0358 static const char * const di_parents[] = {
0359 "clk26m",
0360 "tvd2pll_ck",
0361 "tvd2pll_d2",
0362 "clk26m"
0363 };
0364
0365 static const char * const nr_osd_parents[] = {
0366 "clk26m",
0367 "vencpll_ck",
0368 "syspll1_d2",
0369 "syspll1_d4",
0370 "univpll_d5",
0371 "univpll1_d2",
0372 "univpll2_d2",
0373 "dmpll_ck"
0374 };
0375
0376 static const char * const hdmirx_bist_parents[] = {
0377 "clk26m",
0378 "syspll_d3",
0379 "clk26m",
0380 "syspll1_d16",
0381 "syspll4_d2",
0382 "syspll1_d4",
0383 "vencpll_ck",
0384 "clk26m"
0385 };
0386
0387 static const char * const intdir_parents[] = {
0388 "clk26m",
0389 "mmpll_ck",
0390 "syspll_d2",
0391 "univpll_d2"
0392 };
0393
0394 static const char * const asm_parents[] = {
0395 "clk26m",
0396 "univpll2_d4",
0397 "univpll2_d2",
0398 "syspll_d5"
0399 };
0400
0401 static const char * const ms_card_parents[] = {
0402 "clk26m",
0403 "univpll3_d8",
0404 "syspll4_d4"
0405 };
0406
0407 static const char * const ethif_parents[] = {
0408 "clk26m",
0409 "syspll1_d2",
0410 "syspll_d5",
0411 "syspll1_d4",
0412 "univpll_d5",
0413 "univpll1_d2",
0414 "dmpll_ck",
0415 "dmpll_d2"
0416 };
0417
0418 static const char * const hdmirx_parents[] = {
0419 "clk26m",
0420 "univpll_d52"
0421 };
0422
0423 static const char * const cmsys_parents[] = {
0424 "clk26m",
0425 "syspll1_d2",
0426 "univpll1_d2",
0427 "univpll_d5",
0428 "syspll_d5",
0429 "syspll2_d2",
0430 "syspll1_d4",
0431 "syspll3_d2",
0432 "syspll2_d4",
0433 "syspll1_d8",
0434 "clk26m",
0435 "clk26m",
0436 "clk26m",
0437 "clk26m",
0438 "clk26m"
0439 };
0440
0441 static const char * const clk_8bdac_parents[] = {
0442 "32k_internal",
0443 "8bdac_ck",
0444 "clk26m",
0445 "clk26m"
0446 };
0447
0448 static const char * const aud2dvd_parents[] = {
0449 "a1sys_hp_ck",
0450 "a2sys_hp_ck"
0451 };
0452
0453 static const char * const padmclk_parents[] = {
0454 "clk26m",
0455 "univpll_d26",
0456 "univpll_d52",
0457 "univpll_d108",
0458 "univpll2_d8",
0459 "univpll2_d16",
0460 "univpll2_d32"
0461 };
0462
0463 static const char * const aud_mux_parents[] = {
0464 "clk26m",
0465 "aud1pll_98m_ck",
0466 "aud2pll_90m_ck",
0467 "hadds2pll_98m",
0468 "audio_ext1_ck",
0469 "audio_ext2_ck"
0470 };
0471
0472 static const char * const aud_src_parents[] = {
0473 "aud_mux1_sel",
0474 "aud_mux2_sel"
0475 };
0476
0477 static const char * const cpu_parents[] = {
0478 "clk26m",
0479 "armpll",
0480 "mainpll",
0481 "mmpll"
0482 };
0483
0484 static const struct mtk_composite cpu_muxes[] __initconst = {
0485 MUX(CLK_INFRA_CPUSEL, "infra_cpu_sel", cpu_parents, 0x0000, 2, 2),
0486 };
0487
0488 static const struct mtk_composite top_muxes[] = {
0489 MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
0490 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
0491 MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
0492 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
0493 MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
0494 ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
0495 MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
0496 0x0040, 24, 3, 31),
0497
0498 MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
0499 0x0050, 0, 2, 7),
0500 MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
0501 0x0050, 8, 4, 15),
0502 MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
0503 0x0050, 16, 3, 23),
0504 MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
0505 0x0050, 24, 3, 31),
0506 MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
0507 0x0060, 0, 1, 7),
0508
0509 MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
0510 0x0060, 8, 3, 15),
0511 MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
0512 0x0060, 16, 2, 23),
0513 MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
0514 0x0060, 24, 3, 31),
0515
0516 MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
0517 0x0070, 0, 3, 7),
0518 MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
0519 0x0070, 8, 3, 15),
0520 MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
0521 0x0070, 16, 1, 23),
0522 MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
0523 0x0070, 24, 3, 31),
0524
0525 MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
0526 0x0080, 0, 4, 7),
0527 MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
0528 0x0080, 8, 2, 15),
0529 MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
0530 0x0080, 16, 3, 23),
0531 MUX_GATE_FLAGS_2(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
0532 0x0080, 24, 2, 31, 0, CLK_MUX_ROUND_CLOSEST),
0533
0534 MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
0535 0x0090, 0, 3, 7),
0536 MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
0537 0x0090, 8, 2, 15),
0538 MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
0539 0x0090, 16, 3, 23),
0540
0541 MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
0542 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
0543 MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
0544 0x00A0, 8, 3, 15),
0545 MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
0546 0x00A0, 24, 2, 31),
0547
0548 MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
0549 0x00B0, 0, 3, 7),
0550 MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
0551 0x00B0, 8, 2, 15),
0552 MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
0553 0x00B0, 16, 3, 23),
0554 MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
0555 0x00B0, 24, 3, 31),
0556
0557 MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
0558 hdmirx_bist_parents, 0x00C0, 0, 3, 7),
0559 MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
0560 0x00C0, 8, 2, 15),
0561 MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
0562 0x00C0, 16, 2, 23),
0563 MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
0564 0x00C0, 24, 3, 31),
0565
0566 MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
0567 0x00D0, 0, 2, 7),
0568 MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
0569 0x00D0, 16, 2, 23),
0570 MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
0571 0x00D0, 24, 3, 31),
0572
0573 MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
0574 0x00E0, 0, 1, 7),
0575 MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
0576 0x00E0, 8, 3, 15),
0577 MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
0578 0x00E0, 16, 4, 23),
0579
0580 MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
0581 0x00E0, 24, 3, 31),
0582 MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
0583 0x00F0, 0, 3, 7),
0584 MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
0585 0x00F0, 8, 2, 15),
0586 MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
0587 0x00F0, 16, 1, 23),
0588
0589 MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
0590 0x0100, 0, 3),
0591
0592 MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
0593 0x012c, 0, 3),
0594 MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
0595 0x012c, 3, 3),
0596 MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
0597 0x012c, 6, 3),
0598 MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
0599 0x012c, 15, 1, 23),
0600 MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
0601 0x012c, 16, 1, 24),
0602 MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
0603 0x012c, 17, 1, 25),
0604 MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
0605 0x012c, 18, 1, 26),
0606 MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
0607 0x012c, 19, 1, 27),
0608 MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
0609 0x012c, 20, 1, 28),
0610 };
0611
0612 static const struct mtk_clk_divider top_adj_divs[] = {
0613 DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
0614 0x0120, 0, 8),
0615 DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
0616 0x0120, 8, 8),
0617 DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
0618 0x0120, 16, 8),
0619 DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
0620 0x0120, 24, 8),
0621 DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
0622 0x0124, 0, 8),
0623 DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
0624 0x0124, 8, 8),
0625 DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
0626 0x0124, 16, 8),
0627 DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
0628 0x0124, 24, 8),
0629 DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
0630 0x0128, 0, 8),
0631 DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
0632 0x0128, 8, 8),
0633 };
0634
0635 static const struct mtk_gate_regs top_aud_cg_regs = {
0636 .sta_ofs = 0x012C,
0637 };
0638
0639 #define GATE_TOP_AUD(_id, _name, _parent, _shift) { \
0640 .id = _id, \
0641 .name = _name, \
0642 .parent_name = _parent, \
0643 .regs = &top_aud_cg_regs, \
0644 .shift = _shift, \
0645 .ops = &mtk_clk_gate_ops_no_setclr, \
0646 }
0647
0648 static const struct mtk_gate top_clks[] = {
0649 GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
0650 21),
0651 GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
0652 22),
0653 GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
0654 23),
0655 GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
0656 24),
0657 GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
0658 25),
0659 GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
0660 26),
0661 GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
0662 27),
0663 GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
0664 28),
0665 };
0666
0667 static int mtk_topckgen_init(struct platform_device *pdev)
0668 {
0669 struct clk_hw_onecell_data *clk_data;
0670 void __iomem *base;
0671 struct device_node *node = pdev->dev.of_node;
0672 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0673
0674 base = devm_ioremap_resource(&pdev->dev, res);
0675 if (IS_ERR(base))
0676 return PTR_ERR(base);
0677
0678 clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
0679
0680 mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
0681 clk_data);
0682
0683 mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
0684 clk_data);
0685
0686 mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
0687 base, &mt2701_clk_lock, clk_data);
0688
0689 mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
0690 base, &mt2701_clk_lock, clk_data);
0691
0692 mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
0693 clk_data);
0694
0695 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0696 }
0697
0698 static const struct mtk_gate_regs infra_cg_regs = {
0699 .set_ofs = 0x0040,
0700 .clr_ofs = 0x0044,
0701 .sta_ofs = 0x0048,
0702 };
0703
0704 #define GATE_ICG(_id, _name, _parent, _shift) { \
0705 .id = _id, \
0706 .name = _name, \
0707 .parent_name = _parent, \
0708 .regs = &infra_cg_regs, \
0709 .shift = _shift, \
0710 .ops = &mtk_clk_gate_ops_setclr, \
0711 }
0712
0713 static const struct mtk_gate infra_clks[] = {
0714 GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
0715 GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
0716 GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
0717 GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
0718 GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
0719 GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
0720 GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
0721 GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
0722 GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
0723 GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
0724 GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
0725 GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
0726 GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
0727 GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
0728 GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
0729 GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
0730 GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
0731 GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
0732 };
0733
0734 static const struct mtk_fixed_factor infra_fixed_divs[] = {
0735 FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
0736 };
0737
0738 static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
0739 static u16 pericfg_rst_ofs[] = { 0x0, 0x4, };
0740
0741 static const struct mtk_clk_rst_desc clk_rst_desc[] = {
0742
0743 {
0744 .version = MTK_RST_SIMPLE,
0745 .rst_bank_ofs = infrasys_rst_ofs,
0746 .rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
0747 },
0748
0749 {
0750 .version = MTK_RST_SIMPLE,
0751 .rst_bank_ofs = pericfg_rst_ofs,
0752 .rst_bank_nr = ARRAY_SIZE(pericfg_rst_ofs),
0753 },
0754 };
0755
0756 static struct clk_hw_onecell_data *infra_clk_data;
0757
0758 static void __init mtk_infrasys_init_early(struct device_node *node)
0759 {
0760 int r, i;
0761
0762 if (!infra_clk_data) {
0763 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
0764
0765 for (i = 0; i < CLK_INFRA_NR; i++)
0766 infra_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER);
0767 }
0768
0769 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
0770 infra_clk_data);
0771
0772 mtk_clk_register_cpumuxes(node, cpu_muxes, ARRAY_SIZE(cpu_muxes),
0773 infra_clk_data);
0774
0775 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
0776 infra_clk_data);
0777 if (r)
0778 pr_err("%s(): could not register clock provider: %d\n",
0779 __func__, r);
0780 }
0781 CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
0782 mtk_infrasys_init_early);
0783
0784 static int mtk_infrasys_init(struct platform_device *pdev)
0785 {
0786 int r, i;
0787 struct device_node *node = pdev->dev.of_node;
0788
0789 if (!infra_clk_data) {
0790 infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
0791 } else {
0792 for (i = 0; i < CLK_INFRA_NR; i++) {
0793 if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER))
0794 infra_clk_data->hws[i] = ERR_PTR(-ENOENT);
0795 }
0796 }
0797
0798 mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
0799 infra_clk_data);
0800 mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
0801 infra_clk_data);
0802
0803 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
0804 infra_clk_data);
0805 if (r)
0806 return r;
0807
0808 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[0]);
0809
0810 return 0;
0811 }
0812
0813 static const struct mtk_gate_regs peri0_cg_regs = {
0814 .set_ofs = 0x0008,
0815 .clr_ofs = 0x0010,
0816 .sta_ofs = 0x0018,
0817 };
0818
0819 static const struct mtk_gate_regs peri1_cg_regs = {
0820 .set_ofs = 0x000c,
0821 .clr_ofs = 0x0014,
0822 .sta_ofs = 0x001c,
0823 };
0824
0825 #define GATE_PERI0(_id, _name, _parent, _shift) { \
0826 .id = _id, \
0827 .name = _name, \
0828 .parent_name = _parent, \
0829 .regs = &peri0_cg_regs, \
0830 .shift = _shift, \
0831 .ops = &mtk_clk_gate_ops_setclr, \
0832 }
0833
0834 #define GATE_PERI1(_id, _name, _parent, _shift) { \
0835 .id = _id, \
0836 .name = _name, \
0837 .parent_name = _parent, \
0838 .regs = &peri1_cg_regs, \
0839 .shift = _shift, \
0840 .ops = &mtk_clk_gate_ops_setclr, \
0841 }
0842
0843 static const struct mtk_gate peri_clks[] = {
0844 GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
0845 GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
0846 GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
0847 GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
0848 GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
0849 GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
0850 GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
0851 GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
0852 GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
0853 GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
0854 GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
0855 GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
0856 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
0857 GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
0858 GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
0859 GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
0860 GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
0861 GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
0862 GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
0863 GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
0864 GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
0865 GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
0866 GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
0867 GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axisel_d4", 8),
0868 GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axisel_d4", 7),
0869 GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axisel_d4", 6),
0870 GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axisel_d4", 5),
0871 GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axisel_d4", 4),
0872 GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axisel_d4", 3),
0873 GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axisel_d4", 2),
0874 GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
0875 GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
0876
0877 GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
0878 GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
0879 GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
0880 GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
0881 GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
0882 GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
0883 GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
0884 GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
0885 GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
0886 GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
0887 GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
0888 GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
0889 };
0890
0891 static const char * const uart_ck_sel_parents[] = {
0892 "clk26m",
0893 "uart_sel",
0894 };
0895
0896 static const struct mtk_composite peri_muxs[] = {
0897 MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
0898 0x40c, 0, 1),
0899 MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
0900 0x40c, 1, 1),
0901 MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
0902 0x40c, 2, 1),
0903 MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
0904 0x40c, 3, 1),
0905 };
0906
0907 static int mtk_pericfg_init(struct platform_device *pdev)
0908 {
0909 struct clk_hw_onecell_data *clk_data;
0910 void __iomem *base;
0911 int r;
0912 struct device_node *node = pdev->dev.of_node;
0913 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0914
0915 base = devm_ioremap_resource(&pdev->dev, res);
0916 if (IS_ERR(base))
0917 return PTR_ERR(base);
0918
0919 clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
0920
0921 mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
0922 clk_data);
0923
0924 mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
0925 &mt2701_clk_lock, clk_data);
0926
0927 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0928 if (r)
0929 return r;
0930
0931 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc[1]);
0932
0933 return 0;
0934 }
0935
0936 #define MT8590_PLL_FMAX (2000 * MHZ)
0937 #define CON0_MT8590_RST_BAR BIT(27)
0938
0939 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
0940 _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift) { \
0941 .id = _id, \
0942 .name = _name, \
0943 .reg = _reg, \
0944 .pwr_reg = _pwr_reg, \
0945 .en_mask = _en_mask, \
0946 .flags = _flags, \
0947 .rst_bar_mask = CON0_MT8590_RST_BAR, \
0948 .fmax = MT8590_PLL_FMAX, \
0949 .pcwbits = _pcwbits, \
0950 .pd_reg = _pd_reg, \
0951 .pd_shift = _pd_shift, \
0952 .tuner_reg = _tuner_reg, \
0953 .pcw_reg = _pcw_reg, \
0954 .pcw_shift = _pcw_shift, \
0955 }
0956
0957 static const struct mtk_pll_data apmixed_plls[] = {
0958 PLL(CLK_APMIXED_ARMPLL, "armpll", 0x200, 0x20c, 0x80000000,
0959 PLL_AO, 21, 0x204, 24, 0x0, 0x204, 0),
0960 PLL(CLK_APMIXED_MAINPLL, "mainpll", 0x210, 0x21c, 0xf0000000,
0961 HAVE_RST_BAR, 21, 0x210, 4, 0x0, 0x214, 0),
0962 PLL(CLK_APMIXED_UNIVPLL, "univpll", 0x220, 0x22c, 0xf3000000,
0963 HAVE_RST_BAR, 7, 0x220, 4, 0x0, 0x224, 14),
0964 PLL(CLK_APMIXED_MMPLL, "mmpll", 0x230, 0x23c, 0, 0,
0965 21, 0x230, 4, 0x0, 0x234, 0),
0966 PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x240, 0x24c, 0x00000001, 0,
0967 21, 0x240, 4, 0x0, 0x244, 0),
0968 PLL(CLK_APMIXED_TVDPLL, "tvdpll", 0x250, 0x25c, 0x00000001, 0,
0969 21, 0x250, 4, 0x0, 0x254, 0),
0970 PLL(CLK_APMIXED_AUD1PLL, "aud1pll", 0x270, 0x27c, 0x00000001, 0,
0971 31, 0x270, 4, 0x0, 0x274, 0),
0972 PLL(CLK_APMIXED_TRGPLL, "trgpll", 0x280, 0x28c, 0x00000001, 0,
0973 31, 0x280, 4, 0x0, 0x284, 0),
0974 PLL(CLK_APMIXED_ETHPLL, "ethpll", 0x290, 0x29c, 0x00000001, 0,
0975 31, 0x290, 4, 0x0, 0x294, 0),
0976 PLL(CLK_APMIXED_VDECPLL, "vdecpll", 0x2a0, 0x2ac, 0x00000001, 0,
0977 31, 0x2a0, 4, 0x0, 0x2a4, 0),
0978 PLL(CLK_APMIXED_HADDS2PLL, "hadds2pll", 0x2b0, 0x2bc, 0x00000001, 0,
0979 31, 0x2b0, 4, 0x0, 0x2b4, 0),
0980 PLL(CLK_APMIXED_AUD2PLL, "aud2pll", 0x2c0, 0x2cc, 0x00000001, 0,
0981 31, 0x2c0, 4, 0x0, 0x2c4, 0),
0982 PLL(CLK_APMIXED_TVD2PLL, "tvd2pll", 0x2d0, 0x2dc, 0x00000001, 0,
0983 21, 0x2d0, 4, 0x0, 0x2d4, 0),
0984 };
0985
0986 static const struct mtk_fixed_factor apmixed_fixed_divs[] = {
0987 FACTOR(CLK_APMIXED_HDMI_REF, "hdmi_ref", "tvdpll", 1, 1),
0988 };
0989
0990 static int mtk_apmixedsys_init(struct platform_device *pdev)
0991 {
0992 struct clk_hw_onecell_data *clk_data;
0993 struct device_node *node = pdev->dev.of_node;
0994
0995 clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
0996 if (!clk_data)
0997 return -ENOMEM;
0998
0999 mtk_clk_register_plls(node, apmixed_plls, ARRAY_SIZE(apmixed_plls),
1000 clk_data);
1001 mtk_clk_register_factors(apmixed_fixed_divs, ARRAY_SIZE(apmixed_fixed_divs),
1002 clk_data);
1003
1004 return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
1005 }
1006
1007 static const struct of_device_id of_match_clk_mt2701[] = {
1008 {
1009 .compatible = "mediatek,mt2701-topckgen",
1010 .data = mtk_topckgen_init,
1011 }, {
1012 .compatible = "mediatek,mt2701-infracfg",
1013 .data = mtk_infrasys_init,
1014 }, {
1015 .compatible = "mediatek,mt2701-pericfg",
1016 .data = mtk_pericfg_init,
1017 }, {
1018 .compatible = "mediatek,mt2701-apmixedsys",
1019 .data = mtk_apmixedsys_init,
1020 }, {
1021
1022 }
1023 };
1024
1025 static int clk_mt2701_probe(struct platform_device *pdev)
1026 {
1027 int (*clk_init)(struct platform_device *);
1028 int r;
1029
1030 clk_init = of_device_get_match_data(&pdev->dev);
1031 if (!clk_init)
1032 return -EINVAL;
1033
1034 r = clk_init(pdev);
1035 if (r)
1036 dev_err(&pdev->dev,
1037 "could not register clock provider: %s: %d\n",
1038 pdev->name, r);
1039
1040 return r;
1041 }
1042
1043 static struct platform_driver clk_mt2701_drv = {
1044 .probe = clk_mt2701_probe,
1045 .driver = {
1046 .name = "clk-mt2701",
1047 .of_match_table = of_match_clk_mt2701,
1048 },
1049 };
1050
1051 static int __init clk_mt2701_init(void)
1052 {
1053 return platform_driver_register(&clk_mt2701_drv);
1054 }
1055
1056 arch_initcall(clk_mt2701_init);
