clk/mediatek/clk-mt2701-hif.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Shunli Wang <shunli.wang@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2701-clk.h>
0014
0015 static const struct mtk_gate_regs hif_cg_regs = {
0016     .sta_ofs = 0x0030,
0017 };
0018
0019 #define GATE_HIF(_id, _name, _parent, _shift) {     \
0020         .id = _id,              \
0021         .name = _name,              \
0022         .parent_name = _parent,         \
0023         .regs = &hif_cg_regs,           \
0024         .shift = _shift,            \
0025         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0026     }
0027
0028 static const struct mtk_gate hif_clks[] = {
0029     GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
0030     GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
0031     GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
0032     GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
0033     GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
0034 };
0035
0036 static u16 rst_ofs[] = { 0x34, };
0037
0038 static const struct mtk_clk_rst_desc clk_rst_desc = {
0039     .version = MTK_RST_SIMPLE,
0040     .rst_bank_ofs = rst_ofs,
0041     .rst_bank_nr = ARRAY_SIZE(rst_ofs),
0042 };
0043
0044 static const struct of_device_id of_match_clk_mt2701_hif[] = {
0045     { .compatible = "mediatek,mt2701-hifsys", },
0046     {}
0047 };
0048
0049 static int clk_mt2701_hif_probe(struct platform_device *pdev)
0050 {
0051     struct clk_hw_onecell_data *clk_data;
0052     int r;
0053     struct device_node *node = pdev->dev.of_node;
0054
0055     clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
0056
0057     mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
0058                         clk_data);
0059
0060     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0061     if (r) {
0062         dev_err(&pdev->dev,
0063             "could not register clock provider: %s: %d\n",
0064             pdev->name, r);
0065         return r;
0066     }
0067
0068     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0069
0070     return 0;
0071 }
0072
0073 static struct platform_driver clk_mt2701_hif_drv = {
0074     .probe = clk_mt2701_hif_probe,
0075     .driver = {
0076         .name = "clk-mt2701-hif",
0077         .of_match_table = of_match_clk_mt2701_hif,
0078     },
0079 };
0080
0081 builtin_platform_driver(clk_mt2701_hif_drv);