clk/mediatek/clk-mt2701-g3d.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  * Author: Sean Wang <sean.wang@mediatek.com>
0005  *
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/of.h>
0010 #include <linux/of_address.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013
0014 #include "clk-mtk.h"
0015 #include "clk-gate.h"
0016
0017 #include <dt-bindings/clock/mt2701-clk.h>
0018
0019 #define GATE_G3D(_id, _name, _parent, _shift) { \
0020         .id = _id,              \
0021         .name = _name,              \
0022         .parent_name = _parent,         \
0023         .regs = &g3d_cg_regs,           \
0024         .shift = _shift,            \
0025         .ops = &mtk_clk_gate_ops_setclr,    \
0026     }
0027
0028 static const struct mtk_gate_regs g3d_cg_regs = {
0029     .sta_ofs = 0x0,
0030     .set_ofs = 0x4,
0031     .clr_ofs = 0x8,
0032 };
0033
0034 static const struct mtk_gate g3d_clks[] = {
0035     GATE_G3D(CLK_G3DSYS_CORE, "g3d_core", "mfg_sel", 0),
0036 };
0037
0038 static u16 rst_ofs[] = { 0xc, };
0039
0040 static const struct mtk_clk_rst_desc clk_rst_desc = {
0041     .version = MTK_RST_SIMPLE,
0042     .rst_bank_ofs = rst_ofs,
0043     .rst_bank_nr = ARRAY_SIZE(rst_ofs),
0044 };
0045
0046 static int clk_mt2701_g3dsys_init(struct platform_device *pdev)
0047 {
0048     struct clk_hw_onecell_data *clk_data;
0049     struct device_node *node = pdev->dev.of_node;
0050     int r;
0051
0052     clk_data = mtk_alloc_clk_data(CLK_G3DSYS_NR);
0053
0054     mtk_clk_register_gates(node, g3d_clks, ARRAY_SIZE(g3d_clks),
0055                    clk_data);
0056
0057     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0058     if (r)
0059         dev_err(&pdev->dev,
0060             "could not register clock provider: %s: %d\n",
0061             pdev->name, r);
0062
0063     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0064
0065     return r;
0066 }
0067
0068 static const struct of_device_id of_match_clk_mt2701_g3d[] = {
0069     {
0070         .compatible = "mediatek,mt2701-g3dsys",
0071         .data = clk_mt2701_g3dsys_init,
0072     }, {
0073         /* sentinel */
0074     }
0075 };
0076
0077 static int clk_mt2701_g3d_probe(struct platform_device *pdev)
0078 {
0079     int (*clk_init)(struct platform_device *);
0080     int r;
0081
0082     clk_init = of_device_get_match_data(&pdev->dev);
0083     if (!clk_init)
0084         return -EINVAL;
0085
0086     r = clk_init(pdev);
0087     if (r)
0088         dev_err(&pdev->dev,
0089             "could not register clock provider: %s: %d\n",
0090             pdev->name, r);
0091
0092     return r;
0093 }
0094
0095 static struct platform_driver clk_mt2701_g3d_drv = {
0096     .probe = clk_mt2701_g3d_probe,
0097     .driver = {
0098         .name = "clk-mt2701-g3d",
0099         .of_match_table = of_match_clk_mt2701_g3d,
0100     },
0101 };
0102
0103 builtin_platform_driver(clk_mt2701_g3d_drv);