clk/mediatek/clk-mt2701-eth.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Shunli Wang <shunli.wang@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2701-clk.h>
0014
0015 static const struct mtk_gate_regs eth_cg_regs = {
0016     .sta_ofs = 0x0030,
0017 };
0018
0019 #define GATE_ETH(_id, _name, _parent, _shift) {     \
0020         .id = _id,              \
0021         .name = _name,              \
0022         .parent_name = _parent,         \
0023         .regs = &eth_cg_regs,           \
0024         .shift = _shift,            \
0025         .ops = &mtk_clk_gate_ops_no_setclr_inv, \
0026     }
0027
0028 static const struct mtk_gate eth_clks[] = {
0029     GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
0030     GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
0031     GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
0032     GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
0033     GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
0034     GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
0035     GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
0036     GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
0037 };
0038
0039 static u16 rst_ofs[] = { 0x34, };
0040
0041 static const struct mtk_clk_rst_desc clk_rst_desc = {
0042     .version = MTK_RST_SIMPLE,
0043     .rst_bank_ofs = rst_ofs,
0044     .rst_bank_nr = ARRAY_SIZE(rst_ofs),
0045 };
0046
0047 static const struct of_device_id of_match_clk_mt2701_eth[] = {
0048     { .compatible = "mediatek,mt2701-ethsys", },
0049     {}
0050 };
0051
0052 static int clk_mt2701_eth_probe(struct platform_device *pdev)
0053 {
0054     struct clk_hw_onecell_data *clk_data;
0055     int r;
0056     struct device_node *node = pdev->dev.of_node;
0057
0058     clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
0059
0060     mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
0061                         clk_data);
0062
0063     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0064     if (r)
0065         dev_err(&pdev->dev,
0066             "could not register clock provider: %s: %d\n",
0067             pdev->name, r);
0068
0069     mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
0070
0071     return r;
0072 }
0073
0074 static struct platform_driver clk_mt2701_eth_drv = {
0075     .probe = clk_mt2701_eth_probe,
0076     .driver = {
0077         .name = "clk-mt2701-eth",
0078         .of_match_table = of_match_clk_mt2701_eth,
0079     },
0080 };
0081
0082 builtin_platform_driver(clk_mt2701_eth_drv);