clk/mediatek/clk-mt2701-bdp.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 MediaTek Inc.
0004  * Author: Shunli Wang <shunli.wang@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/platform_device.h>
0009
0010 #include "clk-mtk.h"
0011 #include "clk-gate.h"
0012
0013 #include <dt-bindings/clock/mt2701-clk.h>
0014
0015 static const struct mtk_gate_regs bdp0_cg_regs = {
0016     .set_ofs = 0x0104,
0017     .clr_ofs = 0x0108,
0018     .sta_ofs = 0x0100,
0019 };
0020
0021 static const struct mtk_gate_regs bdp1_cg_regs = {
0022     .set_ofs = 0x0114,
0023     .clr_ofs = 0x0118,
0024     .sta_ofs = 0x0110,
0025 };
0026
0027 #define GATE_BDP0(_id, _name, _parent, _shift) {    \
0028         .id = _id,              \
0029         .name = _name,              \
0030         .parent_name = _parent,         \
0031         .regs = &bdp0_cg_regs,          \
0032         .shift = _shift,            \
0033         .ops = &mtk_clk_gate_ops_setclr_inv,    \
0034     }
0035
0036 #define GATE_BDP1(_id, _name, _parent, _shift) {    \
0037         .id = _id,              \
0038         .name = _name,              \
0039         .parent_name = _parent,         \
0040         .regs = &bdp1_cg_regs,          \
0041         .shift = _shift,            \
0042         .ops = &mtk_clk_gate_ops_setclr_inv,    \
0043     }
0044
0045 static const struct mtk_gate bdp_clks[] = {
0046     GATE_BDP0(CLK_BDP_BRG_BA, "brg_baclk", "mm_sel", 0),
0047     GATE_BDP0(CLK_BDP_BRG_DRAM, "brg_dram", "mm_sel", 1),
0048     GATE_BDP0(CLK_BDP_LARB_DRAM, "larb_dram", "mm_sel", 2),
0049     GATE_BDP0(CLK_BDP_WR_VDI_PXL, "wr_vdi_pxl", "hdmi_0_deep340m", 3),
0050     GATE_BDP0(CLK_BDP_WR_VDI_DRAM, "wr_vdi_dram", "mm_sel", 4),
0051     GATE_BDP0(CLK_BDP_WR_B, "wr_bclk", "mm_sel", 5),
0052     GATE_BDP0(CLK_BDP_DGI_IN, "dgi_in", "dpi1_sel", 6),
0053     GATE_BDP0(CLK_BDP_DGI_OUT, "dgi_out", "dpi1_sel", 7),
0054     GATE_BDP0(CLK_BDP_FMT_MAST_27, "fmt_mast_27", "dpi1_sel", 8),
0055     GATE_BDP0(CLK_BDP_FMT_B, "fmt_bclk", "mm_sel", 9),
0056     GATE_BDP0(CLK_BDP_OSD_B, "osd_bclk", "mm_sel", 10),
0057     GATE_BDP0(CLK_BDP_OSD_DRAM, "osd_dram", "mm_sel", 11),
0058     GATE_BDP0(CLK_BDP_OSD_AGENT, "osd_agent", "osd_sel", 12),
0059     GATE_BDP0(CLK_BDP_OSD_PXL, "osd_pxl", "dpi1_sel", 13),
0060     GATE_BDP0(CLK_BDP_RLE_B, "rle_bclk", "mm_sel", 14),
0061     GATE_BDP0(CLK_BDP_RLE_AGENT, "rle_agent", "mm_sel", 15),
0062     GATE_BDP0(CLK_BDP_RLE_DRAM, "rle_dram", "mm_sel", 16),
0063     GATE_BDP0(CLK_BDP_F27M, "f27m", "di_sel", 17),
0064     GATE_BDP0(CLK_BDP_F27M_VDOUT, "f27m_vdout", "di_sel", 18),
0065     GATE_BDP0(CLK_BDP_F27_74_74, "f27_74_74", "di_sel", 19),
0066     GATE_BDP0(CLK_BDP_F2FS, "f2fs", "di_sel", 20),
0067     GATE_BDP0(CLK_BDP_F2FS74_148, "f2fs74_148", "di_sel", 21),
0068     GATE_BDP0(CLK_BDP_FB, "fbclk", "mm_sel", 22),
0069     GATE_BDP0(CLK_BDP_VDO_DRAM, "vdo_dram", "mm_sel", 23),
0070     GATE_BDP0(CLK_BDP_VDO_2FS, "vdo_2fs", "di_sel", 24),
0071     GATE_BDP0(CLK_BDP_VDO_B, "vdo_bclk", "mm_sel", 25),
0072     GATE_BDP0(CLK_BDP_WR_DI_PXL, "wr_di_pxl", "di_sel", 26),
0073     GATE_BDP0(CLK_BDP_WR_DI_DRAM, "wr_di_dram", "mm_sel", 27),
0074     GATE_BDP0(CLK_BDP_WR_DI_B, "wr_di_bclk", "mm_sel", 28),
0075     GATE_BDP0(CLK_BDP_NR_PXL, "nr_pxl", "nr_sel", 29),
0076     GATE_BDP0(CLK_BDP_NR_DRAM, "nr_dram", "mm_sel", 30),
0077     GATE_BDP0(CLK_BDP_NR_B, "nr_bclk", "mm_sel", 31),
0078     GATE_BDP1(CLK_BDP_RX_F, "rx_fclk", "hadds2_fbclk", 0),
0079     GATE_BDP1(CLK_BDP_RX_X, "rx_xclk", "clk26m", 1),
0080     GATE_BDP1(CLK_BDP_RXPDT, "rxpdtclk", "hdmi_0_pix340m", 2),
0081     GATE_BDP1(CLK_BDP_RX_CSCL_N, "rx_cscl_n", "clk26m", 3),
0082     GATE_BDP1(CLK_BDP_RX_CSCL, "rx_cscl", "clk26m", 4),
0083     GATE_BDP1(CLK_BDP_RX_DDCSCL_N, "rx_ddcscl_n", "hdmi_scl_rx", 5),
0084     GATE_BDP1(CLK_BDP_RX_DDCSCL, "rx_ddcscl", "hdmi_scl_rx", 6),
0085     GATE_BDP1(CLK_BDP_RX_VCO, "rx_vcoclk", "hadds2pll_294m", 7),
0086     GATE_BDP1(CLK_BDP_RX_DP, "rx_dpclk", "hdmi_0_pll340m", 8),
0087     GATE_BDP1(CLK_BDP_RX_P, "rx_pclk", "hdmi_0_pll340m", 9),
0088     GATE_BDP1(CLK_BDP_RX_M, "rx_mclk", "hadds2pll_294m", 10),
0089     GATE_BDP1(CLK_BDP_RX_PLL, "rx_pllclk", "hdmi_0_pix340m", 11),
0090     GATE_BDP1(CLK_BDP_BRG_RT_B, "brg_rt_bclk", "mm_sel", 12),
0091     GATE_BDP1(CLK_BDP_BRG_RT_DRAM, "brg_rt_dram", "mm_sel", 13),
0092     GATE_BDP1(CLK_BDP_LARBRT_DRAM, "larbrt_dram", "mm_sel", 14),
0093     GATE_BDP1(CLK_BDP_TMDS_SYN, "tmds_syn", "hdmi_0_pll340m", 15),
0094     GATE_BDP1(CLK_BDP_HDMI_MON, "hdmi_mon", "hdmi_0_pll340m", 16),
0095 };
0096
0097 static const struct of_device_id of_match_clk_mt2701_bdp[] = {
0098     { .compatible = "mediatek,mt2701-bdpsys", },
0099     {}
0100 };
0101
0102 static int clk_mt2701_bdp_probe(struct platform_device *pdev)
0103 {
0104     struct clk_hw_onecell_data *clk_data;
0105     int r;
0106     struct device_node *node = pdev->dev.of_node;
0107
0108     clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
0109
0110     mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
0111                         clk_data);
0112
0113     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0114     if (r)
0115         dev_err(&pdev->dev,
0116             "could not register clock provider: %s: %d\n",
0117             pdev->name, r);
0118
0119     return r;
0120 }
0121
0122 static struct platform_driver clk_mt2701_bdp_drv = {
0123     .probe = clk_mt2701_bdp_probe,
0124     .driver = {
0125         .name = "clk-mt2701-bdp",
0126         .of_match_table = of_match_clk_mt2701_bdp,
0127     },
0128 };
0129
0130 builtin_platform_driver(clk_mt2701_bdp_drv);