clk/mediatek/clk-mt2701-aud.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (c) 2018 MediaTek Inc.
0004  * Author: Ryder Lee <ryder.lee@mediatek.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_device.h>
0011 #include <linux/platform_device.h>
0012
0013 #include "clk-mtk.h"
0014 #include "clk-gate.h"
0015
0016 #include <dt-bindings/clock/mt2701-clk.h>
0017
0018 #define GATE_AUDIO0(_id, _name, _parent, _shift) {  \
0019         .id = _id,              \
0020         .name = _name,              \
0021         .parent_name = _parent,         \
0022         .regs = &audio0_cg_regs,            \
0023         .shift = _shift,            \
0024         .ops = &mtk_clk_gate_ops_no_setclr, \
0025     }
0026
0027 #define GATE_AUDIO1(_id, _name, _parent, _shift) {  \
0028         .id = _id,              \
0029         .name = _name,              \
0030         .parent_name = _parent,         \
0031         .regs = &audio1_cg_regs,            \
0032         .shift = _shift,            \
0033         .ops = &mtk_clk_gate_ops_no_setclr, \
0034     }
0035
0036 #define GATE_AUDIO2(_id, _name, _parent, _shift) {  \
0037         .id = _id,              \
0038         .name = _name,              \
0039         .parent_name = _parent,         \
0040         .regs = &audio2_cg_regs,            \
0041         .shift = _shift,            \
0042         .ops = &mtk_clk_gate_ops_no_setclr, \
0043     }
0044
0045 #define GATE_AUDIO3(_id, _name, _parent, _shift) {  \
0046         .id = _id,              \
0047         .name = _name,              \
0048         .parent_name = _parent,         \
0049         .regs = &audio3_cg_regs,            \
0050         .shift = _shift,            \
0051         .ops = &mtk_clk_gate_ops_no_setclr, \
0052     }
0053
0054 static const struct mtk_gate_regs audio0_cg_regs = {
0055     .set_ofs = 0x0,
0056     .clr_ofs = 0x0,
0057     .sta_ofs = 0x0,
0058 };
0059
0060 static const struct mtk_gate_regs audio1_cg_regs = {
0061     .set_ofs = 0x10,
0062     .clr_ofs = 0x10,
0063     .sta_ofs = 0x10,
0064 };
0065
0066 static const struct mtk_gate_regs audio2_cg_regs = {
0067     .set_ofs = 0x14,
0068     .clr_ofs = 0x14,
0069     .sta_ofs = 0x14,
0070 };
0071
0072 static const struct mtk_gate_regs audio3_cg_regs = {
0073     .set_ofs = 0x634,
0074     .clr_ofs = 0x634,
0075     .sta_ofs = 0x634,
0076 };
0077
0078 static const struct mtk_gate audio_clks[] = {
0079     /* AUDIO0 */
0080     GATE_AUDIO0(CLK_AUD_AFE, "audio_afe", "aud_intbus_sel", 2),
0081     GATE_AUDIO0(CLK_AUD_HDMI, "audio_hdmi", "audpll_sel", 20),
0082     GATE_AUDIO0(CLK_AUD_SPDF, "audio_spdf", "audpll_sel", 21),
0083     GATE_AUDIO0(CLK_AUD_SPDF2, "audio_spdf2", "audpll_sel", 22),
0084     GATE_AUDIO0(CLK_AUD_APLL, "audio_apll", "audpll_sel", 23),
0085     /* AUDIO1 */
0086     GATE_AUDIO1(CLK_AUD_I2SIN1, "audio_i2sin1", "aud_mux1_sel", 0),
0087     GATE_AUDIO1(CLK_AUD_I2SIN2, "audio_i2sin2", "aud_mux1_sel", 1),
0088     GATE_AUDIO1(CLK_AUD_I2SIN3, "audio_i2sin3", "aud_mux1_sel", 2),
0089     GATE_AUDIO1(CLK_AUD_I2SIN4, "audio_i2sin4", "aud_mux1_sel", 3),
0090     GATE_AUDIO1(CLK_AUD_I2SIN5, "audio_i2sin5", "aud_mux1_sel", 4),
0091     GATE_AUDIO1(CLK_AUD_I2SIN6, "audio_i2sin6", "aud_mux1_sel", 5),
0092     GATE_AUDIO1(CLK_AUD_I2SO1, "audio_i2so1", "aud_mux1_sel", 6),
0093     GATE_AUDIO1(CLK_AUD_I2SO2, "audio_i2so2", "aud_mux1_sel", 7),
0094     GATE_AUDIO1(CLK_AUD_I2SO3, "audio_i2so3", "aud_mux1_sel", 8),
0095     GATE_AUDIO1(CLK_AUD_I2SO4, "audio_i2so4", "aud_mux1_sel", 9),
0096     GATE_AUDIO1(CLK_AUD_I2SO5, "audio_i2so5", "aud_mux1_sel", 10),
0097     GATE_AUDIO1(CLK_AUD_I2SO6, "audio_i2so6", "aud_mux1_sel", 11),
0098     GATE_AUDIO1(CLK_AUD_ASRCI1, "audio_asrci1", "asm_h_sel", 12),
0099     GATE_AUDIO1(CLK_AUD_ASRCI2, "audio_asrci2", "asm_h_sel", 13),
0100     GATE_AUDIO1(CLK_AUD_ASRCO1, "audio_asrco1", "asm_h_sel", 14),
0101     GATE_AUDIO1(CLK_AUD_ASRCO2, "audio_asrco2", "asm_h_sel", 15),
0102     GATE_AUDIO1(CLK_AUD_INTDIR, "audio_intdir", "intdir_sel", 20),
0103     GATE_AUDIO1(CLK_AUD_A1SYS, "audio_a1sys", "aud_mux1_sel", 21),
0104     GATE_AUDIO1(CLK_AUD_A2SYS, "audio_a2sys", "aud_mux2_sel", 22),
0105     GATE_AUDIO1(CLK_AUD_AFE_CONN, "audio_afe_conn", "aud_mux1_sel", 23),
0106     GATE_AUDIO1(CLK_AUD_AFE_MRGIF, "audio_afe_mrgif", "aud_mux1_sel", 25),
0107     /* AUDIO2 */
0108     GATE_AUDIO2(CLK_AUD_MMIF_UL1, "audio_ul1", "aud_mux1_sel", 0),
0109     GATE_AUDIO2(CLK_AUD_MMIF_UL2, "audio_ul2", "aud_mux1_sel", 1),
0110     GATE_AUDIO2(CLK_AUD_MMIF_UL3, "audio_ul3", "aud_mux1_sel", 2),
0111     GATE_AUDIO2(CLK_AUD_MMIF_UL4, "audio_ul4", "aud_mux1_sel", 3),
0112     GATE_AUDIO2(CLK_AUD_MMIF_UL5, "audio_ul5", "aud_mux1_sel", 4),
0113     GATE_AUDIO2(CLK_AUD_MMIF_UL6, "audio_ul6", "aud_mux1_sel", 5),
0114     GATE_AUDIO2(CLK_AUD_MMIF_DL1, "audio_dl1", "aud_mux1_sel", 6),
0115     GATE_AUDIO2(CLK_AUD_MMIF_DL2, "audio_dl2", "aud_mux1_sel", 7),
0116     GATE_AUDIO2(CLK_AUD_MMIF_DL3, "audio_dl3", "aud_mux1_sel", 8),
0117     GATE_AUDIO2(CLK_AUD_MMIF_DL4, "audio_dl4", "aud_mux1_sel", 9),
0118     GATE_AUDIO2(CLK_AUD_MMIF_DL5, "audio_dl5", "aud_mux1_sel", 10),
0119     GATE_AUDIO2(CLK_AUD_MMIF_DL6, "audio_dl6", "aud_mux1_sel", 11),
0120     GATE_AUDIO2(CLK_AUD_MMIF_DLMCH, "audio_dlmch", "aud_mux1_sel", 12),
0121     GATE_AUDIO2(CLK_AUD_MMIF_ARB1, "audio_arb1", "aud_mux1_sel", 13),
0122     GATE_AUDIO2(CLK_AUD_MMIF_AWB1, "audio_awb", "aud_mux1_sel", 14),
0123     GATE_AUDIO2(CLK_AUD_MMIF_AWB2, "audio_awb2", "aud_mux1_sel", 15),
0124     GATE_AUDIO2(CLK_AUD_MMIF_DAI, "audio_dai", "aud_mux1_sel", 16),
0125     /* AUDIO3 */
0126     GATE_AUDIO3(CLK_AUD_ASRCI3, "audio_asrci3", "asm_h_sel", 2),
0127     GATE_AUDIO3(CLK_AUD_ASRCI4, "audio_asrci4", "asm_h_sel", 3),
0128     GATE_AUDIO3(CLK_AUD_ASRCI5, "audio_asrci5", "asm_h_sel", 4),
0129     GATE_AUDIO3(CLK_AUD_ASRCI6, "audio_asrci6", "asm_h_sel", 5),
0130     GATE_AUDIO3(CLK_AUD_ASRCO3, "audio_asrco3", "asm_h_sel", 6),
0131     GATE_AUDIO3(CLK_AUD_ASRCO4, "audio_asrco4", "asm_h_sel", 7),
0132     GATE_AUDIO3(CLK_AUD_ASRCO5, "audio_asrco5", "asm_h_sel", 8),
0133     GATE_AUDIO3(CLK_AUD_ASRCO6, "audio_asrco6", "asm_h_sel", 9),
0134     GATE_AUDIO3(CLK_AUD_MEM_ASRC1, "audio_mem_asrc1", "asm_h_sel", 10),
0135     GATE_AUDIO3(CLK_AUD_MEM_ASRC2, "audio_mem_asrc2", "asm_h_sel", 11),
0136     GATE_AUDIO3(CLK_AUD_MEM_ASRC3, "audio_mem_asrc3", "asm_h_sel", 12),
0137     GATE_AUDIO3(CLK_AUD_MEM_ASRC4, "audio_mem_asrc4", "asm_h_sel", 13),
0138     GATE_AUDIO3(CLK_AUD_MEM_ASRC5, "audio_mem_asrc5", "asm_h_sel", 14),
0139 };
0140
0141 static const struct of_device_id of_match_clk_mt2701_aud[] = {
0142     { .compatible = "mediatek,mt2701-audsys", },
0143     {}
0144 };
0145
0146 static int clk_mt2701_aud_probe(struct platform_device *pdev)
0147 {
0148     struct clk_hw_onecell_data *clk_data;
0149     struct device_node *node = pdev->dev.of_node;
0150     int r;
0151
0152     clk_data = mtk_alloc_clk_data(CLK_AUD_NR);
0153
0154     mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
0155                    clk_data);
0156
0157     r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
0158     if (r) {
0159         dev_err(&pdev->dev,
0160             "could not register clock provider: %s: %d\n",
0161             pdev->name, r);
0162
0163         goto err_clk_provider;
0164     }
0165
0166     r = devm_of_platform_populate(&pdev->dev);
0167     if (r)
0168         goto err_plat_populate;
0169
0170     return 0;
0171
0172 err_plat_populate:
0173     of_clk_del_provider(node);
0174 err_clk_provider:
0175     return r;
0176 }
0177
0178 static struct platform_driver clk_mt2701_aud_drv = {
0179     .probe = clk_mt2701_aud_probe,
0180     .driver = {
0181         .name = "clk-mt2701-aud",
0182         .of_match_table = of_match_clk_mt2701_aud,
0183     },
0184 };
0185
0186 builtin_platform_driver(clk_mt2701_aud_drv);