clk/loongson1/clk-loongson1c.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (c) 2016 Yang Ling <gnaygnil@gmail.com>
0004  */
0005
0006 #include <linux/clkdev.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/io.h>
0009
0010 #include <loongson1.h>
0011 #include "clk.h"
0012
0013 #define OSC     (24 * 1000000)
0014 #define DIV_APB     1
0015
0016 static DEFINE_SPINLOCK(_lock);
0017
0018 static unsigned long ls1x_pll_recalc_rate(struct clk_hw *hw,
0019                       unsigned long parent_rate)
0020 {
0021     u32 pll, rate;
0022
0023     pll = __raw_readl(LS1X_CLK_PLL_FREQ);
0024     rate = ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
0025     rate *= OSC;
0026     rate >>= 2;
0027
0028     return rate;
0029 }
0030
0031 static const struct clk_ops ls1x_pll_clk_ops = {
0032     .recalc_rate = ls1x_pll_recalc_rate,
0033 };
0034
0035 static const struct clk_div_table ahb_div_table[] = {
0036     [0] = { .val = 0, .div = 2 },
0037     [1] = { .val = 1, .div = 4 },
0038     [2] = { .val = 2, .div = 3 },
0039     [3] = { .val = 3, .div = 3 },
0040     [4] = { /* sentinel */ }
0041 };
0042
0043 void __init ls1x_clk_init(void)
0044 {
0045     struct clk_hw *hw;
0046
0047     hw = clk_hw_register_fixed_rate(NULL, "osc_clk", NULL, 0, OSC);
0048     clk_hw_register_clkdev(hw, "osc_clk", NULL);
0049
0050     /* clock derived from 24 MHz OSC clk */
0051     hw = clk_hw_register_pll(NULL, "pll_clk", "osc_clk",
0052                 &ls1x_pll_clk_ops, 0);
0053     clk_hw_register_clkdev(hw, "pll_clk", NULL);
0054
0055     hw = clk_hw_register_divider(NULL, "cpu_clk_div", "pll_clk",
0056                    CLK_GET_RATE_NOCACHE, LS1X_CLK_PLL_DIV,
0057                    DIV_CPU_SHIFT, DIV_CPU_WIDTH,
0058                    CLK_DIVIDER_ONE_BASED |
0059                    CLK_DIVIDER_ROUND_CLOSEST, &_lock);
0060     clk_hw_register_clkdev(hw, "cpu_clk_div", NULL);
0061     hw = clk_hw_register_fixed_factor(NULL, "cpu_clk", "cpu_clk_div",
0062                     0, 1, 1);
0063     clk_hw_register_clkdev(hw, "cpu_clk", NULL);
0064
0065     hw = clk_hw_register_divider(NULL, "dc_clk_div", "pll_clk",
0066                    0, LS1X_CLK_PLL_DIV, DIV_DC_SHIFT,
0067                    DIV_DC_WIDTH, CLK_DIVIDER_ONE_BASED, &_lock);
0068     clk_hw_register_clkdev(hw, "dc_clk_div", NULL);
0069     hw = clk_hw_register_fixed_factor(NULL, "dc_clk", "dc_clk_div",
0070                     0, 1, 1);
0071     clk_hw_register_clkdev(hw, "dc_clk", NULL);
0072
0073     hw = clk_hw_register_divider_table(NULL, "ahb_clk_div", "cpu_clk_div",
0074                 0, LS1X_CLK_PLL_FREQ, DIV_DDR_SHIFT,
0075                 DIV_DDR_WIDTH, CLK_DIVIDER_ALLOW_ZERO,
0076                 ahb_div_table, &_lock);
0077     clk_hw_register_clkdev(hw, "ahb_clk_div", NULL);
0078     hw = clk_hw_register_fixed_factor(NULL, "ahb_clk", "ahb_clk_div",
0079                     0, 1, 1);
0080     clk_hw_register_clkdev(hw, "ahb_clk", NULL);
0081     clk_hw_register_clkdev(hw, "ls1x-dma", NULL);
0082     clk_hw_register_clkdev(hw, "stmmaceth", NULL);
0083
0084     /* clock derived from AHB clk */
0085     hw = clk_hw_register_fixed_factor(NULL, "apb_clk", "ahb_clk", 0, 1,
0086                     DIV_APB);
0087     clk_hw_register_clkdev(hw, "apb_clk", NULL);
0088     clk_hw_register_clkdev(hw, "ls1x-ac97", NULL);
0089     clk_hw_register_clkdev(hw, "ls1x-i2c", NULL);
0090     clk_hw_register_clkdev(hw, "ls1x-nand", NULL);
0091     clk_hw_register_clkdev(hw, "ls1x-pwmtimer", NULL);
0092     clk_hw_register_clkdev(hw, "ls1x-spi", NULL);
0093     clk_hw_register_clkdev(hw, "ls1x-wdt", NULL);
0094     clk_hw_register_clkdev(hw, "serial8250", NULL);
0095 }