clk/keystone/syscon-clk.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/mfd/syscon.h>
0008 #include <linux/module.h>
0009 #include <linux/platform_device.h>
0010 #include <linux/regmap.h>
0011
0012 struct ti_syscon_gate_clk_priv {
0013     struct clk_hw hw;
0014     struct regmap *regmap;
0015     u32 reg;
0016     u32 idx;
0017 };
0018
0019 struct ti_syscon_gate_clk_data {
0020     char *name;
0021     u32 offset;
0022     u32 bit_idx;
0023 };
0024
0025 static struct
0026 ti_syscon_gate_clk_priv *to_ti_syscon_gate_clk_priv(struct clk_hw *hw)
0027 {
0028     return container_of(hw, struct ti_syscon_gate_clk_priv, hw);
0029 }
0030
0031 static int ti_syscon_gate_clk_enable(struct clk_hw *hw)
0032 {
0033     struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw);
0034
0035     return regmap_write_bits(priv->regmap, priv->reg, priv->idx,
0036                  priv->idx);
0037 }
0038
0039 static void ti_syscon_gate_clk_disable(struct clk_hw *hw)
0040 {
0041     struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw);
0042
0043     regmap_write_bits(priv->regmap, priv->reg, priv->idx, 0);
0044 }
0045
0046 static int ti_syscon_gate_clk_is_enabled(struct clk_hw *hw)
0047 {
0048     unsigned int val;
0049     struct ti_syscon_gate_clk_priv *priv = to_ti_syscon_gate_clk_priv(hw);
0050
0051     regmap_read(priv->regmap, priv->reg, &val);
0052
0053     return !!(val & priv->idx);
0054 }
0055
0056 static const struct clk_ops ti_syscon_gate_clk_ops = {
0057     .enable     = ti_syscon_gate_clk_enable,
0058     .disable    = ti_syscon_gate_clk_disable,
0059     .is_enabled = ti_syscon_gate_clk_is_enabled,
0060 };
0061
0062 static struct clk_hw
0063 *ti_syscon_gate_clk_register(struct device *dev, struct regmap *regmap,
0064                  const struct ti_syscon_gate_clk_data *data)
0065 {
0066     struct ti_syscon_gate_clk_priv *priv;
0067     struct clk_init_data init;
0068     int ret;
0069
0070     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0071     if (!priv)
0072         return ERR_PTR(-ENOMEM);
0073
0074     init.name = data->name;
0075     init.ops = &ti_syscon_gate_clk_ops;
0076     init.parent_names = NULL;
0077     init.num_parents = 0;
0078     init.flags = 0;
0079
0080     priv->regmap = regmap;
0081     priv->reg = data->offset;
0082     priv->idx = BIT(data->bit_idx);
0083     priv->hw.init = &init;
0084
0085     ret = devm_clk_hw_register(dev, &priv->hw);
0086     if (ret)
0087         return ERR_PTR(ret);
0088
0089     return &priv->hw;
0090 }
0091
0092 static int ti_syscon_gate_clk_probe(struct platform_device *pdev)
0093 {
0094     const struct ti_syscon_gate_clk_data *data, *p;
0095     struct clk_hw_onecell_data *hw_data;
0096     struct device *dev = &pdev->dev;
0097     struct regmap *regmap;
0098     int num_clks, i;
0099
0100     data = device_get_match_data(dev);
0101     if (!data)
0102         return -EINVAL;
0103
0104     regmap = syscon_node_to_regmap(dev->of_node);
0105     if (IS_ERR(regmap)) {
0106         if (PTR_ERR(regmap) == -EPROBE_DEFER)
0107             return -EPROBE_DEFER;
0108         dev_err(dev, "failed to find parent regmap\n");
0109         return PTR_ERR(regmap);
0110     }
0111
0112     num_clks = 0;
0113     for (p = data; p->name; p++)
0114         num_clks++;
0115
0116     hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks),
0117                    GFP_KERNEL);
0118     if (!hw_data)
0119         return -ENOMEM;
0120
0121     hw_data->num = num_clks;
0122
0123     for (i = 0; i < num_clks; i++) {
0124         hw_data->hws[i] = ti_syscon_gate_clk_register(dev, regmap,
0125                                   &data[i]);
0126         if (IS_ERR(hw_data->hws[i]))
0127             dev_warn(dev, "failed to register %s\n",
0128                  data[i].name);
0129     }
0130
0131     return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
0132                        hw_data);
0133 }
0134
0135 #define TI_SYSCON_CLK_GATE(_name, _offset, _bit_idx)    \
0136     {                       \
0137         .name = _name,              \
0138         .offset = (_offset),            \
0139         .bit_idx = (_bit_idx),          \
0140     }
0141
0142 static const struct ti_syscon_gate_clk_data am654_clk_data[] = {
0143     TI_SYSCON_CLK_GATE("ehrpwm_tbclk0", 0x0, 0),
0144     TI_SYSCON_CLK_GATE("ehrpwm_tbclk1", 0x4, 0),
0145     TI_SYSCON_CLK_GATE("ehrpwm_tbclk2", 0x8, 0),
0146     TI_SYSCON_CLK_GATE("ehrpwm_tbclk3", 0xc, 0),
0147     TI_SYSCON_CLK_GATE("ehrpwm_tbclk4", 0x10, 0),
0148     TI_SYSCON_CLK_GATE("ehrpwm_tbclk5", 0x14, 0),
0149     { /* Sentinel */ },
0150 };
0151
0152 static const struct ti_syscon_gate_clk_data am64_clk_data[] = {
0153     TI_SYSCON_CLK_GATE("epwm_tbclk0", 0x0, 0),
0154     TI_SYSCON_CLK_GATE("epwm_tbclk1", 0x0, 1),
0155     TI_SYSCON_CLK_GATE("epwm_tbclk2", 0x0, 2),
0156     TI_SYSCON_CLK_GATE("epwm_tbclk3", 0x0, 3),
0157     TI_SYSCON_CLK_GATE("epwm_tbclk4", 0x0, 4),
0158     TI_SYSCON_CLK_GATE("epwm_tbclk5", 0x0, 5),
0159     TI_SYSCON_CLK_GATE("epwm_tbclk6", 0x0, 6),
0160     TI_SYSCON_CLK_GATE("epwm_tbclk7", 0x0, 7),
0161     TI_SYSCON_CLK_GATE("epwm_tbclk8", 0x0, 8),
0162     { /* Sentinel */ },
0163 };
0164
0165 static const struct ti_syscon_gate_clk_data am62_clk_data[] = {
0166     TI_SYSCON_CLK_GATE("epwm_tbclk0", 0x0, 0),
0167     TI_SYSCON_CLK_GATE("epwm_tbclk1", 0x0, 1),
0168     TI_SYSCON_CLK_GATE("epwm_tbclk2", 0x0, 2),
0169     { /* Sentinel */ },
0170 };
0171
0172 static const struct of_device_id ti_syscon_gate_clk_ids[] = {
0173     {
0174         .compatible = "ti,am654-ehrpwm-tbclk",
0175         .data = &am654_clk_data,
0176     },
0177     {
0178         .compatible = "ti,am64-epwm-tbclk",
0179         .data = &am64_clk_data,
0180     },
0181     {
0182         .compatible = "ti,am62-epwm-tbclk",
0183         .data = &am62_clk_data,
0184     },
0185     { }
0186 };
0187 MODULE_DEVICE_TABLE(of, ti_syscon_gate_clk_ids);
0188
0189 static struct platform_driver ti_syscon_gate_clk_driver = {
0190     .probe = ti_syscon_gate_clk_probe,
0191     .driver = {
0192         .name = "ti-syscon-gate-clk",
0193         .of_match_table = ti_syscon_gate_clk_ids,
0194     },
0195 };
0196 module_platform_driver(ti_syscon_gate_clk_driver);
0197
0198 MODULE_AUTHOR("Vignesh Raghavendra <vigneshr@ti.com>");
0199 MODULE_DESCRIPTION("Syscon backed gate-clock driver");
0200 MODULE_LICENSE("GPL");