clk/keystone/pll.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * PLL clock driver for Keystone devices
0004  *
0005  * Copyright (C) 2013 Texas Instruments Inc.
0006  *  Murali Karicheri <m-karicheri2@ti.com>
0007  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
0008  */
0009 #include <linux/clk-provider.h>
0010 #include <linux/err.h>
0011 #include <linux/io.h>
0012 #include <linux/slab.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of.h>
0015 #include <linux/module.h>
0016
0017 #define PLLM_LOW_MASK       0x3f
0018 #define PLLM_HIGH_MASK      0x7ffc0
0019 #define MAIN_PLLM_HIGH_MASK 0x7f000
0020 #define PLLM_HIGH_SHIFT     6
0021 #define PLLD_MASK       0x3f
0022 #define CLKOD_MASK      0x780000
0023 #define CLKOD_SHIFT     19
0024
0025 /**
0026  * struct clk_pll_data - pll data structure
0027  * @has_pllctrl: If set to non zero, lower 6 bits of multiplier is in pllm
0028  *  register of pll controller, else it is in the pll_ctrl0((bit 11-6)
0029  * @phy_pllm: Physical address of PLLM in pll controller. Used when
0030  *  has_pllctrl is non zero.
0031  * @phy_pll_ctl0: Physical address of PLL ctrl0. This could be that of
0032  *  Main PLL or any other PLLs in the device such as ARM PLL, DDR PLL
0033  *  or PA PLL available on keystone2. These PLLs are controlled by
0034  *  this register. Main PLL is controlled by a PLL controller.
0035  * @pllm: PLL register map address for multiplier bits
0036  * @pllod: PLL register map address for post divider bits
0037  * @pll_ctl0: PLL controller map address
0038  * @pllm_lower_mask: multiplier lower mask
0039  * @pllm_upper_mask: multiplier upper mask
0040  * @pllm_upper_shift: multiplier upper shift
0041  * @plld_mask: divider mask
0042  * @clkod_mask: output divider mask
0043  * @clkod_shift: output divider shift
0044  * @plld_mask: divider mask
0045  * @postdiv: Fixed post divider
0046  */
0047 struct clk_pll_data {
0048     bool has_pllctrl;
0049     u32 phy_pllm;
0050     u32 phy_pll_ctl0;
0051     void __iomem *pllm;
0052     void __iomem *pllod;
0053     void __iomem *pll_ctl0;
0054     u32 pllm_lower_mask;
0055     u32 pllm_upper_mask;
0056     u32 pllm_upper_shift;
0057     u32 plld_mask;
0058     u32 clkod_mask;
0059     u32 clkod_shift;
0060     u32 postdiv;
0061 };
0062
0063 /**
0064  * struct clk_pll - Main pll clock
0065  * @hw: clk_hw for the pll
0066  * @pll_data: PLL driver specific data
0067  */
0068 struct clk_pll {
0069     struct clk_hw hw;
0070     struct clk_pll_data *pll_data;
0071 };
0072
0073 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
0074
0075 static unsigned long clk_pllclk_recalc(struct clk_hw *hw,
0076                     unsigned long parent_rate)
0077 {
0078     struct clk_pll *pll = to_clk_pll(hw);
0079     struct clk_pll_data *pll_data = pll->pll_data;
0080     unsigned long rate = parent_rate;
0081     u32  mult = 0, prediv, postdiv, val;
0082
0083     /*
0084      * get bits 0-5 of multiplier from pllctrl PLLM register
0085      * if has_pllctrl is non zero
0086      */
0087     if (pll_data->has_pllctrl) {
0088         val = readl(pll_data->pllm);
0089         mult = (val & pll_data->pllm_lower_mask);
0090     }
0091
0092     /* bit6-12 of PLLM is in Main PLL control register */
0093     val = readl(pll_data->pll_ctl0);
0094     mult |= ((val & pll_data->pllm_upper_mask)
0095             >> pll_data->pllm_upper_shift);
0096     prediv = (val & pll_data->plld_mask);
0097
0098     if (!pll_data->has_pllctrl)
0099         /* read post divider from od bits*/
0100         postdiv = ((val & pll_data->clkod_mask) >>
0101                  pll_data->clkod_shift) + 1;
0102     else if (pll_data->pllod) {
0103         postdiv = readl(pll_data->pllod);
0104         postdiv = ((postdiv & pll_data->clkod_mask) >>
0105                 pll_data->clkod_shift) + 1;
0106     } else
0107         postdiv = pll_data->postdiv;
0108
0109     rate /= (prediv + 1);
0110     rate = (rate * (mult + 1));
0111     rate /= postdiv;
0112
0113     return rate;
0114 }
0115
0116 static const struct clk_ops clk_pll_ops = {
0117     .recalc_rate = clk_pllclk_recalc,
0118 };
0119
0120 static struct clk *clk_register_pll(struct device *dev,
0121             const char *name,
0122             const char *parent_name,
0123             struct clk_pll_data *pll_data)
0124 {
0125     struct clk_init_data init;
0126     struct clk_pll *pll;
0127     struct clk *clk;
0128
0129     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0130     if (!pll)
0131         return ERR_PTR(-ENOMEM);
0132
0133     init.name = name;
0134     init.ops = &clk_pll_ops;
0135     init.flags = 0;
0136     init.parent_names = (parent_name ? &parent_name : NULL);
0137     init.num_parents = (parent_name ? 1 : 0);
0138
0139     pll->pll_data   = pll_data;
0140     pll->hw.init = &init;
0141
0142     clk = clk_register(NULL, &pll->hw);
0143     if (IS_ERR(clk))
0144         goto out;
0145
0146     return clk;
0147 out:
0148     kfree(pll);
0149     return NULL;
0150 }
0151
0152 /**
0153  * _of_pll_clk_init - PLL initialisation via DT
0154  * @node: device tree node for this clock
0155  * @pllctrl: If true, lower 6 bits of multiplier is in pllm register of
0156  *      pll controller, else it is in the control register0(bit 11-6)
0157  */
0158 static void __init _of_pll_clk_init(struct device_node *node, bool pllctrl)
0159 {
0160     struct clk_pll_data *pll_data;
0161     const char *parent_name;
0162     struct clk *clk;
0163     int i;
0164
0165     pll_data = kzalloc(sizeof(*pll_data), GFP_KERNEL);
0166     if (!pll_data) {
0167         pr_err("%s: Out of memory\n", __func__);
0168         return;
0169     }
0170
0171     parent_name = of_clk_get_parent_name(node, 0);
0172     if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) {
0173         /* assume the PLL has output divider register bits */
0174         pll_data->clkod_mask = CLKOD_MASK;
0175         pll_data->clkod_shift = CLKOD_SHIFT;
0176
0177         /*
0178          * Check if there is an post-divider register. If not
0179          * assume od bits are part of control register.
0180          */
0181         i = of_property_match_string(node, "reg-names",
0182                          "post-divider");
0183         pll_data->pllod = of_iomap(node, i);
0184     }
0185
0186     i = of_property_match_string(node, "reg-names", "control");
0187     pll_data->pll_ctl0 = of_iomap(node, i);
0188     if (!pll_data->pll_ctl0) {
0189         pr_err("%s: ioremap failed\n", __func__);
0190         iounmap(pll_data->pllod);
0191         goto out;
0192     }
0193
0194     pll_data->pllm_lower_mask = PLLM_LOW_MASK;
0195     pll_data->pllm_upper_shift = PLLM_HIGH_SHIFT;
0196     pll_data->plld_mask = PLLD_MASK;
0197     pll_data->has_pllctrl = pllctrl;
0198     if (!pll_data->has_pllctrl) {
0199         pll_data->pllm_upper_mask = PLLM_HIGH_MASK;
0200     } else {
0201         pll_data->pllm_upper_mask = MAIN_PLLM_HIGH_MASK;
0202         i = of_property_match_string(node, "reg-names", "multiplier");
0203         pll_data->pllm = of_iomap(node, i);
0204         if (!pll_data->pllm) {
0205             iounmap(pll_data->pll_ctl0);
0206             iounmap(pll_data->pllod);
0207             goto out;
0208         }
0209     }
0210
0211     clk = clk_register_pll(NULL, node->name, parent_name, pll_data);
0212     if (clk) {
0213         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0214         return;
0215     }
0216
0217 out:
0218     pr_err("%s: error initializing pll %pOFn\n", __func__, node);
0219     kfree(pll_data);
0220 }
0221
0222 /**
0223  * of_keystone_pll_clk_init - PLL initialisation DT wrapper
0224  * @node: device tree node for this clock
0225  */
0226 static void __init of_keystone_pll_clk_init(struct device_node *node)
0227 {
0228     _of_pll_clk_init(node, false);
0229 }
0230 CLK_OF_DECLARE(keystone_pll_clock, "ti,keystone,pll-clock",
0231                     of_keystone_pll_clk_init);
0232
0233 /**
0234  * of_keystone_main_pll_clk_init - Main PLL initialisation DT wrapper
0235  * @node: device tree node for this clock
0236  */
0237 static void __init of_keystone_main_pll_clk_init(struct device_node *node)
0238 {
0239     _of_pll_clk_init(node, true);
0240 }
0241 CLK_OF_DECLARE(keystone_main_pll_clock, "ti,keystone,main-pll-clock",
0242                         of_keystone_main_pll_clk_init);
0243
0244 /**
0245  * of_pll_div_clk_init - PLL divider setup function
0246  * @node: device tree node for this clock
0247  */
0248 static void __init of_pll_div_clk_init(struct device_node *node)
0249 {
0250     const char *parent_name;
0251     void __iomem *reg;
0252     u32 shift, mask;
0253     struct clk *clk;
0254     const char *clk_name = node->name;
0255
0256     of_property_read_string(node, "clock-output-names", &clk_name);
0257     reg = of_iomap(node, 0);
0258     if (!reg) {
0259         pr_err("%s: ioremap failed\n", __func__);
0260         return;
0261     }
0262
0263     parent_name = of_clk_get_parent_name(node, 0);
0264     if (!parent_name) {
0265         pr_err("%s: missing parent clock\n", __func__);
0266         iounmap(reg);
0267         return;
0268     }
0269
0270     if (of_property_read_u32(node, "bit-shift", &shift)) {
0271         pr_err("%s: missing 'shift' property\n", __func__);
0272         iounmap(reg);
0273         return;
0274     }
0275
0276     if (of_property_read_u32(node, "bit-mask", &mask)) {
0277         pr_err("%s: missing 'bit-mask' property\n", __func__);
0278         iounmap(reg);
0279         return;
0280     }
0281
0282     clk = clk_register_divider(NULL, clk_name, parent_name, 0, reg, shift,
0283                  mask, 0, NULL);
0284     if (clk) {
0285         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0286     } else {
0287         pr_err("%s: error registering divider %s\n", __func__, clk_name);
0288         iounmap(reg);
0289     }
0290 }
0291 CLK_OF_DECLARE(pll_divider_clock, "ti,keystone,pll-divider-clock", of_pll_div_clk_init);
0292
0293 /**
0294  * of_pll_mux_clk_init - PLL mux setup function
0295  * @node: device tree node for this clock
0296  */
0297 static void __init of_pll_mux_clk_init(struct device_node *node)
0298 {
0299     void __iomem *reg;
0300     u32 shift, mask;
0301     struct clk *clk;
0302     const char *parents[2];
0303     const char *clk_name = node->name;
0304
0305     of_property_read_string(node, "clock-output-names", &clk_name);
0306     reg = of_iomap(node, 0);
0307     if (!reg) {
0308         pr_err("%s: ioremap failed\n", __func__);
0309         return;
0310     }
0311
0312     of_clk_parent_fill(node, parents, 2);
0313     if (!parents[0] || !parents[1]) {
0314         pr_err("%s: missing parent clocks\n", __func__);
0315         return;
0316     }
0317
0318     if (of_property_read_u32(node, "bit-shift", &shift)) {
0319         pr_err("%s: missing 'shift' property\n", __func__);
0320         return;
0321     }
0322
0323     if (of_property_read_u32(node, "bit-mask", &mask)) {
0324         pr_err("%s: missing 'bit-mask' property\n", __func__);
0325         return;
0326     }
0327
0328     clk = clk_register_mux(NULL, clk_name, (const char **)&parents,
0329                 ARRAY_SIZE(parents) , 0, reg, shift, mask,
0330                 0, NULL);
0331     if (clk)
0332         of_clk_add_provider(node, of_clk_src_simple_get, clk);
0333     else
0334         pr_err("%s: error registering mux %s\n", __func__, clk_name);
0335 }
0336 CLK_OF_DECLARE(pll_mux_clock, "ti,keystone,pll-mux-clock", of_pll_mux_clk_init);
0337
0338 MODULE_LICENSE("GPL");
0339 MODULE_DESCRIPTION("PLL clock driver for Keystone devices");
0340 MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
0341 MODULE_AUTHOR("Santosh Shilimkar <santosh.shilimkar@ti.com>");