clk/ingenic/tcu.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * JZ47xx SoCs TCU clocks driver
0004  * Copyright (C) 2019 Paul Cercueil <paul@crapouillou.net>
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/clockchips.h>
0010 #include <linux/mfd/ingenic-tcu.h>
0011 #include <linux/mfd/syscon.h>
0012 #include <linux/regmap.h>
0013 #include <linux/slab.h>
0014 #include <linux/syscore_ops.h>
0015
0016 #include <dt-bindings/clock/ingenic,tcu.h>
0017
0018 /* 8 channels max + watchdog + OST */
0019 #define TCU_CLK_COUNT   10
0020
0021 #undef pr_fmt
0022 #define pr_fmt(fmt) "ingenic-tcu-clk: " fmt
0023
0024 enum tcu_clk_parent {
0025     TCU_PARENT_PCLK,
0026     TCU_PARENT_RTC,
0027     TCU_PARENT_EXT,
0028 };
0029
0030 struct ingenic_soc_info {
0031     unsigned int num_channels;
0032     bool has_ost;
0033     bool has_tcu_clk;
0034     bool allow_missing_tcu_clk;
0035 };
0036
0037 struct ingenic_tcu_clk_info {
0038     struct clk_init_data init_data;
0039     u8 gate_bit;
0040     u8 tcsr_reg;
0041 };
0042
0043 struct ingenic_tcu_clk {
0044     struct clk_hw hw;
0045     unsigned int idx;
0046     struct ingenic_tcu *tcu;
0047     const struct ingenic_tcu_clk_info *info;
0048 };
0049
0050 struct ingenic_tcu {
0051     const struct ingenic_soc_info *soc_info;
0052     struct regmap *map;
0053     struct clk *clk;
0054
0055     struct clk_hw_onecell_data *clocks;
0056 };
0057
0058 static struct ingenic_tcu *ingenic_tcu;
0059
0060 static inline struct ingenic_tcu_clk *to_tcu_clk(struct clk_hw *hw)
0061 {
0062     return container_of(hw, struct ingenic_tcu_clk, hw);
0063 }
0064
0065 static int ingenic_tcu_enable(struct clk_hw *hw)
0066 {
0067     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0068     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0069     struct ingenic_tcu *tcu = tcu_clk->tcu;
0070
0071     regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
0072
0073     return 0;
0074 }
0075
0076 static void ingenic_tcu_disable(struct clk_hw *hw)
0077 {
0078     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0079     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0080     struct ingenic_tcu *tcu = tcu_clk->tcu;
0081
0082     regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
0083 }
0084
0085 static int ingenic_tcu_is_enabled(struct clk_hw *hw)
0086 {
0087     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0088     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0089     unsigned int value;
0090
0091     regmap_read(tcu_clk->tcu->map, TCU_REG_TSR, &value);
0092
0093     return !(value & BIT(info->gate_bit));
0094 }
0095
0096 static bool ingenic_tcu_enable_regs(struct clk_hw *hw)
0097 {
0098     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0099     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0100     struct ingenic_tcu *tcu = tcu_clk->tcu;
0101     bool enabled = false;
0102
0103     /*
0104      * According to the programming manual, a timer channel's registers can
0105      * only be accessed when the channel's stop bit is clear.
0106      */
0107     enabled = !!ingenic_tcu_is_enabled(hw);
0108     regmap_write(tcu->map, TCU_REG_TSCR, BIT(info->gate_bit));
0109
0110     return enabled;
0111 }
0112
0113 static void ingenic_tcu_disable_regs(struct clk_hw *hw)
0114 {
0115     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0116     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0117     struct ingenic_tcu *tcu = tcu_clk->tcu;
0118
0119     regmap_write(tcu->map, TCU_REG_TSSR, BIT(info->gate_bit));
0120 }
0121
0122 static u8 ingenic_tcu_get_parent(struct clk_hw *hw)
0123 {
0124     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0125     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0126     unsigned int val = 0;
0127     int ret;
0128
0129     ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &val);
0130     WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
0131
0132     return ffs(val & TCU_TCSR_PARENT_CLOCK_MASK) - 1;
0133 }
0134
0135 static int ingenic_tcu_set_parent(struct clk_hw *hw, u8 idx)
0136 {
0137     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0138     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0139     bool was_enabled;
0140     int ret;
0141
0142     was_enabled = ingenic_tcu_enable_regs(hw);
0143
0144     ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
0145                  TCU_TCSR_PARENT_CLOCK_MASK, BIT(idx));
0146     WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
0147
0148     if (!was_enabled)
0149         ingenic_tcu_disable_regs(hw);
0150
0151     return 0;
0152 }
0153
0154 static unsigned long ingenic_tcu_recalc_rate(struct clk_hw *hw,
0155         unsigned long parent_rate)
0156 {
0157     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0158     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0159     unsigned int prescale;
0160     int ret;
0161
0162     ret = regmap_read(tcu_clk->tcu->map, info->tcsr_reg, &prescale);
0163     WARN_ONCE(ret < 0, "Unable to read TCSR %d", tcu_clk->idx);
0164
0165     prescale = (prescale & TCU_TCSR_PRESCALE_MASK) >> TCU_TCSR_PRESCALE_LSB;
0166
0167     return parent_rate >> (prescale * 2);
0168 }
0169
0170 static u8 ingenic_tcu_get_prescale(unsigned long rate, unsigned long req_rate)
0171 {
0172     u8 prescale;
0173
0174     for (prescale = 0; prescale < 5; prescale++)
0175         if ((rate >> (prescale * 2)) <= req_rate)
0176             return prescale;
0177
0178     return 5; /* /1024 divider */
0179 }
0180
0181 static long ingenic_tcu_round_rate(struct clk_hw *hw, unsigned long req_rate,
0182         unsigned long *parent_rate)
0183 {
0184     unsigned long rate = *parent_rate;
0185     u8 prescale;
0186
0187     if (req_rate > rate)
0188         return rate;
0189
0190     prescale = ingenic_tcu_get_prescale(rate, req_rate);
0191
0192     return rate >> (prescale * 2);
0193 }
0194
0195 static int ingenic_tcu_set_rate(struct clk_hw *hw, unsigned long req_rate,
0196         unsigned long parent_rate)
0197 {
0198     struct ingenic_tcu_clk *tcu_clk = to_tcu_clk(hw);
0199     const struct ingenic_tcu_clk_info *info = tcu_clk->info;
0200     u8 prescale = ingenic_tcu_get_prescale(parent_rate, req_rate);
0201     bool was_enabled;
0202     int ret;
0203
0204     was_enabled = ingenic_tcu_enable_regs(hw);
0205
0206     ret = regmap_update_bits(tcu_clk->tcu->map, info->tcsr_reg,
0207                  TCU_TCSR_PRESCALE_MASK,
0208                  prescale << TCU_TCSR_PRESCALE_LSB);
0209     WARN_ONCE(ret < 0, "Unable to update TCSR %d", tcu_clk->idx);
0210
0211     if (!was_enabled)
0212         ingenic_tcu_disable_regs(hw);
0213
0214     return 0;
0215 }
0216
0217 static const struct clk_ops ingenic_tcu_clk_ops = {
0218     .get_parent = ingenic_tcu_get_parent,
0219     .set_parent = ingenic_tcu_set_parent,
0220
0221     .recalc_rate    = ingenic_tcu_recalc_rate,
0222     .round_rate = ingenic_tcu_round_rate,
0223     .set_rate   = ingenic_tcu_set_rate,
0224
0225     .enable     = ingenic_tcu_enable,
0226     .disable    = ingenic_tcu_disable,
0227     .is_enabled = ingenic_tcu_is_enabled,
0228 };
0229
0230 static const char * const ingenic_tcu_timer_parents[] = {
0231     [TCU_PARENT_PCLK] = "pclk",
0232     [TCU_PARENT_RTC]  = "rtc",
0233     [TCU_PARENT_EXT]  = "ext",
0234 };
0235
0236 #define DEF_TIMER(_name, _gate_bit, _tcsr)              \
0237     {                               \
0238         .init_data = {                      \
0239             .name = _name,                  \
0240             .parent_names = ingenic_tcu_timer_parents,  \
0241             .num_parents = ARRAY_SIZE(ingenic_tcu_timer_parents),\
0242             .ops = &ingenic_tcu_clk_ops,            \
0243             .flags = CLK_SET_RATE_UNGATE,           \
0244         },                          \
0245         .gate_bit = _gate_bit,                  \
0246         .tcsr_reg = _tcsr,                  \
0247     }
0248 static const struct ingenic_tcu_clk_info ingenic_tcu_clk_info[] = {
0249     [TCU_CLK_TIMER0] = DEF_TIMER("timer0", 0, TCU_REG_TCSRc(0)),
0250     [TCU_CLK_TIMER1] = DEF_TIMER("timer1", 1, TCU_REG_TCSRc(1)),
0251     [TCU_CLK_TIMER2] = DEF_TIMER("timer2", 2, TCU_REG_TCSRc(2)),
0252     [TCU_CLK_TIMER3] = DEF_TIMER("timer3", 3, TCU_REG_TCSRc(3)),
0253     [TCU_CLK_TIMER4] = DEF_TIMER("timer4", 4, TCU_REG_TCSRc(4)),
0254     [TCU_CLK_TIMER5] = DEF_TIMER("timer5", 5, TCU_REG_TCSRc(5)),
0255     [TCU_CLK_TIMER6] = DEF_TIMER("timer6", 6, TCU_REG_TCSRc(6)),
0256     [TCU_CLK_TIMER7] = DEF_TIMER("timer7", 7, TCU_REG_TCSRc(7)),
0257 };
0258
0259 static const struct ingenic_tcu_clk_info ingenic_tcu_watchdog_clk_info =
0260                      DEF_TIMER("wdt", 16, TCU_REG_WDT_TCSR);
0261 static const struct ingenic_tcu_clk_info ingenic_tcu_ost_clk_info =
0262                      DEF_TIMER("ost", 15, TCU_REG_OST_TCSR);
0263 #undef DEF_TIMER
0264
0265 static int __init ingenic_tcu_register_clock(struct ingenic_tcu *tcu,
0266             unsigned int idx, enum tcu_clk_parent parent,
0267             const struct ingenic_tcu_clk_info *info,
0268             struct clk_hw_onecell_data *clocks)
0269 {
0270     struct ingenic_tcu_clk *tcu_clk;
0271     int err;
0272
0273     tcu_clk = kzalloc(sizeof(*tcu_clk), GFP_KERNEL);
0274     if (!tcu_clk)
0275         return -ENOMEM;
0276
0277     tcu_clk->hw.init = &info->init_data;
0278     tcu_clk->idx = idx;
0279     tcu_clk->info = info;
0280     tcu_clk->tcu = tcu;
0281
0282     /* Reset channel and clock divider, set default parent */
0283     ingenic_tcu_enable_regs(&tcu_clk->hw);
0284     regmap_update_bits(tcu->map, info->tcsr_reg, 0xffff, BIT(parent));
0285     ingenic_tcu_disable_regs(&tcu_clk->hw);
0286
0287     err = clk_hw_register(NULL, &tcu_clk->hw);
0288     if (err) {
0289         kfree(tcu_clk);
0290         return err;
0291     }
0292
0293     clocks->hws[idx] = &tcu_clk->hw;
0294
0295     return 0;
0296 }
0297
0298 static const struct ingenic_soc_info jz4740_soc_info = {
0299     .num_channels = 8,
0300     .has_ost = false,
0301     .has_tcu_clk = true,
0302 };
0303
0304 static const struct ingenic_soc_info jz4725b_soc_info = {
0305     .num_channels = 6,
0306     .has_ost = true,
0307     .has_tcu_clk = true,
0308 };
0309
0310 static const struct ingenic_soc_info jz4770_soc_info = {
0311     .num_channels = 8,
0312     .has_ost = true,
0313     .has_tcu_clk = false,
0314 };
0315
0316 static const struct ingenic_soc_info x1000_soc_info = {
0317     .num_channels = 8,
0318     .has_ost = false, /* X1000 has OST, but it not belong TCU */
0319     .has_tcu_clk = true,
0320     .allow_missing_tcu_clk = true,
0321 };
0322
0323 static const struct of_device_id __maybe_unused ingenic_tcu_of_match[] __initconst = {
0324     { .compatible = "ingenic,jz4740-tcu", .data = &jz4740_soc_info, },
0325     { .compatible = "ingenic,jz4725b-tcu", .data = &jz4725b_soc_info, },
0326     { .compatible = "ingenic,jz4760-tcu", .data = &jz4770_soc_info, },
0327     { .compatible = "ingenic,jz4770-tcu", .data = &jz4770_soc_info, },
0328     { .compatible = "ingenic,x1000-tcu", .data = &x1000_soc_info, },
0329     { /* sentinel */ }
0330 };
0331
0332 static int __init ingenic_tcu_probe(struct device_node *np)
0333 {
0334     const struct of_device_id *id = of_match_node(ingenic_tcu_of_match, np);
0335     struct ingenic_tcu *tcu;
0336     struct regmap *map;
0337     unsigned int i;
0338     int ret;
0339
0340     map = device_node_to_regmap(np);
0341     if (IS_ERR(map))
0342         return PTR_ERR(map);
0343
0344     tcu = kzalloc(sizeof(*tcu), GFP_KERNEL);
0345     if (!tcu)
0346         return -ENOMEM;
0347
0348     tcu->map = map;
0349     tcu->soc_info = id->data;
0350
0351     if (tcu->soc_info->has_tcu_clk) {
0352         tcu->clk = of_clk_get_by_name(np, "tcu");
0353         if (IS_ERR(tcu->clk)) {
0354             ret = PTR_ERR(tcu->clk);
0355
0356             /*
0357              * Old device trees for some SoCs did not include the
0358              * TCU clock because this driver (incorrectly) didn't
0359              * use it. In this case we complain loudly and attempt
0360              * to continue without the clock, which might work if
0361              * booting with workarounds like "clk_ignore_unused".
0362              */
0363             if (tcu->soc_info->allow_missing_tcu_clk && ret == -EINVAL) {
0364                 pr_warn("TCU clock missing from device tree, please update your device tree\n");
0365                 tcu->clk = NULL;
0366             } else {
0367                 pr_crit("Cannot get TCU clock from device tree\n");
0368                 goto err_free_tcu;
0369             }
0370         } else {
0371             ret = clk_prepare_enable(tcu->clk);
0372             if (ret) {
0373                 pr_crit("Unable to enable TCU clock\n");
0374                 goto err_put_clk;
0375             }
0376         }
0377     }
0378
0379     tcu->clocks = kzalloc(struct_size(tcu->clocks, hws, TCU_CLK_COUNT),
0380                   GFP_KERNEL);
0381     if (!tcu->clocks) {
0382         ret = -ENOMEM;
0383         goto err_clk_disable;
0384     }
0385
0386     tcu->clocks->num = TCU_CLK_COUNT;
0387
0388     for (i = 0; i < tcu->soc_info->num_channels; i++) {
0389         ret = ingenic_tcu_register_clock(tcu, i, TCU_PARENT_EXT,
0390                          &ingenic_tcu_clk_info[i],
0391                          tcu->clocks);
0392         if (ret) {
0393             pr_crit("cannot register clock %d\n", i);
0394             goto err_unregister_timer_clocks;
0395         }
0396     }
0397
0398     /*
0399      * We set EXT as the default parent clock for all the TCU clocks
0400      * except for the watchdog one, where we set the RTC clock as the
0401      * parent. Since the EXT and PCLK are much faster than the RTC clock,
0402      * the watchdog would kick after a maximum time of 5s, and we might
0403      * want a slower kicking time.
0404      */
0405     ret = ingenic_tcu_register_clock(tcu, TCU_CLK_WDT, TCU_PARENT_RTC,
0406                      &ingenic_tcu_watchdog_clk_info,
0407                      tcu->clocks);
0408     if (ret) {
0409         pr_crit("cannot register watchdog clock\n");
0410         goto err_unregister_timer_clocks;
0411     }
0412
0413     if (tcu->soc_info->has_ost) {
0414         ret = ingenic_tcu_register_clock(tcu, TCU_CLK_OST,
0415                          TCU_PARENT_EXT,
0416                          &ingenic_tcu_ost_clk_info,
0417                          tcu->clocks);
0418         if (ret) {
0419             pr_crit("cannot register ost clock\n");
0420             goto err_unregister_watchdog_clock;
0421         }
0422     }
0423
0424     ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, tcu->clocks);
0425     if (ret) {
0426         pr_crit("cannot add OF clock provider\n");
0427         goto err_unregister_ost_clock;
0428     }
0429
0430     ingenic_tcu = tcu;
0431
0432     return 0;
0433
0434 err_unregister_ost_clock:
0435     if (tcu->soc_info->has_ost)
0436         clk_hw_unregister(tcu->clocks->hws[i + 1]);
0437 err_unregister_watchdog_clock:
0438     clk_hw_unregister(tcu->clocks->hws[i]);
0439 err_unregister_timer_clocks:
0440     for (i = 0; i < tcu->clocks->num; i++)
0441         if (tcu->clocks->hws[i])
0442             clk_hw_unregister(tcu->clocks->hws[i]);
0443     kfree(tcu->clocks);
0444 err_clk_disable:
0445     if (tcu->clk)
0446         clk_disable_unprepare(tcu->clk);
0447 err_put_clk:
0448     if (tcu->clk)
0449         clk_put(tcu->clk);
0450 err_free_tcu:
0451     kfree(tcu);
0452     return ret;
0453 }
0454
0455 static int __maybe_unused tcu_pm_suspend(void)
0456 {
0457     struct ingenic_tcu *tcu = ingenic_tcu;
0458
0459     if (tcu->clk)
0460         clk_disable(tcu->clk);
0461
0462     return 0;
0463 }
0464
0465 static void __maybe_unused tcu_pm_resume(void)
0466 {
0467     struct ingenic_tcu *tcu = ingenic_tcu;
0468
0469     if (tcu->clk)
0470         clk_enable(tcu->clk);
0471 }
0472
0473 static struct syscore_ops __maybe_unused tcu_pm_ops = {
0474     .suspend = tcu_pm_suspend,
0475     .resume = tcu_pm_resume,
0476 };
0477
0478 static void __init ingenic_tcu_init(struct device_node *np)
0479 {
0480     int ret = ingenic_tcu_probe(np);
0481
0482     if (ret)
0483         pr_crit("Failed to initialize TCU clocks: %d\n", ret);
0484
0485     if (IS_ENABLED(CONFIG_PM_SLEEP))
0486         register_syscore_ops(&tcu_pm_ops);
0487 }
0488
0489 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-tcu", ingenic_tcu_init);
0490 CLK_OF_DECLARE_DRIVER(jz4725b_cgu, "ingenic,jz4725b-tcu", ingenic_tcu_init);
0491 CLK_OF_DECLARE_DRIVER(jz4760_cgu, "ingenic,jz4760-tcu", ingenic_tcu_init);
0492 CLK_OF_DECLARE_DRIVER(jz4770_cgu, "ingenic,jz4770-tcu", ingenic_tcu_init);
0493 CLK_OF_DECLARE_DRIVER(x1000_cgu, "ingenic,x1000-tcu", ingenic_tcu_init);