clk/ingenic/jz4740-cgu.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Ingenic JZ4740 SoC CGU driver
0004  *
0005  * Copyright (c) 2015 Imagination Technologies
0006  * Author: Paul Burton <paul.burton@mips.com>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/delay.h>
0011 #include <linux/io.h>
0012 #include <linux/of.h>
0013
0014 #include <dt-bindings/clock/ingenic,jz4740-cgu.h>
0015
0016 #include "cgu.h"
0017 #include "pm.h"
0018
0019 /* CGU register offsets */
0020 #define CGU_REG_CPCCR       0x00
0021 #define CGU_REG_LCR     0x04
0022 #define CGU_REG_CPPCR       0x10
0023 #define CGU_REG_CLKGR       0x20
0024 #define CGU_REG_SCR     0x24
0025 #define CGU_REG_I2SCDR      0x60
0026 #define CGU_REG_LPCDR       0x64
0027 #define CGU_REG_MSCCDR      0x68
0028 #define CGU_REG_UHCCDR      0x6c
0029 #define CGU_REG_SSICDR      0x74
0030
0031 /* bits within a PLL control register */
0032 #define PLLCTL_M_SHIFT      23
0033 #define PLLCTL_M_MASK       (0x1ff << PLLCTL_M_SHIFT)
0034 #define PLLCTL_N_SHIFT      18
0035 #define PLLCTL_N_MASK       (0x1f << PLLCTL_N_SHIFT)
0036 #define PLLCTL_OD_SHIFT     16
0037 #define PLLCTL_OD_MASK      (0x3 << PLLCTL_OD_SHIFT)
0038 #define PLLCTL_STABLE       (1 << 10)
0039 #define PLLCTL_BYPASS       (1 << 9)
0040 #define PLLCTL_ENABLE       (1 << 8)
0041
0042 /* bits within the LCR register */
0043 #define LCR_SLEEP       (1 << 0)
0044
0045 /* bits within the CLKGR register */
0046 #define CLKGR_UDC       (1 << 11)
0047
0048 static struct ingenic_cgu *cgu;
0049
0050 static const s8 pll_od_encoding[4] = {
0051     0x0, 0x1, -1, 0x3,
0052 };
0053
0054 static const u8 jz4740_cgu_cpccr_div_table[] = {
0055     1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
0056 };
0057
0058 static const u8 jz4740_cgu_pll_half_div_table[] = {
0059     2, 1,
0060 };
0061
0062 static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
0063
0064     /* External clocks */
0065
0066     [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
0067     [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
0068
0069     [JZ4740_CLK_PLL] = {
0070         "pll", CGU_CLK_PLL,
0071         .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
0072         .pll = {
0073             .reg = CGU_REG_CPPCR,
0074             .rate_multiplier = 1,
0075             .m_shift = 23,
0076             .m_bits = 9,
0077             .m_offset = 2,
0078             .n_shift = 18,
0079             .n_bits = 5,
0080             .n_offset = 2,
0081             .od_shift = 16,
0082             .od_bits = 2,
0083             .od_max = 4,
0084             .od_encoding = pll_od_encoding,
0085             .stable_bit = 10,
0086             .bypass_reg = CGU_REG_CPPCR,
0087             .bypass_bit = 9,
0088             .enable_bit = 8,
0089         },
0090     },
0091
0092     /* Muxes & dividers */
0093
0094     [JZ4740_CLK_PLL_HALF] = {
0095         "pll half", CGU_CLK_DIV,
0096         .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
0097         .div = {
0098             CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0,
0099             jz4740_cgu_pll_half_div_table,
0100         },
0101     },
0102
0103     [JZ4740_CLK_CCLK] = {
0104         "cclk", CGU_CLK_DIV,
0105         /*
0106          * Disabling the CPU clock or any parent clocks will hang the
0107          * system; mark it critical.
0108          */
0109         .flags = CLK_IS_CRITICAL,
0110         .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
0111         .div = {
0112             CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0,
0113             jz4740_cgu_cpccr_div_table,
0114         },
0115     },
0116
0117     [JZ4740_CLK_HCLK] = {
0118         "hclk", CGU_CLK_DIV,
0119         .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
0120         .div = {
0121             CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0,
0122             jz4740_cgu_cpccr_div_table,
0123         },
0124     },
0125
0126     [JZ4740_CLK_PCLK] = {
0127         "pclk", CGU_CLK_DIV,
0128         .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
0129         .div = {
0130             CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0,
0131             jz4740_cgu_cpccr_div_table,
0132         },
0133     },
0134
0135     [JZ4740_CLK_MCLK] = {
0136         "mclk", CGU_CLK_DIV,
0137         /*
0138          * Disabling MCLK or its parents will render DRAM
0139          * inaccessible; mark it critical.
0140          */
0141         .flags = CLK_IS_CRITICAL,
0142         .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
0143         .div = {
0144             CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0,
0145             jz4740_cgu_cpccr_div_table,
0146         },
0147     },
0148
0149     [JZ4740_CLK_LCD] = {
0150         "lcd", CGU_CLK_DIV | CGU_CLK_GATE,
0151         .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
0152         .div = {
0153             CGU_REG_CPCCR, 16, 1, 5, 22, -1, -1, 0,
0154             jz4740_cgu_cpccr_div_table,
0155         },
0156         .gate = { CGU_REG_CLKGR, 10 },
0157     },
0158
0159     [JZ4740_CLK_LCD_PCLK] = {
0160         "lcd_pclk", CGU_CLK_DIV,
0161         .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
0162         .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 },
0163     },
0164
0165     [JZ4740_CLK_I2S] = {
0166         "i2s", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
0167         .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
0168         .mux = { CGU_REG_CPCCR, 31, 1 },
0169         .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 },
0170         .gate = { CGU_REG_CLKGR, 6 },
0171     },
0172
0173     [JZ4740_CLK_SPI] = {
0174         "spi", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
0175         .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL, -1, -1 },
0176         .mux = { CGU_REG_SSICDR, 31, 1 },
0177         .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 },
0178         .gate = { CGU_REG_CLKGR, 4 },
0179     },
0180
0181     [JZ4740_CLK_MMC] = {
0182         "mmc", CGU_CLK_DIV | CGU_CLK_GATE,
0183         .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
0184         .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 },
0185         .gate = { CGU_REG_CLKGR, 7 },
0186     },
0187
0188     [JZ4740_CLK_UHC] = {
0189         "uhc", CGU_CLK_DIV | CGU_CLK_GATE,
0190         .parents = { JZ4740_CLK_PLL_HALF, -1, -1, -1 },
0191         .div = { CGU_REG_UHCCDR, 0, 1, 4, -1, -1, -1 },
0192         .gate = { CGU_REG_CLKGR, 14 },
0193     },
0194
0195     [JZ4740_CLK_UDC] = {
0196         "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE,
0197         .parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
0198         .mux = { CGU_REG_CPCCR, 29, 1 },
0199         .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
0200         .gate = { CGU_REG_SCR, 6, true },
0201     },
0202
0203     /* Gate-only clocks */
0204
0205     [JZ4740_CLK_UART0] = {
0206         "uart0", CGU_CLK_GATE,
0207         .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
0208         .gate = { CGU_REG_CLKGR, 0 },
0209     },
0210
0211     [JZ4740_CLK_UART1] = {
0212         "uart1", CGU_CLK_GATE,
0213         .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
0214         .gate = { CGU_REG_CLKGR, 15 },
0215     },
0216
0217     [JZ4740_CLK_DMA] = {
0218         "dma", CGU_CLK_GATE,
0219         .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
0220         .gate = { CGU_REG_CLKGR, 12 },
0221     },
0222
0223     [JZ4740_CLK_IPU] = {
0224         "ipu", CGU_CLK_GATE,
0225         .parents = { JZ4740_CLK_PCLK, -1, -1, -1 },
0226         .gate = { CGU_REG_CLKGR, 13 },
0227     },
0228
0229     [JZ4740_CLK_ADC] = {
0230         "adc", CGU_CLK_GATE,
0231         .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
0232         .gate = { CGU_REG_CLKGR, 8 },
0233     },
0234
0235     [JZ4740_CLK_I2C] = {
0236         "i2c", CGU_CLK_GATE,
0237         .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
0238         .gate = { CGU_REG_CLKGR, 3 },
0239     },
0240
0241     [JZ4740_CLK_AIC] = {
0242         "aic", CGU_CLK_GATE,
0243         .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
0244         .gate = { CGU_REG_CLKGR, 5 },
0245     },
0246
0247     [JZ4740_CLK_TCU] = {
0248         "tcu", CGU_CLK_GATE,
0249         .parents = { JZ4740_CLK_EXT, -1, -1, -1 },
0250         .gate = { CGU_REG_CLKGR, 1 },
0251     },
0252 };
0253
0254 static void __init jz4740_cgu_init(struct device_node *np)
0255 {
0256     int retval;
0257
0258     cgu = ingenic_cgu_new(jz4740_cgu_clocks,
0259                   ARRAY_SIZE(jz4740_cgu_clocks), np);
0260     if (!cgu) {
0261         pr_err("%s: failed to initialise CGU\n", __func__);
0262         return;
0263     }
0264
0265     retval = ingenic_cgu_register_clocks(cgu);
0266     if (retval)
0267         pr_err("%s: failed to register CGU Clocks\n", __func__);
0268
0269     ingenic_cgu_register_syscore_ops(cgu);
0270 }
0271 CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);