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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 * Ingenic SoC CGU driver 0004 * 0005 * Copyright (c) 2013-2015 Imagination Technologies 0006 * Author: Paul Burton <paul.burton@mips.com> 0007 */ 0008 0009 #ifndef __DRIVERS_CLK_INGENIC_CGU_H__ 0010 #define __DRIVERS_CLK_INGENIC_CGU_H__ 0011 0012 #include <linux/bitops.h> 0013 #include <linux/clk-provider.h> 0014 #include <linux/of.h> 0015 #include <linux/spinlock.h> 0016 0017 /** 0018 * struct ingenic_cgu_pll_info - information about a PLL 0019 * @reg: the offset of the PLL's control register within the CGU 0020 * @rate_multiplier: the multiplier needed by pll rate calculation 0021 * @m_shift: the number of bits to shift the multiplier value by (ie. the 0022 * index of the lowest bit of the multiplier value in the PLL's 0023 * control register) 0024 * @m_bits: the size of the multiplier field in bits 0025 * @m_offset: the multiplier value which encodes to 0 in the PLL's control 0026 * register 0027 * @n_shift: the number of bits to shift the divider value by (ie. the 0028 * index of the lowest bit of the divider value in the PLL's 0029 * control register) 0030 * @n_bits: the size of the divider field in bits 0031 * @n_offset: the divider value which encodes to 0 in the PLL's control 0032 * register 0033 * @od_shift: the number of bits to shift the post-VCO divider value by (ie. 0034 * the index of the lowest bit of the post-VCO divider value in 0035 * the PLL's control register) 0036 * @od_bits: the size of the post-VCO divider field in bits 0037 * @od_max: the maximum post-VCO divider value 0038 * @od_encoding: a pointer to an array mapping post-VCO divider values to 0039 * their encoded values in the PLL control register, or -1 for 0040 * unsupported values 0041 * @bypass_reg: the offset of the bypass control register within the CGU 0042 * @bypass_bit: the index of the bypass bit in the PLL control register, or 0043 * -1 if there is no bypass bit 0044 * @enable_bit: the index of the enable bit in the PLL control register 0045 * @stable_bit: the index of the stable bit in the PLL control register 0046 */ 0047 struct ingenic_cgu_pll_info { 0048 unsigned reg; 0049 unsigned rate_multiplier; 0050 const s8 *od_encoding; 0051 u8 m_shift, m_bits, m_offset; 0052 u8 n_shift, n_bits, n_offset; 0053 u8 od_shift, od_bits, od_max; 0054 unsigned bypass_reg; 0055 s8 bypass_bit; 0056 u8 enable_bit; 0057 u8 stable_bit; 0058 void (*calc_m_n_od)(const struct ingenic_cgu_pll_info *pll_info, 0059 unsigned long rate, unsigned long parent_rate, 0060 unsigned int *m, unsigned int *n, unsigned int *od); 0061 }; 0062 0063 /** 0064 * struct ingenic_cgu_mux_info - information about a clock mux 0065 * @reg: offset of the mux control register within the CGU 0066 * @shift: number of bits to shift the mux value by (ie. the index of 0067 * the lowest bit of the mux value within its control register) 0068 * @bits: the size of the mux value in bits 0069 */ 0070 struct ingenic_cgu_mux_info { 0071 unsigned reg; 0072 u8 shift; 0073 u8 bits; 0074 }; 0075 0076 /** 0077 * struct ingenic_cgu_div_info - information about a divider 0078 * @reg: offset of the divider control register within the CGU 0079 * @shift: number of bits to left shift the divide value by (ie. the index of 0080 * the lowest bit of the divide value within its control register) 0081 * @div: number to divide the divider value by (i.e. if the 0082 * effective divider value is the value written to the register 0083 * multiplied by some constant) 0084 * @bits: the size of the divide value in bits 0085 * @ce_bit: the index of the change enable bit within reg, or -1 if there 0086 * isn't one 0087 * @busy_bit: the index of the busy bit within reg, or -1 if there isn't one 0088 * @stop_bit: the index of the stop bit within reg, or -1 if there isn't one 0089 * @bypass_mask: mask of parent clocks for which the divider does not apply 0090 * @div_table: optional table to map the value read from the register to the 0091 * actual divider value 0092 */ 0093 struct ingenic_cgu_div_info { 0094 unsigned reg; 0095 u8 shift; 0096 u8 div; 0097 u8 bits; 0098 s8 ce_bit; 0099 s8 busy_bit; 0100 s8 stop_bit; 0101 u8 bypass_mask; 0102 const u8 *div_table; 0103 }; 0104 0105 /** 0106 * struct ingenic_cgu_fixdiv_info - information about a fixed divider 0107 * @div: the divider applied to the parent clock 0108 */ 0109 struct ingenic_cgu_fixdiv_info { 0110 unsigned div; 0111 }; 0112 0113 /** 0114 * struct ingenic_cgu_gate_info - information about a clock gate 0115 * @reg: offset of the gate control register within the CGU 0116 * @bit: offset of the bit in the register that controls the gate 0117 * @clear_to_gate: if set, the clock is gated when the bit is cleared 0118 * @delay_us: delay in microseconds after which the clock is considered stable 0119 */ 0120 struct ingenic_cgu_gate_info { 0121 unsigned reg; 0122 u8 bit; 0123 bool clear_to_gate; 0124 u16 delay_us; 0125 }; 0126 0127 /** 0128 * struct ingenic_cgu_custom_info - information about a custom (SoC) clock 0129 * @clk_ops: custom clock operation callbacks 0130 */ 0131 struct ingenic_cgu_custom_info { 0132 const struct clk_ops *clk_ops; 0133 }; 0134 0135 /** 0136 * struct ingenic_cgu_clk_info - information about a clock 0137 * @name: name of the clock 0138 * @type: a bitmask formed from CGU_CLK_* values 0139 * @flags: common clock flags to set on this clock 0140 * @parents: an array of the indices of potential parents of this clock 0141 * within the clock_info array of the CGU, or -1 in entries 0142 * which correspond to no valid parent 0143 * @pll: information valid if type includes CGU_CLK_PLL 0144 * @gate: information valid if type includes CGU_CLK_GATE 0145 * @mux: information valid if type includes CGU_CLK_MUX 0146 * @div: information valid if type includes CGU_CLK_DIV 0147 * @fixdiv: information valid if type includes CGU_CLK_FIXDIV 0148 * @custom: information valid if type includes CGU_CLK_CUSTOM 0149 */ 0150 struct ingenic_cgu_clk_info { 0151 const char *name; 0152 0153 enum { 0154 CGU_CLK_NONE = 0, 0155 CGU_CLK_EXT = BIT(0), 0156 CGU_CLK_PLL = BIT(1), 0157 CGU_CLK_GATE = BIT(2), 0158 CGU_CLK_MUX = BIT(3), 0159 CGU_CLK_MUX_GLITCHFREE = BIT(4), 0160 CGU_CLK_DIV = BIT(5), 0161 CGU_CLK_FIXDIV = BIT(6), 0162 CGU_CLK_CUSTOM = BIT(7), 0163 } type; 0164 0165 unsigned long flags; 0166 0167 int parents[4]; 0168 0169 union { 0170 struct ingenic_cgu_pll_info pll; 0171 0172 struct { 0173 struct ingenic_cgu_gate_info gate; 0174 struct ingenic_cgu_mux_info mux; 0175 struct ingenic_cgu_div_info div; 0176 struct ingenic_cgu_fixdiv_info fixdiv; 0177 }; 0178 0179 struct ingenic_cgu_custom_info custom; 0180 }; 0181 }; 0182 0183 /** 0184 * struct ingenic_cgu - data about the CGU 0185 * @np: the device tree node that caused the CGU to be probed 0186 * @base: the ioremap'ed base address of the CGU registers 0187 * @clock_info: an array containing information about implemented clocks 0188 * @clocks: used to provide clocks to DT, allows lookup of struct clk* 0189 * @lock: lock to be held whilst manipulating CGU registers 0190 */ 0191 struct ingenic_cgu { 0192 struct device_node *np; 0193 void __iomem *base; 0194 0195 const struct ingenic_cgu_clk_info *clock_info; 0196 struct clk_onecell_data clocks; 0197 0198 spinlock_t lock; 0199 }; 0200 0201 /** 0202 * struct ingenic_clk - private data for a clock 0203 * @hw: see Documentation/driver-api/clk.rst 0204 * @cgu: a pointer to the CGU data 0205 * @idx: the index of this clock in cgu->clock_info 0206 */ 0207 struct ingenic_clk { 0208 struct clk_hw hw; 0209 struct ingenic_cgu *cgu; 0210 unsigned idx; 0211 }; 0212 0213 #define to_ingenic_clk(_hw) container_of(_hw, struct ingenic_clk, hw) 0214 0215 /** 0216 * ingenic_cgu_new() - create a new CGU instance 0217 * @clock_info: an array of clock information structures describing the clocks 0218 * which are implemented by the CGU 0219 * @num_clocks: the number of entries in clock_info 0220 * @np: the device tree node which causes this CGU to be probed 0221 * 0222 * Return: a pointer to the CGU instance if initialisation is successful, 0223 * otherwise NULL. 0224 */ 0225 struct ingenic_cgu * 0226 ingenic_cgu_new(const struct ingenic_cgu_clk_info *clock_info, 0227 unsigned num_clocks, struct device_node *np); 0228 0229 /** 0230 * ingenic_cgu_register_clocks() - Registers the clocks 0231 * @cgu: pointer to cgu data 0232 * 0233 * Register the clocks described by the CGU with the common clock framework. 0234 * 0235 * Return: 0 on success or -errno if unsuccesful. 0236 */ 0237 int ingenic_cgu_register_clocks(struct ingenic_cgu *cgu); 0238 0239 #endif /* __DRIVERS_CLK_INGENIC_CGU_H__ */
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