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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2012 Freescale Semiconductor, Inc.
0004  * Copyright 2012 Linaro Ltd.
0005  */
0006 
0007 #include <linux/clk-provider.h>
0008 #include <linux/delay.h>
0009 #include <linux/io.h>
0010 #include <linux/iopoll.h>
0011 #include <linux/slab.h>
0012 #include <linux/jiffies.h>
0013 #include <linux/err.h>
0014 #include "clk.h"
0015 
0016 #define PLL_NUM_OFFSET      0x10
0017 #define PLL_DENOM_OFFSET    0x20
0018 #define PLL_IMX7_NUM_OFFSET 0x20
0019 #define PLL_IMX7_DENOM_OFFSET   0x30
0020 
0021 #define PLL_VF610_NUM_OFFSET    0x20
0022 #define PLL_VF610_DENOM_OFFSET  0x30
0023 
0024 #define BM_PLL_POWER        (0x1 << 12)
0025 #define BM_PLL_LOCK     (0x1 << 31)
0026 #define IMX7_ENET_PLL_POWER (0x1 << 5)
0027 #define IMX7_DDR_PLL_POWER  (0x1 << 20)
0028 
0029 #define PLL_LOCK_TIMEOUT    10000
0030 
0031 /**
0032  * struct clk_pllv3 - IMX PLL clock version 3
0033  * @hw:     clock source
0034  * @base:    base address of PLL registers
0035  * @power_bit:   pll power bit mask
0036  * @powerup_set: set power_bit to power up the PLL
0037  * @div_mask:    mask of divider bits
0038  * @div_shift:   shift of divider bits
0039  * @ref_clock:  reference clock rate
0040  * @num_offset: num register offset
0041  * @denom_offset: denom register offset
0042  *
0043  * IMX PLL clock version 3, found on i.MX6 series.  Divider for pllv3
0044  * is actually a multiplier, and always sits at bit 0.
0045  */
0046 struct clk_pllv3 {
0047     struct clk_hw   hw;
0048     void __iomem    *base;
0049     u32     power_bit;
0050     bool        powerup_set;
0051     u32     div_mask;
0052     u32     div_shift;
0053     unsigned long   ref_clock;
0054     u32     num_offset;
0055     u32     denom_offset;
0056 };
0057 
0058 #define to_clk_pllv3(_hw) container_of(_hw, struct clk_pllv3, hw)
0059 
0060 static int clk_pllv3_wait_lock(struct clk_pllv3 *pll)
0061 {
0062     u32 val = readl_relaxed(pll->base) & pll->power_bit;
0063 
0064     /* No need to wait for lock when pll is not powered up */
0065     if ((pll->powerup_set && !val) || (!pll->powerup_set && val))
0066         return 0;
0067 
0068     return readl_relaxed_poll_timeout(pll->base, val, val & BM_PLL_LOCK,
0069                       500, PLL_LOCK_TIMEOUT);
0070 }
0071 
0072 static int clk_pllv3_prepare(struct clk_hw *hw)
0073 {
0074     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0075     u32 val;
0076 
0077     val = readl_relaxed(pll->base);
0078     if (pll->powerup_set)
0079         val |= pll->power_bit;
0080     else
0081         val &= ~pll->power_bit;
0082     writel_relaxed(val, pll->base);
0083 
0084     return clk_pllv3_wait_lock(pll);
0085 }
0086 
0087 static void clk_pllv3_unprepare(struct clk_hw *hw)
0088 {
0089     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0090     u32 val;
0091 
0092     val = readl_relaxed(pll->base);
0093     if (pll->powerup_set)
0094         val &= ~pll->power_bit;
0095     else
0096         val |= pll->power_bit;
0097     writel_relaxed(val, pll->base);
0098 }
0099 
0100 static int clk_pllv3_is_prepared(struct clk_hw *hw)
0101 {
0102     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0103 
0104     if (readl_relaxed(pll->base) & BM_PLL_LOCK)
0105         return 1;
0106 
0107     return 0;
0108 }
0109 
0110 static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
0111                        unsigned long parent_rate)
0112 {
0113     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0114     u32 div = (readl_relaxed(pll->base) >> pll->div_shift)  & pll->div_mask;
0115 
0116     return (div == 1) ? parent_rate * 22 : parent_rate * 20;
0117 }
0118 
0119 static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
0120                  unsigned long *prate)
0121 {
0122     unsigned long parent_rate = *prate;
0123 
0124     return (rate >= parent_rate * 22) ? parent_rate * 22 :
0125                         parent_rate * 20;
0126 }
0127 
0128 static int clk_pllv3_set_rate(struct clk_hw *hw, unsigned long rate,
0129         unsigned long parent_rate)
0130 {
0131     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0132     u32 val, div;
0133 
0134     if (rate == parent_rate * 22)
0135         div = 1;
0136     else if (rate == parent_rate * 20)
0137         div = 0;
0138     else
0139         return -EINVAL;
0140 
0141     val = readl_relaxed(pll->base);
0142     val &= ~(pll->div_mask << pll->div_shift);
0143     val |= (div << pll->div_shift);
0144     writel_relaxed(val, pll->base);
0145 
0146     return clk_pllv3_wait_lock(pll);
0147 }
0148 
0149 static const struct clk_ops clk_pllv3_ops = {
0150     .prepare    = clk_pllv3_prepare,
0151     .unprepare  = clk_pllv3_unprepare,
0152     .is_prepared    = clk_pllv3_is_prepared,
0153     .recalc_rate    = clk_pllv3_recalc_rate,
0154     .round_rate = clk_pllv3_round_rate,
0155     .set_rate   = clk_pllv3_set_rate,
0156 };
0157 
0158 static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
0159                            unsigned long parent_rate)
0160 {
0161     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0162     u32 div = readl_relaxed(pll->base) & pll->div_mask;
0163 
0164     return parent_rate * div / 2;
0165 }
0166 
0167 static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
0168                      unsigned long *prate)
0169 {
0170     unsigned long parent_rate = *prate;
0171     unsigned long min_rate = parent_rate * 54 / 2;
0172     unsigned long max_rate = parent_rate * 108 / 2;
0173     u32 div;
0174 
0175     if (rate > max_rate)
0176         rate = max_rate;
0177     else if (rate < min_rate)
0178         rate = min_rate;
0179     div = rate * 2 / parent_rate;
0180 
0181     return parent_rate * div / 2;
0182 }
0183 
0184 static int clk_pllv3_sys_set_rate(struct clk_hw *hw, unsigned long rate,
0185         unsigned long parent_rate)
0186 {
0187     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0188     unsigned long min_rate = parent_rate * 54 / 2;
0189     unsigned long max_rate = parent_rate * 108 / 2;
0190     u32 val, div;
0191 
0192     if (rate < min_rate || rate > max_rate)
0193         return -EINVAL;
0194 
0195     div = rate * 2 / parent_rate;
0196     val = readl_relaxed(pll->base);
0197     val &= ~pll->div_mask;
0198     val |= div;
0199     writel_relaxed(val, pll->base);
0200 
0201     return clk_pllv3_wait_lock(pll);
0202 }
0203 
0204 static const struct clk_ops clk_pllv3_sys_ops = {
0205     .prepare    = clk_pllv3_prepare,
0206     .unprepare  = clk_pllv3_unprepare,
0207     .is_prepared    = clk_pllv3_is_prepared,
0208     .recalc_rate    = clk_pllv3_sys_recalc_rate,
0209     .round_rate = clk_pllv3_sys_round_rate,
0210     .set_rate   = clk_pllv3_sys_set_rate,
0211 };
0212 
0213 static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
0214                           unsigned long parent_rate)
0215 {
0216     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0217     u32 mfn = readl_relaxed(pll->base + pll->num_offset);
0218     u32 mfd = readl_relaxed(pll->base + pll->denom_offset);
0219     u32 div = readl_relaxed(pll->base) & pll->div_mask;
0220     u64 temp64 = (u64)parent_rate;
0221 
0222     temp64 *= mfn;
0223     do_div(temp64, mfd);
0224 
0225     return parent_rate * div + (unsigned long)temp64;
0226 }
0227 
0228 static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
0229                     unsigned long *prate)
0230 {
0231     unsigned long parent_rate = *prate;
0232     unsigned long min_rate = parent_rate * 27;
0233     unsigned long max_rate = parent_rate * 54;
0234     u32 div;
0235     u32 mfn, mfd = 1000000;
0236     u32 max_mfd = 0x3FFFFFFF;
0237     u64 temp64;
0238 
0239     if (rate > max_rate)
0240         rate = max_rate;
0241     else if (rate < min_rate)
0242         rate = min_rate;
0243 
0244     if (parent_rate <= max_mfd)
0245         mfd = parent_rate;
0246 
0247     div = rate / parent_rate;
0248     temp64 = (u64) (rate - div * parent_rate);
0249     temp64 *= mfd;
0250     temp64 = div64_ul(temp64, parent_rate);
0251     mfn = temp64;
0252 
0253     temp64 = (u64)parent_rate;
0254     temp64 *= mfn;
0255     do_div(temp64, mfd);
0256 
0257     return parent_rate * div + (unsigned long)temp64;
0258 }
0259 
0260 static int clk_pllv3_av_set_rate(struct clk_hw *hw, unsigned long rate,
0261         unsigned long parent_rate)
0262 {
0263     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0264     unsigned long min_rate = parent_rate * 27;
0265     unsigned long max_rate = parent_rate * 54;
0266     u32 val, div;
0267     u32 mfn, mfd = 1000000;
0268     u32 max_mfd = 0x3FFFFFFF;
0269     u64 temp64;
0270 
0271     if (rate < min_rate || rate > max_rate)
0272         return -EINVAL;
0273 
0274     if (parent_rate <= max_mfd)
0275         mfd = parent_rate;
0276 
0277     div = rate / parent_rate;
0278     temp64 = (u64) (rate - div * parent_rate);
0279     temp64 *= mfd;
0280     temp64 = div64_ul(temp64, parent_rate);
0281     mfn = temp64;
0282 
0283     val = readl_relaxed(pll->base);
0284     val &= ~pll->div_mask;
0285     val |= div;
0286     writel_relaxed(val, pll->base);
0287     writel_relaxed(mfn, pll->base + pll->num_offset);
0288     writel_relaxed(mfd, pll->base + pll->denom_offset);
0289 
0290     return clk_pllv3_wait_lock(pll);
0291 }
0292 
0293 static const struct clk_ops clk_pllv3_av_ops = {
0294     .prepare    = clk_pllv3_prepare,
0295     .unprepare  = clk_pllv3_unprepare,
0296     .is_prepared    = clk_pllv3_is_prepared,
0297     .recalc_rate    = clk_pllv3_av_recalc_rate,
0298     .round_rate = clk_pllv3_av_round_rate,
0299     .set_rate   = clk_pllv3_av_set_rate,
0300 };
0301 
0302 struct clk_pllv3_vf610_mf {
0303     u32 mfi;    /* integer part, can be 20 or 22 */
0304     u32 mfn;    /* numerator, 30-bit value */
0305     u32 mfd;    /* denominator, 30-bit value, must be less than mfn */
0306 };
0307 
0308 static unsigned long clk_pllv3_vf610_mf_to_rate(unsigned long parent_rate,
0309         struct clk_pllv3_vf610_mf mf)
0310 {
0311     u64 temp64;
0312 
0313     temp64 = parent_rate;
0314     temp64 *= mf.mfn;
0315     do_div(temp64, mf.mfd);
0316 
0317     return (parent_rate * mf.mfi) + temp64;
0318 }
0319 
0320 static struct clk_pllv3_vf610_mf clk_pllv3_vf610_rate_to_mf(
0321         unsigned long parent_rate, unsigned long rate)
0322 {
0323     struct clk_pllv3_vf610_mf mf;
0324     u64 temp64;
0325 
0326     mf.mfi = (rate >= 22 * parent_rate) ? 22 : 20;
0327     mf.mfd = 0x3fffffff;    /* use max supported value for best accuracy */
0328 
0329     if (rate <= parent_rate * mf.mfi)
0330         mf.mfn = 0;
0331     else if (rate >= parent_rate * (mf.mfi + 1))
0332         mf.mfn = mf.mfd - 1;
0333     else {
0334         /* rate = parent_rate * (mfi + mfn/mfd) */
0335         temp64 = rate - parent_rate * mf.mfi;
0336         temp64 *= mf.mfd;
0337         temp64 = div64_ul(temp64, parent_rate);
0338         mf.mfn = temp64;
0339     }
0340 
0341     return mf;
0342 }
0343 
0344 static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
0345                           unsigned long parent_rate)
0346 {
0347     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0348     struct clk_pllv3_vf610_mf mf;
0349 
0350     mf.mfn = readl_relaxed(pll->base + pll->num_offset);
0351     mf.mfd = readl_relaxed(pll->base + pll->denom_offset);
0352     mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20;
0353 
0354     return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
0355 }
0356 
0357 static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
0358                     unsigned long *prate)
0359 {
0360     struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
0361 
0362     return clk_pllv3_vf610_mf_to_rate(*prate, mf);
0363 }
0364 
0365 static int clk_pllv3_vf610_set_rate(struct clk_hw *hw, unsigned long rate,
0366         unsigned long parent_rate)
0367 {
0368     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0369     struct clk_pllv3_vf610_mf mf =
0370             clk_pllv3_vf610_rate_to_mf(parent_rate, rate);
0371     u32 val;
0372 
0373     val = readl_relaxed(pll->base);
0374     if (mf.mfi == 20)
0375         val &= ~pll->div_mask;  /* clear bit for mfi=20 */
0376     else
0377         val |= pll->div_mask;   /* set bit for mfi=22 */
0378     writel_relaxed(val, pll->base);
0379 
0380     writel_relaxed(mf.mfn, pll->base + pll->num_offset);
0381     writel_relaxed(mf.mfd, pll->base + pll->denom_offset);
0382 
0383     return clk_pllv3_wait_lock(pll);
0384 }
0385 
0386 static const struct clk_ops clk_pllv3_vf610_ops = {
0387     .prepare    = clk_pllv3_prepare,
0388     .unprepare  = clk_pllv3_unprepare,
0389     .is_prepared    = clk_pllv3_is_prepared,
0390     .recalc_rate    = clk_pllv3_vf610_recalc_rate,
0391     .round_rate = clk_pllv3_vf610_round_rate,
0392     .set_rate   = clk_pllv3_vf610_set_rate,
0393 };
0394 
0395 static unsigned long clk_pllv3_enet_recalc_rate(struct clk_hw *hw,
0396                         unsigned long parent_rate)
0397 {
0398     struct clk_pllv3 *pll = to_clk_pllv3(hw);
0399 
0400     return pll->ref_clock;
0401 }
0402 
0403 static const struct clk_ops clk_pllv3_enet_ops = {
0404     .prepare    = clk_pllv3_prepare,
0405     .unprepare  = clk_pllv3_unprepare,
0406     .is_prepared    = clk_pllv3_is_prepared,
0407     .recalc_rate    = clk_pllv3_enet_recalc_rate,
0408 };
0409 
0410 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
0411               const char *parent_name, void __iomem *base,
0412               u32 div_mask)
0413 {
0414     struct clk_pllv3 *pll;
0415     const struct clk_ops *ops;
0416     struct clk_hw *hw;
0417     struct clk_init_data init;
0418     int ret;
0419 
0420     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0421     if (!pll)
0422         return ERR_PTR(-ENOMEM);
0423 
0424     pll->power_bit = BM_PLL_POWER;
0425     pll->num_offset = PLL_NUM_OFFSET;
0426     pll->denom_offset = PLL_DENOM_OFFSET;
0427 
0428     switch (type) {
0429     case IMX_PLLV3_SYS:
0430         ops = &clk_pllv3_sys_ops;
0431         break;
0432     case IMX_PLLV3_SYS_VF610:
0433         ops = &clk_pllv3_vf610_ops;
0434         pll->num_offset = PLL_VF610_NUM_OFFSET;
0435         pll->denom_offset = PLL_VF610_DENOM_OFFSET;
0436         break;
0437     case IMX_PLLV3_USB_VF610:
0438         pll->div_shift = 1;
0439         fallthrough;
0440     case IMX_PLLV3_USB:
0441         ops = &clk_pllv3_ops;
0442         pll->powerup_set = true;
0443         break;
0444     case IMX_PLLV3_AV_IMX7:
0445         pll->num_offset = PLL_IMX7_NUM_OFFSET;
0446         pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
0447         fallthrough;
0448     case IMX_PLLV3_AV:
0449         ops = &clk_pllv3_av_ops;
0450         break;
0451     case IMX_PLLV3_ENET_IMX7:
0452         pll->power_bit = IMX7_ENET_PLL_POWER;
0453         pll->ref_clock = 1000000000;
0454         ops = &clk_pllv3_enet_ops;
0455         break;
0456     case IMX_PLLV3_ENET:
0457         pll->ref_clock = 500000000;
0458         ops = &clk_pllv3_enet_ops;
0459         break;
0460     case IMX_PLLV3_DDR_IMX7:
0461         pll->power_bit = IMX7_DDR_PLL_POWER;
0462         pll->num_offset = PLL_IMX7_NUM_OFFSET;
0463         pll->denom_offset = PLL_IMX7_DENOM_OFFSET;
0464         ops = &clk_pllv3_av_ops;
0465         break;
0466     default:
0467         ops = &clk_pllv3_ops;
0468     }
0469     pll->base = base;
0470     pll->div_mask = div_mask;
0471 
0472     init.name = name;
0473     init.ops = ops;
0474     init.flags = 0;
0475     init.parent_names = &parent_name;
0476     init.num_parents = 1;
0477 
0478     pll->hw.init = &init;
0479     hw = &pll->hw;
0480 
0481     ret = clk_hw_register(NULL, hw);
0482     if (ret) {
0483         kfree(pll);
0484         return ERR_PTR(ret);
0485     }
0486 
0487     return hw;
0488 }
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