clk/imx/clk-imxrt1050.c

0001 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
0002 /*
0003  * Copyright (C) 2021
0004  * Author(s):
0005  * Jesse Taube <Mr.Bossman075@gmail.com>
0006  * Giulio Benetti <giulio.benetti@benettiengineering.com>
0007  */
0008 #include <linux/clk.h>
0009 #include <linux/of_address.h>
0010 #include <linux/of_irq.h>
0011 #include <linux/platform_device.h>
0012 #include <dt-bindings/clock/imxrt1050-clock.h>
0013
0014 #include "clk.h"
0015
0016 static const char * const pll_ref_sels[] = {"osc", "dummy", };
0017 static const char * const per_sels[] = {"ipg_pdof", "osc", };
0018 static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
0019 static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
0020 static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
0021 static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
0022 static const char *const pre_periph_sels[] = {
0023     "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
0024 static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
0025 static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
0026 static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
0027 static const char *const lcdif_sels[] = {
0028     "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m",
0029     "pll2_pfd1_594m", "pll3_pfd1_664_62m", };
0030 static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
0031 static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
0032
0033 static struct clk_hw **hws;
0034 static struct clk_hw_onecell_data *clk_hw_data;
0035
0036 static int imxrt1050_clocks_probe(struct platform_device *pdev)
0037 {
0038     void __iomem *ccm_base;
0039     void __iomem *pll_base;
0040     struct device *dev = &pdev->dev;
0041     struct device_node *np = dev->of_node;
0042     struct device_node *anp;
0043     int ret;
0044
0045     clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
0046                       IMXRT1050_CLK_END), GFP_KERNEL);
0047     if (WARN_ON(!clk_hw_data))
0048         return -ENOMEM;
0049
0050     clk_hw_data->num = IMXRT1050_CLK_END;
0051     hws = clk_hw_data->hws;
0052
0053     hws[IMXRT1050_CLK_OSC] = imx_obtain_fixed_clk_hw(np, "osc");
0054
0055     anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
0056     pll_base = of_iomap(anp, 0);
0057     of_node_put(anp);
0058     if (WARN_ON(!pll_base))
0059         return -ENOMEM;
0060
0061     /* Anatop clocks */
0062     hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
0063
0064     hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel",
0065         pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
0066     hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel",
0067         pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
0068     hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel",
0069         pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
0070     hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel",
0071         pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
0072
0073     hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1_arm",
0074         "pll1_arm_ref_sel", pll_base + 0x0, 0x7f);
0075     hws[IMXRT1050_CLK_PLL2_SYS] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2_sys",
0076         "pll2_sys_ref_sel", pll_base + 0x30, 0x1);
0077     hws[IMXRT1050_CLK_PLL3_USB_OTG] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
0078         "pll3_usb_otg_ref_sel", pll_base + 0x10, 0x1);
0079     hws[IMXRT1050_CLK_PLL5_VIDEO] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5_video",
0080         "pll5_video_ref_sel", pll_base + 0xa0, 0x7f);
0081
0082     /* PLL bypass out */
0083     hws[IMXRT1050_CLK_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", pll_base + 0x0, 16, 1,
0084         pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
0085     hws[IMXRT1050_CLK_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", pll_base + 0x30, 16, 1,
0086         pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
0087     hws[IMXRT1050_CLK_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", pll_base + 0x10, 16, 1,
0088         pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
0089     hws[IMXRT1050_CLK_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", pll_base + 0xa0, 16, 1,
0090         pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
0091
0092     hws[IMXRT1050_CLK_VIDEO_POST_DIV_SEL] = imx_clk_hw_divider("video_post_div_sel",
0093         "pll5_video", pll_base + 0xa0, 19, 2);
0094     hws[IMXRT1050_CLK_VIDEO_DIV] = imx_clk_hw_divider("video_div",
0095         "video_post_div_sel", pll_base + 0x170, 30, 2);
0096
0097     hws[IMXRT1050_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m",  "pll3_usb_otg", 1, 6);
0098
0099     hws[IMXRT1050_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_sys", pll_base + 0x100, 0);
0100     hws[IMXRT1050_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_sys", pll_base + 0x100, 1);
0101     hws[IMXRT1050_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_sys", pll_base + 0x100, 2);
0102     hws[IMXRT1050_CLK_PLL3_PFD1_664_62M] = imx_clk_hw_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", pll_base + 0xf0, 1);
0103     hws[IMXRT1050_CLK_PLL3_PFD3_454_74M] = imx_clk_hw_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", pll_base + 0xf0, 3);
0104
0105     /* CCM clocks */
0106     ccm_base = devm_platform_ioremap_resource(pdev, 0);
0107     if (WARN_ON(IS_ERR(ccm_base)))
0108         return PTR_ERR(ccm_base);
0109
0110     hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3);
0111     hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2,
0112         pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
0113     hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1,
0114         periph_sels, ARRAY_SIZE(periph_sels));
0115     hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1,
0116         usdhc_sels, ARRAY_SIZE(usdhc_sels));
0117     hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + 0x1c, 17, 1,
0118         usdhc_sels, ARRAY_SIZE(usdhc_sels));
0119     hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base + 0x24, 6, 1,
0120         lpuart_sels, ARRAY_SIZE(lpuart_sels));
0121     hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + 0x38, 15, 3,
0122         lcdif_sels, ARRAY_SIZE(lcdif_sels));
0123     hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel", ccm_base + 0x1C, 6, 1,
0124         per_sels, ARRAY_SIZE(per_sels));
0125     hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel", ccm_base + 0x14, 7, 1,
0126         semc_alt_sels, ARRAY_SIZE(semc_alt_sels));
0127     hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel", ccm_base + 0x14, 6, 1,
0128         semc_sels, ARRAY_SIZE(semc_sels), CLK_IS_CRITICAL);
0129
0130     hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb", "periph_sel", ccm_base + 0x14, 10, 3);
0131     hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg", "ahb", ccm_base + 0x14, 8, 2);
0132     hws[IMXRT1050_CLK_PER_PDOF] = imx_clk_hw_divider("per", "per_sel", ccm_base + 0x1C, 0, 5);
0133
0134     hws[IMXRT1050_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", ccm_base + 0x24, 11, 3);
0135     hws[IMXRT1050_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", ccm_base + 0x24, 16, 3);
0136     hws[IMXRT1050_CLK_LPUART_PODF] = imx_clk_hw_divider("lpuart_podf", "lpuart_sel", ccm_base + 0x24, 0, 6);
0137     hws[IMXRT1050_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_sel", ccm_base + 0x38, 12, 3);
0138     hws[IMXRT1050_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", ccm_base + 0x18, 23, 3);
0139
0140     hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2);
0141     hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4);
0142     hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24);
0143     hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10);
0144     hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6);
0145     hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7);
0146     imx_check_clk_hws(hws, IMXRT1050_CLK_END);
0147
0148     ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
0149     if (ret < 0) {
0150         dev_err(dev, "Failed to register clks for i.MXRT1050.\n");
0151         imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END);
0152     }
0153     return ret;
0154 }
0155 static const struct of_device_id imxrt1050_clk_of_match[] = {
0156     { .compatible = "fsl,imxrt1050-ccm" },
0157     { /* Sentinel */ }
0158 };
0159 MODULE_DEVICE_TABLE(of, imxrt1050_clk_of_match);
0160
0161 static struct platform_driver imxrt1050_clk_driver = {
0162     .probe = imxrt1050_clocks_probe,
0163     .driver = {
0164         .name = "imxrt1050-ccm",
0165         .of_match_table = imxrt1050_clk_of_match,
0166     },
0167 };
0168 module_platform_driver(imxrt1050_clk_driver);