clk/imx/clk-imx8qxp-lpcg.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2018 NXP
0004  *  Dong Aisheng <aisheng.dong@nxp.com>
0005  */
0006
0007 #include <linux/clk-provider.h>
0008 #include <linux/err.h>
0009 #include <linux/io.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/slab.h>
0017
0018 #include "clk-scu.h"
0019 #include "clk-imx8qxp-lpcg.h"
0020
0021 #include <dt-bindings/clock/imx8-clock.h>
0022
0023 /*
0024  * struct imx8qxp_lpcg_data - Description of one LPCG clock
0025  * @id: clock ID
0026  * @name: clock name
0027  * @parent: parent clock name
0028  * @flags: common clock flags
0029  * @offset: offset of this LPCG clock
0030  * @bit_idx: bit index of this LPCG clock
0031  * @hw_gate: whether supports HW autogate
0032  *
0033  * This structure describes one LPCG clock
0034  */
0035 struct imx8qxp_lpcg_data {
0036     int id;
0037     char *name;
0038     char *parent;
0039     unsigned long flags;
0040     u32 offset;
0041     u8 bit_idx;
0042     bool hw_gate;
0043 };
0044
0045 /*
0046  * struct imx8qxp_ss_lpcg - Description of one subsystem LPCG clocks
0047  * @lpcg: LPCG clocks array of one subsystem
0048  * @num_lpcg: the number of LPCG clocks
0049  * @num_max: the maximum number of LPCG clocks
0050  *
0051  * This structure describes each subsystem LPCG clocks information
0052  * which then will be used to create respective LPCGs clocks
0053  */
0054 struct imx8qxp_ss_lpcg {
0055     const struct imx8qxp_lpcg_data *lpcg;
0056     u8 num_lpcg;
0057     u8 num_max;
0058 };
0059
0060 static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
0061     { IMX_ADMA_LPCG_UART0_IPG_CLK, "uart0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_0_LPCG, 16, 0, },
0062     { IMX_ADMA_LPCG_UART0_BAUD_CLK, "uart0_lpcg_baud_clk", "uart0_clk", 0, ADMA_LPUART_0_LPCG, 0, 0, },
0063     { IMX_ADMA_LPCG_UART1_IPG_CLK, "uart1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_1_LPCG, 16, 0, },
0064     { IMX_ADMA_LPCG_UART1_BAUD_CLK, "uart1_lpcg_baud_clk", "uart1_clk", 0, ADMA_LPUART_1_LPCG, 0, 0, },
0065     { IMX_ADMA_LPCG_UART2_IPG_CLK, "uart2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_2_LPCG, 16, 0, },
0066     { IMX_ADMA_LPCG_UART2_BAUD_CLK, "uart2_lpcg_baud_clk", "uart2_clk", 0, ADMA_LPUART_2_LPCG, 0, 0, },
0067     { IMX_ADMA_LPCG_UART3_IPG_CLK, "uart3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPUART_3_LPCG, 16, 0, },
0068     { IMX_ADMA_LPCG_UART3_BAUD_CLK, "uart3_lpcg_baud_clk", "uart3_clk", 0, ADMA_LPUART_3_LPCG, 0, 0, },
0069     { IMX_ADMA_LPCG_I2C0_IPG_CLK, "i2c0_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_0_LPCG, 16, 0, },
0070     { IMX_ADMA_LPCG_I2C0_CLK, "i2c0_lpcg_clk", "i2c0_clk", 0, ADMA_LPI2C_0_LPCG, 0, 0, },
0071     { IMX_ADMA_LPCG_I2C1_IPG_CLK, "i2c1_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_1_LPCG, 16, 0, },
0072     { IMX_ADMA_LPCG_I2C1_CLK, "i2c1_lpcg_clk", "i2c1_clk", 0, ADMA_LPI2C_1_LPCG, 0, 0, },
0073     { IMX_ADMA_LPCG_I2C2_IPG_CLK, "i2c2_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_2_LPCG, 16, 0, },
0074     { IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
0075     { IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
0076     { IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
0077
0078     { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
0079     { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
0080     { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
0081     { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
0082 };
0083
0084 static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
0085     .lpcg = imx8qxp_lpcg_adma,
0086     .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_adma),
0087     .num_max = IMX_ADMA_LPCG_CLK_END,
0088 };
0089
0090 static const struct imx8qxp_lpcg_data imx8qxp_lpcg_conn[] = {
0091     { IMX_CONN_LPCG_SDHC0_PER_CLK, "sdhc0_lpcg_per_clk", "sdhc0_clk", 0, CONN_USDHC_0_LPCG, 0, 0, },
0092     { IMX_CONN_LPCG_SDHC0_IPG_CLK, "sdhc0_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_0_LPCG, 16, 0, },
0093     { IMX_CONN_LPCG_SDHC0_HCLK, "sdhc0_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_0_LPCG, 20, 0, },
0094     { IMX_CONN_LPCG_SDHC1_PER_CLK, "sdhc1_lpcg_per_clk", "sdhc1_clk", 0, CONN_USDHC_1_LPCG, 0, 0, },
0095     { IMX_CONN_LPCG_SDHC1_IPG_CLK, "sdhc1_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_1_LPCG, 16, 0, },
0096     { IMX_CONN_LPCG_SDHC1_HCLK, "sdhc1_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_1_LPCG, 20, 0, },
0097     { IMX_CONN_LPCG_SDHC2_PER_CLK, "sdhc2_lpcg_per_clk", "sdhc2_clk", 0, CONN_USDHC_2_LPCG, 0, 0, },
0098     { IMX_CONN_LPCG_SDHC2_IPG_CLK, "sdhc2_lpcg_ipg_clk", "conn_ipg_clk_root", 0, CONN_USDHC_2_LPCG, 16, 0, },
0099     { IMX_CONN_LPCG_SDHC2_HCLK, "sdhc2_lpcg_ahb_clk", "conn_axi_clk_root", 0, CONN_USDHC_2_LPCG, 20, 0, },
0100     { IMX_CONN_LPCG_ENET0_ROOT_CLK, "enet0_ipg_root_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 0, 0, },
0101     { IMX_CONN_LPCG_ENET0_TX_CLK, "enet0_tx_clk", "enet0_clk", 0, CONN_ENET_0_LPCG, 4, 0, },
0102     { IMX_CONN_LPCG_ENET0_AHB_CLK, "enet0_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_0_LPCG, 8, 0, },
0103     { IMX_CONN_LPCG_ENET0_IPG_S_CLK, "enet0_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_0_LPCG, 20, 0, },
0104     { IMX_CONN_LPCG_ENET0_IPG_CLK, "enet0_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_0_LPCG, 16, 0, },
0105     { IMX_CONN_LPCG_ENET1_ROOT_CLK, "enet1_ipg_root_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 0, 0, },
0106     { IMX_CONN_LPCG_ENET1_TX_CLK, "enet1_tx_clk", "enet1_clk", 0, CONN_ENET_1_LPCG, 4, 0, },
0107     { IMX_CONN_LPCG_ENET1_AHB_CLK, "enet1_ahb_clk", "conn_axi_clk_root", 0, CONN_ENET_1_LPCG, 8, 0, },
0108     { IMX_CONN_LPCG_ENET1_IPG_S_CLK, "enet1_ipg_s_clk", "conn_ipg_clk_root", 0, CONN_ENET_1_LPCG, 20, 0, },
0109     { IMX_CONN_LPCG_ENET1_IPG_CLK, "enet1_ipg_clk", "enet0_ipg_s_clk", 0, CONN_ENET_1_LPCG, 16, 0, },
0110 };
0111
0112 static const struct imx8qxp_ss_lpcg imx8qxp_ss_conn = {
0113     .lpcg = imx8qxp_lpcg_conn,
0114     .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_conn),
0115     .num_max = IMX_CONN_LPCG_CLK_END,
0116 };
0117
0118 static const struct imx8qxp_lpcg_data imx8qxp_lpcg_lsio[] = {
0119     { IMX_LSIO_LPCG_PWM0_IPG_CLK, "pwm0_lpcg_ipg_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 0, 0, },
0120     { IMX_LSIO_LPCG_PWM0_IPG_HF_CLK, "pwm0_lpcg_ipg_hf_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 4, 0, },
0121     { IMX_LSIO_LPCG_PWM0_IPG_S_CLK, "pwm0_lpcg_ipg_s_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 16, 0, },
0122     { IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK, "pwm0_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_0_LPCG, 20, 0, },
0123     { IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK, "pwm0_lpcg_ipg_mstr_clk", "pwm0_clk", 0, LSIO_PWM_0_LPCG, 24, 0, },
0124     { IMX_LSIO_LPCG_PWM1_IPG_CLK, "pwm1_lpcg_ipg_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 0, 0, },
0125     { IMX_LSIO_LPCG_PWM1_IPG_HF_CLK, "pwm1_lpcg_ipg_hf_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 4, 0, },
0126     { IMX_LSIO_LPCG_PWM1_IPG_S_CLK, "pwm1_lpcg_ipg_s_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 16, 0, },
0127     { IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK, "pwm1_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_1_LPCG, 20, 0, },
0128     { IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK, "pwm1_lpcg_ipg_mstr_clk", "pwm1_clk", 0, LSIO_PWM_1_LPCG, 24, 0, },
0129     { IMX_LSIO_LPCG_PWM2_IPG_CLK, "pwm2_lpcg_ipg_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 0, 0, },
0130     { IMX_LSIO_LPCG_PWM2_IPG_HF_CLK, "pwm2_lpcg_ipg_hf_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 4, 0, },
0131     { IMX_LSIO_LPCG_PWM2_IPG_S_CLK, "pwm2_lpcg_ipg_s_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 16, 0, },
0132     { IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK, "pwm2_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_2_LPCG, 20, 0, },
0133     { IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK, "pwm2_lpcg_ipg_mstr_clk", "pwm2_clk", 0, LSIO_PWM_2_LPCG, 24, 0, },
0134     { IMX_LSIO_LPCG_PWM3_IPG_CLK, "pwm3_lpcg_ipg_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 0, 0, },
0135     { IMX_LSIO_LPCG_PWM3_IPG_HF_CLK, "pwm3_lpcg_ipg_hf_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 4, 0, },
0136     { IMX_LSIO_LPCG_PWM3_IPG_S_CLK, "pwm3_lpcg_ipg_s_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 16, 0, },
0137     { IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK, "pwm3_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_3_LPCG, 20, 0, },
0138     { IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK, "pwm3_lpcg_ipg_mstr_clk", "pwm3_clk", 0, LSIO_PWM_3_LPCG, 24, 0, },
0139     { IMX_LSIO_LPCG_PWM4_IPG_CLK, "pwm4_lpcg_ipg_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 0, 0, },
0140     { IMX_LSIO_LPCG_PWM4_IPG_HF_CLK, "pwm4_lpcg_ipg_hf_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 4, 0, },
0141     { IMX_LSIO_LPCG_PWM4_IPG_S_CLK, "pwm4_lpcg_ipg_s_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 16, 0, },
0142     { IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK, "pwm4_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_4_LPCG, 20, 0, },
0143     { IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK, "pwm4_lpcg_ipg_mstr_clk", "pwm4_clk", 0, LSIO_PWM_4_LPCG, 24, 0, },
0144     { IMX_LSIO_LPCG_PWM5_IPG_CLK, "pwm5_lpcg_ipg_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 0, 0, },
0145     { IMX_LSIO_LPCG_PWM5_IPG_HF_CLK, "pwm5_lpcg_ipg_hf_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 4, 0, },
0146     { IMX_LSIO_LPCG_PWM5_IPG_S_CLK, "pwm5_lpcg_ipg_s_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 16, 0, },
0147     { IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK, "pwm5_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_5_LPCG, 20, 0, },
0148     { IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK, "pwm5_lpcg_ipg_mstr_clk", "pwm5_clk", 0, LSIO_PWM_5_LPCG, 24, 0, },
0149     { IMX_LSIO_LPCG_PWM6_IPG_CLK, "pwm6_lpcg_ipg_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 0, 0, },
0150     { IMX_LSIO_LPCG_PWM6_IPG_HF_CLK, "pwm6_lpcg_ipg_hf_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 4, 0, },
0151     { IMX_LSIO_LPCG_PWM6_IPG_S_CLK, "pwm6_lpcg_ipg_s_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 16, 0, },
0152     { IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK, "pwm6_lpcg_ipg_slv_clk", "lsio_bus_clk_root", 0, LSIO_PWM_6_LPCG, 20, 0, },
0153     { IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK, "pwm6_lpcg_ipg_mstr_clk", "pwm6_clk", 0, LSIO_PWM_6_LPCG, 24, 0, },
0154 };
0155
0156 static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
0157     .lpcg = imx8qxp_lpcg_lsio,
0158     .num_lpcg = ARRAY_SIZE(imx8qxp_lpcg_lsio),
0159     .num_max = IMX_LSIO_LPCG_CLK_END,
0160 };
0161
0162 #define IMX_LPCG_MAX_CLKS   8
0163
0164 static struct clk_hw *imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec,
0165                           void *data)
0166 {
0167     struct clk_hw_onecell_data *hw_data = data;
0168     unsigned int idx = clkspec->args[0] / 4;
0169
0170     if (idx >= hw_data->num) {
0171         pr_err("%s: invalid index %u\n", __func__, idx);
0172         return ERR_PTR(-EINVAL);
0173     }
0174
0175     return hw_data->hws[idx];
0176 }
0177
0178 static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
0179                        struct device_node *np)
0180 {
0181     const char *output_names[IMX_LPCG_MAX_CLKS];
0182     const char *parent_names[IMX_LPCG_MAX_CLKS];
0183     unsigned int bit_offset[IMX_LPCG_MAX_CLKS];
0184     struct clk_hw_onecell_data *clk_data;
0185     struct clk_hw **clk_hws;
0186     struct resource *res;
0187     void __iomem *base;
0188     int count;
0189     int idx;
0190     int ret;
0191     int i;
0192
0193     if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))
0194         return -EINVAL;
0195
0196     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0197     base = devm_ioremap_resource(&pdev->dev, res);
0198     if (IS_ERR(base))
0199         return PTR_ERR(base);
0200
0201     count = of_property_count_u32_elems(np, "clock-indices");
0202     if (count < 0) {
0203         dev_err(&pdev->dev, "failed to count clocks\n");
0204         return -EINVAL;
0205     }
0206
0207     /*
0208      * A trick here is that we set the num of clks to the MAX instead
0209      * of the count from clock-indices because one LPCG supports up to
0210      * 8 clock outputs which each of them is fixed to 4 bits. Then we can
0211      * easily get the clock by clk-indices (bit-offset) / 4.
0212      * And the cost is very limited few pointers.
0213      */
0214
0215     clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
0216                 IMX_LPCG_MAX_CLKS), GFP_KERNEL);
0217     if (!clk_data)
0218         return -ENOMEM;
0219
0220     clk_data->num = IMX_LPCG_MAX_CLKS;
0221     clk_hws = clk_data->hws;
0222
0223     ret = of_property_read_u32_array(np, "clock-indices", bit_offset,
0224                      count);
0225     if (ret < 0) {
0226         dev_err(&pdev->dev, "failed to read clock-indices\n");
0227         return -EINVAL;
0228     }
0229
0230     ret = of_clk_parent_fill(np, parent_names, count);
0231     if (ret != count) {
0232         dev_err(&pdev->dev, "failed to get clock parent names\n");
0233         return count;
0234     }
0235
0236     ret = of_property_read_string_array(np, "clock-output-names",
0237                         output_names, count);
0238     if (ret != count) {
0239         dev_err(&pdev->dev, "failed to read clock-output-names\n");
0240         return -EINVAL;
0241     }
0242
0243     pm_runtime_get_noresume(&pdev->dev);
0244     pm_runtime_set_active(&pdev->dev);
0245     pm_runtime_set_autosuspend_delay(&pdev->dev, 500);
0246     pm_runtime_use_autosuspend(&pdev->dev);
0247     pm_runtime_enable(&pdev->dev);
0248
0249     for (i = 0; i < count; i++) {
0250         idx = bit_offset[i] / 4;
0251         if (idx >= IMX_LPCG_MAX_CLKS) {
0252             dev_warn(&pdev->dev, "invalid bit offset of clock %d\n",
0253                  i);
0254             ret = -EINVAL;
0255             goto unreg;
0256         }
0257
0258         clk_hws[idx] = imx_clk_lpcg_scu_dev(&pdev->dev, output_names[i],
0259                             parent_names[i], 0, base,
0260                             bit_offset[i], false);
0261         if (IS_ERR(clk_hws[idx])) {
0262             dev_warn(&pdev->dev, "failed to register clock %d\n",
0263                  idx);
0264             ret = PTR_ERR(clk_hws[idx]);
0265             goto unreg;
0266         }
0267     }
0268
0269     ret = devm_of_clk_add_hw_provider(&pdev->dev, imx_lpcg_of_clk_src_get,
0270                       clk_data);
0271     if (ret)
0272         goto unreg;
0273
0274     pm_runtime_mark_last_busy(&pdev->dev);
0275     pm_runtime_put_autosuspend(&pdev->dev);
0276
0277     return 0;
0278
0279 unreg:
0280     while (--i >= 0) {
0281         idx = bit_offset[i] / 4;
0282         if (clk_hws[idx])
0283             imx_clk_lpcg_scu_unregister(clk_hws[idx]);
0284     }
0285
0286     pm_runtime_disable(&pdev->dev);
0287
0288     return ret;
0289 }
0290
0291 static int imx8qxp_lpcg_clk_probe(struct platform_device *pdev)
0292 {
0293     struct device *dev = &pdev->dev;
0294     struct device_node *np = dev->of_node;
0295     struct clk_hw_onecell_data *clk_data;
0296     const struct imx8qxp_ss_lpcg *ss_lpcg;
0297     const struct imx8qxp_lpcg_data *lpcg;
0298     struct resource *res;
0299     struct clk_hw **clks;
0300     void __iomem *base;
0301     int ret;
0302     int i;
0303
0304     /* try new binding to parse clocks from device tree first */
0305     ret = imx_lpcg_parse_clks_from_dt(pdev, np);
0306     if (!ret)
0307         return 0;
0308
0309     ss_lpcg = of_device_get_match_data(dev);
0310     if (!ss_lpcg)
0311         return -ENODEV;
0312
0313     /*
0314      * Please don't replace this with devm_platform_ioremap_resource.
0315      *
0316      * devm_platform_ioremap_resource calls devm_ioremap_resource which
0317      * differs from devm_ioremap by also calling devm_request_mem_region
0318      * and preventing other mappings in the same area.
0319      *
0320      * On imx8 the LPCG nodes map entire subsystems and overlap
0321      * peripherals, this means that using devm_platform_ioremap_resource
0322      * will cause many devices to fail to probe including serial ports.
0323      */
0324     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0325     if (!res)
0326         return -EINVAL;
0327     base = devm_ioremap(dev, res->start, resource_size(res));
0328     if (!base)
0329         return -ENOMEM;
0330
0331     clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws,
0332                 ss_lpcg->num_max), GFP_KERNEL);
0333     if (!clk_data)
0334         return -ENOMEM;
0335
0336     clk_data->num = ss_lpcg->num_max;
0337     clks = clk_data->hws;
0338
0339     for (i = 0; i < ss_lpcg->num_lpcg; i++) {
0340         lpcg = ss_lpcg->lpcg + i;
0341         clks[lpcg->id] = imx_clk_lpcg_scu(lpcg->name, lpcg->parent,
0342                           lpcg->flags, base + lpcg->offset,
0343                           lpcg->bit_idx, lpcg->hw_gate);
0344     }
0345
0346     for (i = 0; i < clk_data->num; i++) {
0347         if (IS_ERR(clks[i]))
0348             pr_warn("i.MX clk %u: register failed with %ld\n",
0349                 i, PTR_ERR(clks[i]));
0350     }
0351
0352     return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
0353 }
0354
0355 static const struct of_device_id imx8qxp_lpcg_match[] = {
0356     { .compatible = "fsl,imx8qxp-lpcg-adma", &imx8qxp_ss_adma, },
0357     { .compatible = "fsl,imx8qxp-lpcg-conn", &imx8qxp_ss_conn, },
0358     { .compatible = "fsl,imx8qxp-lpcg-lsio", &imx8qxp_ss_lsio, },
0359     { .compatible = "fsl,imx8qxp-lpcg", NULL },
0360     { /* sentinel */ }
0361 };
0362
0363 static struct platform_driver imx8qxp_lpcg_clk_driver = {
0364     .driver = {
0365         .name = "imx8qxp-lpcg-clk",
0366         .of_match_table = imx8qxp_lpcg_match,
0367         .pm = &imx_clk_lpcg_scu_pm_ops,
0368         .suppress_bind_attrs = true,
0369     },
0370     .probe = imx8qxp_lpcg_clk_probe,
0371 };
0372
0373 module_platform_driver(imx8qxp_lpcg_clk_driver);
0374
0375 MODULE_AUTHOR("Aisheng Dong <aisheng.dong@nxp.com>");
0376 MODULE_DESCRIPTION("NXP i.MX8QXP LPCG clock driver");
0377 MODULE_LICENSE("GPL v2");