clk/imx/clk-imx8qm-rsrc.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2019-2021 NXP
0004  *  Dong Aisheng <aisheng.dong@nxp.com>
0005  */
0006
0007 #include <dt-bindings/firmware/imx/rsrc.h>
0008
0009 #include "clk-scu.h"
0010
0011 /* Keep sorted in the ascending order */
0012 static const u32 imx8qm_clk_scu_rsrc_table[] = {
0013     IMX_SC_R_A53,
0014     IMX_SC_R_A72,
0015     IMX_SC_R_DC_0_VIDEO0,
0016     IMX_SC_R_DC_0_VIDEO1,
0017     IMX_SC_R_DC_0,
0018     IMX_SC_R_DC_0_PLL_0,
0019     IMX_SC_R_DC_0_PLL_1,
0020     IMX_SC_R_DC_1_VIDEO0,
0021     IMX_SC_R_DC_1_VIDEO1,
0022     IMX_SC_R_DC_1,
0023     IMX_SC_R_DC_1_PLL_0,
0024     IMX_SC_R_DC_1_PLL_1,
0025     IMX_SC_R_SPI_0,
0026     IMX_SC_R_SPI_1,
0027     IMX_SC_R_SPI_2,
0028     IMX_SC_R_SPI_3,
0029     IMX_SC_R_UART_0,
0030     IMX_SC_R_UART_1,
0031     IMX_SC_R_UART_2,
0032     IMX_SC_R_UART_3,
0033     IMX_SC_R_UART_4,
0034     IMX_SC_R_EMVSIM_0,
0035     IMX_SC_R_EMVSIM_1,
0036     IMX_SC_R_I2C_0,
0037     IMX_SC_R_I2C_1,
0038     IMX_SC_R_I2C_2,
0039     IMX_SC_R_I2C_3,
0040     IMX_SC_R_I2C_4,
0041     IMX_SC_R_ADC_0,
0042     IMX_SC_R_ADC_1,
0043     IMX_SC_R_FTM_0,
0044     IMX_SC_R_FTM_1,
0045     IMX_SC_R_CAN_0,
0046     IMX_SC_R_GPU_0_PID0,
0047     IMX_SC_R_GPU_1_PID0,
0048     IMX_SC_R_PWM_0,
0049     IMX_SC_R_PWM_1,
0050     IMX_SC_R_PWM_2,
0051     IMX_SC_R_PWM_3,
0052     IMX_SC_R_PWM_4,
0053     IMX_SC_R_PWM_5,
0054     IMX_SC_R_PWM_6,
0055     IMX_SC_R_PWM_7,
0056     IMX_SC_R_GPT_0,
0057     IMX_SC_R_GPT_1,
0058     IMX_SC_R_GPT_2,
0059     IMX_SC_R_GPT_3,
0060     IMX_SC_R_GPT_4,
0061     IMX_SC_R_FSPI_0,
0062     IMX_SC_R_FSPI_1,
0063     IMX_SC_R_SDHC_0,
0064     IMX_SC_R_SDHC_1,
0065     IMX_SC_R_SDHC_2,
0066     IMX_SC_R_ENET_0,
0067     IMX_SC_R_ENET_1,
0068     IMX_SC_R_MLB_0,
0069     IMX_SC_R_USB_2,
0070     IMX_SC_R_NAND,
0071     IMX_SC_R_LVDS_0,
0072     IMX_SC_R_LVDS_0_PWM_0,
0073     IMX_SC_R_LVDS_0_I2C_0,
0074     IMX_SC_R_LVDS_0_I2C_1,
0075     IMX_SC_R_LVDS_1,
0076     IMX_SC_R_LVDS_1_PWM_0,
0077     IMX_SC_R_LVDS_1_I2C_0,
0078     IMX_SC_R_LVDS_1_I2C_1,
0079     IMX_SC_R_M4_0_I2C,
0080     IMX_SC_R_M4_1_I2C,
0081     IMX_SC_R_AUDIO_PLL_0,
0082     IMX_SC_R_VPU_UART,
0083     IMX_SC_R_VPUCORE,
0084     IMX_SC_R_MIPI_0,
0085     IMX_SC_R_MIPI_0_PWM_0,
0086     IMX_SC_R_MIPI_0_I2C_0,
0087     IMX_SC_R_MIPI_0_I2C_1,
0088     IMX_SC_R_MIPI_1,
0089     IMX_SC_R_MIPI_1_PWM_0,
0090     IMX_SC_R_MIPI_1_I2C_0,
0091     IMX_SC_R_MIPI_1_I2C_1,
0092     IMX_SC_R_CSI_0,
0093     IMX_SC_R_CSI_0_PWM_0,
0094     IMX_SC_R_CSI_0_I2C_0,
0095     IMX_SC_R_CSI_1,
0096     IMX_SC_R_CSI_1_PWM_0,
0097     IMX_SC_R_CSI_1_I2C_0,
0098     IMX_SC_R_HDMI,
0099     IMX_SC_R_HDMI_I2S,
0100     IMX_SC_R_HDMI_I2C_0,
0101     IMX_SC_R_HDMI_PLL_0,
0102     IMX_SC_R_HDMI_RX,
0103     IMX_SC_R_HDMI_RX_BYPASS,
0104     IMX_SC_R_HDMI_RX_I2C_0,
0105     IMX_SC_R_AUDIO_PLL_1,
0106     IMX_SC_R_AUDIO_CLK_0,
0107     IMX_SC_R_AUDIO_CLK_1,
0108     IMX_SC_R_HDMI_RX_PWM_0,
0109     IMX_SC_R_HDMI_PLL_1,
0110     IMX_SC_R_VPU,
0111 };
0112
0113 const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8qm = {
0114     .rsrc = imx8qm_clk_scu_rsrc_table,
0115     .num = ARRAY_SIZE(imx8qm_clk_scu_rsrc_table),
0116 };