clk/imx/clk-imx8dxl-rsrc.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright 2019~2020 NXP
0004  */
0005
0006 #include <dt-bindings/firmware/imx/rsrc.h>
0007
0008 #include "clk-scu.h"
0009
0010 /* Keep sorted in the ascending order */
0011 static u32 imx8dxl_clk_scu_rsrc_table[] = {
0012     IMX_SC_R_SPI_0,
0013     IMX_SC_R_SPI_1,
0014     IMX_SC_R_SPI_2,
0015     IMX_SC_R_SPI_3,
0016     IMX_SC_R_UART_0,
0017     IMX_SC_R_UART_1,
0018     IMX_SC_R_UART_2,
0019     IMX_SC_R_UART_3,
0020     IMX_SC_R_I2C_0,
0021     IMX_SC_R_I2C_1,
0022     IMX_SC_R_I2C_2,
0023     IMX_SC_R_I2C_3,
0024     IMX_SC_R_ADC_0,
0025     IMX_SC_R_FTM_0,
0026     IMX_SC_R_FTM_1,
0027     IMX_SC_R_CAN_0,
0028     IMX_SC_R_LCD_0,
0029     IMX_SC_R_LCD_0_PWM_0,
0030     IMX_SC_R_PWM_0,
0031     IMX_SC_R_PWM_1,
0032     IMX_SC_R_PWM_2,
0033     IMX_SC_R_PWM_3,
0034     IMX_SC_R_PWM_4,
0035     IMX_SC_R_PWM_5,
0036     IMX_SC_R_PWM_6,
0037     IMX_SC_R_PWM_7,
0038     IMX_SC_R_GPT_0,
0039     IMX_SC_R_GPT_1,
0040     IMX_SC_R_GPT_2,
0041     IMX_SC_R_GPT_3,
0042     IMX_SC_R_GPT_4,
0043     IMX_SC_R_FSPI_0,
0044     IMX_SC_R_FSPI_1,
0045     IMX_SC_R_SDHC_0,
0046     IMX_SC_R_SDHC_1,
0047     IMX_SC_R_SDHC_2,
0048     IMX_SC_R_ENET_0,
0049     IMX_SC_R_ENET_1,
0050     IMX_SC_R_MLB_0,
0051     IMX_SC_R_USB_1,
0052     IMX_SC_R_NAND,
0053     IMX_SC_R_M4_0_I2C,
0054     IMX_SC_R_M4_0_UART,
0055     IMX_SC_R_ELCDIF_PLL,
0056     IMX_SC_R_AUDIO_PLL_0,
0057     IMX_SC_R_AUDIO_PLL_1,
0058     IMX_SC_R_AUDIO_CLK_0,
0059     IMX_SC_R_AUDIO_CLK_1,
0060     IMX_SC_R_A35
0061 };
0062
0063 const struct imx_clk_scu_rsrc_table imx_clk_scu_rsrc_imx8dxl = {
0064     .rsrc = imx8dxl_clk_scu_rsrc_table,
0065     .num = ARRAY_SIZE(imx8dxl_clk_scu_rsrc_table),
0066 };