clk/imx/clk-imx7ulp.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2016 Freescale Semiconductor, Inc.
0004  * Copyright 2017~2018 NXP
0005  *
0006  * Author: Dong Aisheng <aisheng.dong@nxp.com>
0007  *
0008  */
0009
0010 #include <dt-bindings/clock/imx7ulp-clock.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/err.h>
0013 #include <linux/init.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/slab.h>
0019
0020 #include "clk.h"
0021
0022 static const char * const pll_pre_sels[]    = { "sosc", "firc", };
0023 static const char * const spll_pfd_sels[]   = { "spll_pfd0", "spll_pfd1", "spll_pfd2", "spll_pfd3", };
0024 static const char * const spll_sels[]       = { "spll", "spll_pfd_sel", };
0025 static const char * const apll_pfd_sels[]   = { "apll_pfd0", "apll_pfd1", "apll_pfd2", "apll_pfd3", };
0026 static const char * const apll_sels[]       = { "apll", "apll_pfd_sel", };
0027 static const char * const scs_sels[]        = { "dummy", "sosc", "sirc", "firc", "dummy", "apll_sel", "spll_sel", "dummy", };
0028 static const char * const ddr_sels[]        = { "apll_pfd_sel", "dummy", "dummy", "dummy", };
0029 static const char * const nic_sels[]        = { "firc", "ddr_clk", };
0030 static const char * const periph_plat_sels[]    = { "dummy", "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", "upll", };
0031 static const char * const periph_bus_sels[] = { "dummy", "sosc_bus_clk", "dummy", "firc_bus_clk", "rosc", "nic1_bus_clk", "nic1_clk", "spll_bus_clk", };
0032 static const char * const arm_sels[]        = { "core", "dummy", "dummy", "hsrun_core", };
0033
0034 /* used by sosc/sirc/firc/ddr/spll/apll dividers */
0035 static const struct clk_div_table ulp_div_table[] = {
0036     { .val = 1, .div = 1, },
0037     { .val = 2, .div = 2, },
0038     { .val = 3, .div = 4, },
0039     { .val = 4, .div = 8, },
0040     { .val = 5, .div = 16, },
0041     { .val = 6, .div = 32, },
0042     { .val = 7, .div = 64, },
0043     { /* sentinel */ },
0044 };
0045
0046 static void __init imx7ulp_clk_scg1_init(struct device_node *np)
0047 {
0048     struct clk_hw_onecell_data *clk_data;
0049     struct clk_hw **hws;
0050     void __iomem *base;
0051
0052     clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SCG1_END),
0053                GFP_KERNEL);
0054     if (!clk_data)
0055         return;
0056
0057     clk_data->num = IMX7ULP_CLK_SCG1_END;
0058     hws = clk_data->hws;
0059
0060     hws[IMX7ULP_CLK_DUMMY]      = imx_clk_hw_fixed("dummy", 0);
0061
0062     hws[IMX7ULP_CLK_ROSC]       = imx_obtain_fixed_clk_hw(np, "rosc");
0063     hws[IMX7ULP_CLK_SOSC]       = imx_obtain_fixed_clk_hw(np, "sosc");
0064     hws[IMX7ULP_CLK_SIRC]       = imx_obtain_fixed_clk_hw(np, "sirc");
0065     hws[IMX7ULP_CLK_FIRC]       = imx_obtain_fixed_clk_hw(np, "firc");
0066     hws[IMX7ULP_CLK_UPLL]       = imx_obtain_fixed_clk_hw(np, "upll");
0067
0068     /* SCG1 */
0069     base = of_iomap(np, 0);
0070     WARN_ON(!base);
0071
0072     /* NOTE: xPLL config can't be changed when xPLL is enabled */
0073     hws[IMX7ULP_CLK_APLL_PRE_SEL]   = imx_clk_hw_mux_flags("apll_pre_sel", base + 0x508, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
0074     hws[IMX7ULP_CLK_SPLL_PRE_SEL]   = imx_clk_hw_mux_flags("spll_pre_sel", base + 0x608, 0, 1, pll_pre_sels, ARRAY_SIZE(pll_pre_sels), CLK_SET_PARENT_GATE);
0075
0076     /*                             name         parent_name    reg          shift   width   flags */
0077     hws[IMX7ULP_CLK_APLL_PRE_DIV]   = imx_clk_hw_divider_flags("apll_pre_div", "apll_pre_sel", base + 0x508,    8,  3,  CLK_SET_RATE_GATE);
0078     hws[IMX7ULP_CLK_SPLL_PRE_DIV]   = imx_clk_hw_divider_flags("spll_pre_div", "spll_pre_sel", base + 0x608,    8,  3,  CLK_SET_RATE_GATE);
0079
0080     /*                      name     parent_name     base */
0081     hws[IMX7ULP_CLK_APLL]       = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "apll",  "apll_pre_div", base + 0x500);
0082     hws[IMX7ULP_CLK_SPLL]       = imx_clk_hw_pllv4(IMX_PLLV4_IMX7ULP, "spll",  "spll_pre_div", base + 0x600);
0083
0084     /* APLL PFDs */
0085     hws[IMX7ULP_CLK_APLL_PFD0]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd0", "apll", base + 0x50c, 0);
0086     hws[IMX7ULP_CLK_APLL_PFD1]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd1", "apll", base + 0x50c, 1);
0087     hws[IMX7ULP_CLK_APLL_PFD2]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd2", "apll", base + 0x50c, 2);
0088     hws[IMX7ULP_CLK_APLL_PFD3]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "apll_pfd3", "apll", base + 0x50c, 3);
0089
0090     /* SPLL PFDs */
0091     hws[IMX7ULP_CLK_SPLL_PFD0]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd0", "spll", base + 0x60C, 0);
0092     hws[IMX7ULP_CLK_SPLL_PFD1]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd1", "spll", base + 0x60C, 1);
0093     hws[IMX7ULP_CLK_SPLL_PFD2]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd2", "spll", base + 0x60C, 2);
0094     hws[IMX7ULP_CLK_SPLL_PFD3]  = imx_clk_hw_pfdv2(IMX_PFDV2_IMX7ULP, "spll_pfd3", "spll", base + 0x60C, 3);
0095
0096     /* PLL Mux */
0097     hws[IMX7ULP_CLK_APLL_PFD_SEL]   = imx_clk_hw_mux_flags("apll_pfd_sel", base + 0x508, 14, 2, apll_pfd_sels, ARRAY_SIZE(apll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
0098     hws[IMX7ULP_CLK_SPLL_PFD_SEL]   = imx_clk_hw_mux_flags("spll_pfd_sel", base + 0x608, 14, 2, spll_pfd_sels, ARRAY_SIZE(spll_pfd_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
0099     hws[IMX7ULP_CLK_APLL_SEL]   = imx_clk_hw_mux_flags("apll_sel", base + 0x508, 1, 1, apll_sels, ARRAY_SIZE(apll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
0100     hws[IMX7ULP_CLK_SPLL_SEL]   = imx_clk_hw_mux_flags("spll_sel", base + 0x608, 1, 1, spll_sels, ARRAY_SIZE(spll_sels), CLK_SET_RATE_PARENT | CLK_SET_PARENT_GATE);
0101
0102     hws[IMX7ULP_CLK_SPLL_BUS_CLK]   = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_GATE, base + 0x604, 8, 3, 0, ulp_div_table, &imx_ccm_lock);
0103
0104     /* scs/ddr/nic select different clock source requires that clock to be enabled first */
0105     hws[IMX7ULP_CLK_SYS_SEL]    = imx_clk_hw_mux2("scs_sel", base + 0x14, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
0106     hws[IMX7ULP_CLK_HSRUN_SYS_SEL] = imx_clk_hw_mux2("hsrun_scs_sel", base + 0x1c, 24, 4, scs_sels, ARRAY_SIZE(scs_sels));
0107     hws[IMX7ULP_CLK_NIC_SEL]    = imx_clk_hw_mux2("nic_sel", base + 0x40, 28, 1, nic_sels, ARRAY_SIZE(nic_sels));
0108     hws[IMX7ULP_CLK_DDR_SEL]    = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
0109
0110     hws[IMX7ULP_CLK_CORE_DIV]   = imx_clk_hw_divider_flags("divcore",   "scs_sel",  base + 0x14, 16, 4, CLK_SET_RATE_PARENT);
0111     hws[IMX7ULP_CLK_CORE]       = imx_clk_hw_cpu("core", "divcore", hws[IMX7ULP_CLK_CORE_DIV]->clk, hws[IMX7ULP_CLK_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk);
0112     hws[IMX7ULP_CLK_HSRUN_CORE_DIV] = imx_clk_hw_divider_flags("hsrun_divcore", "hsrun_scs_sel", base + 0x1c, 16, 4, CLK_SET_RATE_PARENT);
0113     hws[IMX7ULP_CLK_HSRUN_CORE] = imx_clk_hw_cpu("hsrun_core", "hsrun_divcore", hws[IMX7ULP_CLK_HSRUN_CORE_DIV]->clk, hws[IMX7ULP_CLK_HSRUN_SYS_SEL]->clk, hws[IMX7ULP_CLK_SPLL_SEL]->clk, hws[IMX7ULP_CLK_FIRC]->clk);
0114
0115     hws[IMX7ULP_CLK_DDR_DIV]    = imx_clk_hw_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, base + 0x30, 0, 3,
0116                                    0, ulp_div_table, &imx_ccm_lock);
0117
0118     hws[IMX7ULP_CLK_NIC0_DIV]   = imx_clk_hw_divider_flags("nic0_clk",      "nic_sel",  base + 0x40, 24, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
0119     hws[IMX7ULP_CLK_NIC1_DIV]   = imx_clk_hw_divider_flags("nic1_clk",      "nic0_clk", base + 0x40, 16, 4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
0120     hws[IMX7ULP_CLK_NIC1_BUS_DIV]   = imx_clk_hw_divider_flags("nic1_bus_clk",  "nic0_clk", base + 0x40, 4,  4, CLK_SET_RATE_PARENT | CLK_IS_CRITICAL);
0121
0122     hws[IMX7ULP_CLK_GPU_DIV]    = imx_clk_hw_divider("gpu_clk", "nic0_clk", base + 0x40, 20, 4);
0123
0124     hws[IMX7ULP_CLK_SOSC_BUS_CLK]   = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, 3,
0125                                    CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);
0126     hws[IMX7ULP_CLK_FIRC_BUS_CLK]   = imx_clk_hw_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, 3,
0127                                    CLK_DIVIDER_READ_ONLY, ulp_div_table, &imx_ccm_lock);
0128
0129     imx_check_clk_hws(hws, clk_data->num);
0130
0131     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
0132 }
0133 CLK_OF_DECLARE(imx7ulp_clk_scg1, "fsl,imx7ulp-scg1", imx7ulp_clk_scg1_init);
0134
0135 static void __init imx7ulp_clk_pcc2_init(struct device_node *np)
0136 {
0137     struct clk_hw_onecell_data *clk_data;
0138     struct clk_hw **hws;
0139     void __iomem *base;
0140
0141     clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC2_END),
0142                GFP_KERNEL);
0143     if (!clk_data)
0144         return;
0145
0146     clk_data->num = IMX7ULP_CLK_PCC2_END;
0147     hws = clk_data->hws;
0148
0149     /* PCC2 */
0150     base = of_iomap(np, 0);
0151     WARN_ON(!base);
0152
0153     hws[IMX7ULP_CLK_DMA1]       = imx_clk_hw_gate("dma1", "nic1_clk", base + 0x20, 30);
0154     hws[IMX7ULP_CLK_RGPIO2P1]   = imx_clk_hw_gate("rgpio2p1", "nic1_bus_clk", base + 0x3c, 30);
0155     hws[IMX7ULP_CLK_DMA_MUX1]   = imx_clk_hw_gate("dma_mux1", "nic1_bus_clk", base + 0x84, 30);
0156     hws[IMX7ULP_CLK_CAAM]       = imx_clk_hw_gate("caam", "nic1_clk", base + 0x90, 30);
0157     hws[IMX7ULP_CLK_LPTPM4]     = imx7ulp_clk_hw_composite("lptpm4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
0158     hws[IMX7ULP_CLK_LPTPM5]     = imx7ulp_clk_hw_composite("lptpm5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
0159     hws[IMX7ULP_CLK_LPIT1]      = imx7ulp_clk_hw_composite("lpit1",   periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
0160     hws[IMX7ULP_CLK_LPSPI2]     = imx7ulp_clk_hw_composite("lpspi2",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa4);
0161     hws[IMX7ULP_CLK_LPSPI3]     = imx7ulp_clk_hw_composite("lpspi3",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xa8);
0162     hws[IMX7ULP_CLK_LPI2C4]     = imx7ulp_clk_hw_composite("lpi2c4",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xac);
0163     hws[IMX7ULP_CLK_LPI2C5]     = imx7ulp_clk_hw_composite("lpi2c5",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb0);
0164     hws[IMX7ULP_CLK_LPUART4]    = imx7ulp_clk_hw_composite("lpuart4", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb4);
0165     hws[IMX7ULP_CLK_LPUART5]    = imx7ulp_clk_hw_composite("lpuart5", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xb8);
0166     hws[IMX7ULP_CLK_FLEXIO1]    = imx7ulp_clk_hw_composite("flexio1", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0xc4);
0167     hws[IMX7ULP_CLK_USB0]       = imx7ulp_clk_hw_composite("usb0",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xcc);
0168     hws[IMX7ULP_CLK_USB1]       = imx7ulp_clk_hw_composite("usb1",    periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xd0);
0169     hws[IMX7ULP_CLK_USB_PHY]    = imx_clk_hw_gate("usb_phy", "nic1_bus_clk", base + 0xd4, 30);
0170     hws[IMX7ULP_CLK_USDHC0]     = imx7ulp_clk_hw_composite("usdhc0",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xdc);
0171     hws[IMX7ULP_CLK_USDHC1]     = imx7ulp_clk_hw_composite("usdhc1",  periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xe0);
0172     hws[IMX7ULP_CLK_WDG1]       = imx7ulp_clk_hw_composite("wdg1",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xf4);
0173     hws[IMX7ULP_CLK_WDG2]       = imx7ulp_clk_hw_composite("wdg2",    periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0x10c);
0174
0175     imx_check_clk_hws(hws, clk_data->num);
0176
0177     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
0178
0179     imx_register_uart_clocks(2);
0180 }
0181 CLK_OF_DECLARE(imx7ulp_clk_pcc2, "fsl,imx7ulp-pcc2", imx7ulp_clk_pcc2_init);
0182
0183 static void __init imx7ulp_clk_pcc3_init(struct device_node *np)
0184 {
0185     struct clk_hw_onecell_data *clk_data;
0186     struct clk_hw **hws;
0187     void __iomem *base;
0188
0189     clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_PCC3_END),
0190                GFP_KERNEL);
0191     if (!clk_data)
0192         return;
0193
0194     clk_data->num = IMX7ULP_CLK_PCC3_END;
0195     hws = clk_data->hws;
0196
0197     /* PCC3 */
0198     base = of_iomap(np, 0);
0199     WARN_ON(!base);
0200
0201     hws[IMX7ULP_CLK_LPTPM6] = imx7ulp_clk_hw_composite("lptpm6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x84);
0202     hws[IMX7ULP_CLK_LPTPM7] = imx7ulp_clk_hw_composite("lptpm7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x88);
0203
0204     hws[IMX7ULP_CLK_MMDC]       = clk_hw_register_gate(NULL, "mmdc", "nic1_clk", CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,
0205                                    base + 0xac, 30, 0, &imx_ccm_lock);
0206     hws[IMX7ULP_CLK_LPI2C6] = imx7ulp_clk_hw_composite("lpi2c6",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x90);
0207     hws[IMX7ULP_CLK_LPI2C7] = imx7ulp_clk_hw_composite("lpi2c7",  periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x94);
0208     hws[IMX7ULP_CLK_LPUART6]    = imx7ulp_clk_hw_composite("lpuart6", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x98);
0209     hws[IMX7ULP_CLK_LPUART7]    = imx7ulp_clk_hw_composite("lpuart7", periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, false, true, base + 0x9c);
0210     hws[IMX7ULP_CLK_DSI]        = imx7ulp_clk_hw_composite("dsi",     periph_bus_sels, ARRAY_SIZE(periph_bus_sels), true, true,  true, base + 0xa4);
0211     hws[IMX7ULP_CLK_LCDIF]      = imx7ulp_clk_hw_composite("lcdif",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, true,  true, base + 0xa8);
0212
0213     hws[IMX7ULP_CLK_VIU]        = imx_clk_hw_gate("viu",   "nic1_clk",     base + 0xa0, 30);
0214     hws[IMX7ULP_CLK_PCTLC]      = imx_clk_hw_gate("pctlc", "nic1_bus_clk", base + 0xb8, 30);
0215     hws[IMX7ULP_CLK_PCTLD]      = imx_clk_hw_gate("pctld", "nic1_bus_clk", base + 0xbc, 30);
0216     hws[IMX7ULP_CLK_PCTLE]      = imx_clk_hw_gate("pctle", "nic1_bus_clk", base + 0xc0, 30);
0217     hws[IMX7ULP_CLK_PCTLF]      = imx_clk_hw_gate("pctlf", "nic1_bus_clk", base + 0xc4, 30);
0218
0219     hws[IMX7ULP_CLK_GPU3D]      = imx7ulp_clk_hw_composite("gpu3d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x140);
0220     hws[IMX7ULP_CLK_GPU2D]      = imx7ulp_clk_hw_composite("gpu2d",   periph_plat_sels, ARRAY_SIZE(periph_plat_sels), true, false, true, base + 0x144);
0221
0222     imx_check_clk_hws(hws, clk_data->num);
0223
0224     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
0225
0226     imx_register_uart_clocks(7);
0227 }
0228 CLK_OF_DECLARE(imx7ulp_clk_pcc3, "fsl,imx7ulp-pcc3", imx7ulp_clk_pcc3_init);
0229
0230 static void __init imx7ulp_clk_smc1_init(struct device_node *np)
0231 {
0232     struct clk_hw_onecell_data *clk_data;
0233     struct clk_hw **hws;
0234     void __iomem *base;
0235
0236     clk_data = kzalloc(struct_size(clk_data, hws, IMX7ULP_CLK_SMC1_END),
0237                GFP_KERNEL);
0238     if (!clk_data)
0239         return;
0240
0241     clk_data->num = IMX7ULP_CLK_SMC1_END;
0242     hws = clk_data->hws;
0243
0244     /* SMC1 */
0245     base = of_iomap(np, 0);
0246     WARN_ON(!base);
0247
0248     hws[IMX7ULP_CLK_ARM] = imx_clk_hw_mux_flags("arm", base + 0x10, 8, 2, arm_sels, ARRAY_SIZE(arm_sels), CLK_SET_RATE_PARENT);
0249
0250     imx_check_clk_hws(hws, clk_data->num);
0251
0252     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
0253 }
0254 CLK_OF_DECLARE(imx7ulp_clk_smc1, "fsl,imx7ulp-smc1", imx7ulp_clk_smc1_init);