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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2015 Freescale Semiconductor, Inc.
0004  */
0005 
0006 #include <dt-bindings/clock/imx6ul-clock.h>
0007 #include <linux/clk.h>
0008 #include <linux/clkdev.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/err.h>
0011 #include <linux/init.h>
0012 #include <linux/io.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_irq.h>
0016 #include <linux/types.h>
0017 
0018 #include "clk.h"
0019 
0020 static const char *pll_bypass_src_sels[] = { "osc", "dummy", };
0021 static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
0022 static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
0023 static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
0024 static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
0025 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
0026 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
0027 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
0028 static const char *ca7_secondary_sels[] = { "pll2_pfd2_396m", "pll2_bus", };
0029 static const char *step_sels[] = { "osc", "ca7_secondary_sel", };
0030 static const char *pll1_sw_sels[] = { "pll1_sys", "step", };
0031 static const char *axi_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_540m", };
0032 static const char *axi_sels[] = {"periph", "axi_alt_sel", };
0033 static const char *periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
0034 static const char *periph2_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll4_audio_div", };
0035 static const char *periph_clk2_sels[] = { "pll3_usb_otg", "osc", "pll2_bypass_src", };
0036 static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "osc", };
0037 static const char *periph_sels[] = { "periph_pre", "periph_clk2", };
0038 static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", };
0039 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
0040 static const char *bch_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
0041 static const char *gpmi_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
0042 static const char *eim_slow_sels[] =  { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd0_720m", };
0043 static const char *spdif_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
0044 static const char *sai_sels[] = { "pll3_pfd2_508m", "pll5_video_div", "pll4_audio_div", };
0045 static const char *lcdif_pre_sels[] = { "pll2_bus", "pll3_pfd3_454m", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd1_594m", "pll3_pfd1_540m", };
0046 static const char *sim_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
0047 static const char *ldb_di0_sels[] = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_pfd3_594m", "pll2_pfd1_594m", "pll3_pfd3_454m", };
0048 static const char *ldb_di0_div_sels[] = { "ldb_di0_div_3_5", "ldb_di0_div_7", };
0049 static const char *ldb_di1_div_sels[] = { "ldb_di1_div_3_5", "ldb_di1_div_7", };
0050 static const char *qspi1_sels[] = { "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll2_bus", "pll3_pfd3_454m", "pll3_pfd2_508m", };
0051 static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", "dummy", "dummy", };
0052 static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", "dummy", };
0053 static const char *ecspi_sels[] = { "pll3_60m", "osc", };
0054 static const char *uart_sels[] = { "pll3_80m", "osc", };
0055 static const char *perclk_sels[] = { "ipg", "osc", };
0056 static const char *lcdif_sels[] = { "lcdif_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
0057 static const char *csi_sels[] = { "osc", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
0058 static const char *sim_sels[] = { "sim_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
0059 /* epdc_pre_sels, epdc_sels, esai_sels only exists on i.MX6ULL */
0060 static const char *epdc_pre_sels[] = { "pll2_bus", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd2_508m", };
0061 static const char *esai_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll5_video_div", "pll3_usb_otg", };
0062 static const char *epdc_sels[] = { "epdc_podf", "ipp_di0", "ipp_di1", "ldb_di0", "ldb_di1", };
0063 static const char *cko1_sels[] = { "dummy", "dummy", "dummy", "dummy", "dummy", "axi", "enfc", "dummy", "dummy",
0064                    "dummy", "lcdif_pix", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
0065 static const char *cko2_sels[] = { "dummy", "dummy", "dummy", "usdhc1", "dummy", "dummy", "ecspi_root", "dummy",
0066                    "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", "osc", "dummy",
0067                    "dummy", "usdhc2", "sai1", "sai2", "sai3", "dummy", "dummy", "can_root",
0068                    "dummy", "dummy", "dummy", "dummy", "uart_serial", "spdif", "dummy", "dummy", };
0069 static const char *cko_sels[] = { "cko1", "cko2", };
0070 
0071 static struct clk_hw **hws;
0072 static struct clk_hw_onecell_data *clk_hw_data;
0073 
0074 static const struct clk_div_table clk_enet_ref_table[] = {
0075     { .val = 0, .div = 20, },
0076     { .val = 1, .div = 10, },
0077     { .val = 2, .div = 5, },
0078     { .val = 3, .div = 4, },
0079     { }
0080 };
0081 
0082 static const struct clk_div_table post_div_table[] = {
0083     { .val = 2, .div = 1, },
0084     { .val = 1, .div = 2, },
0085     { .val = 0, .div = 4, },
0086     { }
0087 };
0088 
0089 static const struct clk_div_table video_div_table[] = {
0090     { .val = 0, .div = 1, },
0091     { .val = 1, .div = 2, },
0092     { .val = 2, .div = 1, },
0093     { .val = 3, .div = 4, },
0094     { }
0095 };
0096 
0097 static u32 share_count_asrc;
0098 static u32 share_count_audio;
0099 static u32 share_count_sai1;
0100 static u32 share_count_sai2;
0101 static u32 share_count_sai3;
0102 static u32 share_count_esai;
0103 
0104 static inline int clk_on_imx6ul(void)
0105 {
0106     return of_machine_is_compatible("fsl,imx6ul");
0107 }
0108 
0109 static inline int clk_on_imx6ull(void)
0110 {
0111     return of_machine_is_compatible("fsl,imx6ull");
0112 }
0113 
0114 static void __init imx6ul_clocks_init(struct device_node *ccm_node)
0115 {
0116     struct device_node *np;
0117     void __iomem *base;
0118 
0119     clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
0120                       IMX6UL_CLK_END), GFP_KERNEL);
0121     if (WARN_ON(!clk_hw_data))
0122         return;
0123 
0124     clk_hw_data->num = IMX6UL_CLK_END;
0125     hws = clk_hw_data->hws;
0126 
0127     hws[IMX6UL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
0128 
0129     hws[IMX6UL_CLK_CKIL] = imx_obtain_fixed_clk_hw(ccm_node, "ckil");
0130     hws[IMX6UL_CLK_OSC] = imx_obtain_fixed_clk_hw(ccm_node, "osc");
0131 
0132     /* ipp_di clock is external input */
0133     hws[IMX6UL_CLK_IPP_DI0] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di0");
0134     hws[IMX6UL_CLK_IPP_DI1] = imx_obtain_fixed_clk_hw(ccm_node, "ipp_di1");
0135 
0136     np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-anatop");
0137     base = of_iomap(np, 0);
0138     of_node_put(np);
0139     WARN_ON(!base);
0140 
0141     hws[IMX6UL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0142     hws[IMX6UL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0143     hws[IMX6UL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0144     hws[IMX6UL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0145     hws[IMX6UL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0146     hws[IMX6UL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0147     hws[IMX6UL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 1, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0148 
0149     hws[IMX6UL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,   "pll1", "osc", base + 0x00, 0x7f);
0150     hws[IMX6UL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
0151     hws[IMX6UL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,   "pll3", "osc", base + 0x10, 0x3);
0152     hws[IMX6UL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,    "pll4", "osc", base + 0x70, 0x7f);
0153     hws[IMX6UL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,    "pll5", "osc", base + 0xa0, 0x7f);
0154     hws[IMX6UL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,  "pll6", "osc", base + 0xe0, 0x3);
0155     hws[IMX6UL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,   "pll7", "osc", base + 0x20, 0x3);
0156 
0157     hws[IMX6UL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
0158     hws[IMX6UL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
0159     hws[IMX6UL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
0160     hws[IMX6UL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
0161     hws[IMX6UL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
0162     hws[IMX6UL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
0163     hws[IMX6UL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
0164 
0165     /* Do not bypass PLLs initially */
0166     clk_set_parent(hws[IMX6UL_PLL1_BYPASS]->clk, hws[IMX6UL_CLK_PLL1]->clk);
0167     clk_set_parent(hws[IMX6UL_PLL2_BYPASS]->clk, hws[IMX6UL_CLK_PLL2]->clk);
0168     clk_set_parent(hws[IMX6UL_PLL3_BYPASS]->clk, hws[IMX6UL_CLK_PLL3]->clk);
0169     clk_set_parent(hws[IMX6UL_PLL4_BYPASS]->clk, hws[IMX6UL_CLK_PLL4]->clk);
0170     clk_set_parent(hws[IMX6UL_PLL5_BYPASS]->clk, hws[IMX6UL_CLK_PLL5]->clk);
0171     clk_set_parent(hws[IMX6UL_PLL6_BYPASS]->clk, hws[IMX6UL_CLK_PLL6]->clk);
0172     clk_set_parent(hws[IMX6UL_PLL7_BYPASS]->clk, hws[IMX6UL_CLK_PLL7]->clk);
0173 
0174     hws[IMX6UL_CLK_PLL1_SYS]    = imx_clk_hw_fixed_factor("pll1_sys",   "pll1_bypass", 1, 1);
0175     hws[IMX6UL_CLK_PLL2_BUS]    = imx_clk_hw_gate("pll2_bus",   "pll2_bypass", base + 0x30, 13);
0176     hws[IMX6UL_CLK_PLL3_USB_OTG]    = imx_clk_hw_gate("pll3_usb_otg",   "pll3_bypass", base + 0x10, 13);
0177     hws[IMX6UL_CLK_PLL4_AUDIO]  = imx_clk_hw_gate("pll4_audio", "pll4_bypass", base + 0x70, 13);
0178     hws[IMX6UL_CLK_PLL5_VIDEO]  = imx_clk_hw_gate("pll5_video", "pll5_bypass", base + 0xa0, 13);
0179     hws[IMX6UL_CLK_PLL6_ENET]   = imx_clk_hw_gate("pll6_enet",  "pll6_bypass", base + 0xe0, 13);
0180     hws[IMX6UL_CLK_PLL7_USB_HOST]   = imx_clk_hw_gate("pll7_usb_host",  "pll7_bypass", base + 0x20, 13);
0181 
0182     /*
0183      * Bit 20 is the reserved and read-only bit, we do this only for:
0184      * - Do nothing for usbphy clk_enable/disable
0185      * - Keep refcount when do usbphy clk_enable/disable, in that case,
0186      * the clk framework many need to enable/disable usbphy's parent
0187      */
0188     hws[IMX6UL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg",  base + 0x10, 20);
0189     hws[IMX6UL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
0190 
0191     /*
0192      * usbphy*_gate needs to be on after system boots up, and software
0193      * never needs to control it anymore.
0194      */
0195     hws[IMX6UL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
0196     hws[IMX6UL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
0197 
0198     /*                  name           parent_name     reg      idx */
0199     hws[IMX6UL_CLK_PLL2_PFD0] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus",       base + 0x100, 0);
0200     hws[IMX6UL_CLK_PLL2_PFD1] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus",       base + 0x100, 1);
0201     hws[IMX6UL_CLK_PLL2_PFD2] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus",       base + 0x100, 2);
0202     hws[IMX6UL_CLK_PLL2_PFD3] = imx_clk_hw_pfd("pll2_pfd3_594m", "pll2_bus",       base + 0x100, 3);
0203     hws[IMX6UL_CLK_PLL3_PFD0] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
0204     hws[IMX6UL_CLK_PLL3_PFD1] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
0205     hws[IMX6UL_CLK_PLL3_PFD2] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,    2);
0206     hws[IMX6UL_CLK_PLL3_PFD3] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,    3);
0207 
0208     hws[IMX6UL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
0209             base + 0xe0, 0, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
0210     hws[IMX6UL_CLK_ENET2_REF] = clk_hw_register_divider_table(NULL, "enet2_ref", "pll6_enet", 0,
0211             base + 0xe0, 2, 2, 0, clk_enet_ref_table, &imx_ccm_lock);
0212 
0213     hws[IMX6UL_CLK_ENET2_REF_125M] = imx_clk_hw_gate("enet_ref_125m", "enet2_ref", base + 0xe0, 20);
0214     hws[IMX6UL_CLK_ENET_PTP_REF]    = imx_clk_hw_fixed_factor("enet_ptp_ref", "pll6_enet", 1, 20);
0215     hws[IMX6UL_CLK_ENET_PTP]    = imx_clk_hw_gate("enet_ptp", "enet_ptp_ref", base + 0xe0, 21);
0216 
0217     hws[IMX6UL_CLK_PLL4_POST_DIV]  = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio",
0218          CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
0219     hws[IMX6UL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div",
0220          CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, 0, &imx_ccm_lock);
0221     hws[IMX6UL_CLK_PLL5_POST_DIV]  = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video",
0222          CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
0223     hws[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div",
0224          CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
0225 
0226     /*                         name     parent_name  mult  div */
0227     hws[IMX6UL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1,   2);
0228     hws[IMX6UL_CLK_PLL3_80M]  = imx_clk_hw_fixed_factor("pll3_80m",  "pll3_usb_otg",   1,   6);
0229     hws[IMX6UL_CLK_PLL3_60M]  = imx_clk_hw_fixed_factor("pll3_60m",  "pll3_usb_otg",   1,   8);
0230     hws[IMX6UL_CLK_GPT_3M]     = imx_clk_hw_fixed_factor("gpt_3m",  "osc",       1, 8);
0231 
0232     np = ccm_node;
0233     base = of_iomap(np, 0);
0234     WARN_ON(!base);
0235 
0236     hws[IMX6UL_CA7_SECONDARY_SEL]     = imx_clk_hw_mux("ca7_secondary_sel", base + 0xc, 3, 1, ca7_secondary_sels, ARRAY_SIZE(ca7_secondary_sels));
0237     hws[IMX6UL_CLK_STEP]          = imx_clk_hw_mux("step", base + 0x0c, 8, 1, step_sels, ARRAY_SIZE(step_sels));
0238     hws[IMX6UL_CLK_PLL1_SW]   = imx_clk_hw_mux_flags("pll1_sw",   base + 0x0c, 2,  1, pll1_sw_sels, ARRAY_SIZE(pll1_sw_sels), 0);
0239     hws[IMX6UL_CLK_AXI_ALT_SEL]   = imx_clk_hw_mux("axi_alt_sel",       base + 0x14, 7,  1, axi_alt_sels, ARRAY_SIZE(axi_alt_sels));
0240     hws[IMX6UL_CLK_AXI_SEL]   = imx_clk_hw_mux_flags("axi_sel", base + 0x14, 6,  1, axi_sels, ARRAY_SIZE(axi_sels), 0);
0241     hws[IMX6UL_CLK_PERIPH_PRE]    = imx_clk_hw_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels, ARRAY_SIZE(periph_pre_sels));
0242     hws[IMX6UL_CLK_PERIPH2_PRE]   = imx_clk_hw_mux("periph2_pre",      base + 0x18, 21, 2, periph2_pre_sels, ARRAY_SIZE(periph2_pre_sels));
0243     hws[IMX6UL_CLK_PERIPH_CLK2_SEL]  = imx_clk_hw_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels, ARRAY_SIZE(periph_clk2_sels));
0244     hws[IMX6UL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
0245     hws[IMX6UL_CLK_EIM_SLOW_SEL]      = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels, ARRAY_SIZE(eim_slow_sels));
0246     hws[IMX6UL_CLK_GPMI_SEL]      = imx_clk_hw_mux("gpmi_sel",     base + 0x1c, 19, 1, gpmi_sels, ARRAY_SIZE(gpmi_sels));
0247     hws[IMX6UL_CLK_BCH_SEL]   = imx_clk_hw_mux("bch_sel",   base + 0x1c, 18, 1, bch_sels, ARRAY_SIZE(bch_sels));
0248     hws[IMX6UL_CLK_USDHC2_SEL]    = imx_clk_hw_mux("usdhc2_sel",   base + 0x1c, 17, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
0249     hws[IMX6UL_CLK_USDHC1_SEL]    = imx_clk_hw_mux("usdhc1_sel",   base + 0x1c, 16, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels));
0250     hws[IMX6UL_CLK_SAI3_SEL]      = imx_clk_hw_mux("sai3_sel",     base + 0x1c, 14, 2, sai_sels, ARRAY_SIZE(sai_sels));
0251     hws[IMX6UL_CLK_SAI2_SEL]         = imx_clk_hw_mux("sai2_sel",     base + 0x1c, 12, 2, sai_sels, ARRAY_SIZE(sai_sels));
0252     hws[IMX6UL_CLK_SAI1_SEL]      = imx_clk_hw_mux("sai1_sel",     base + 0x1c, 10, 2, sai_sels, ARRAY_SIZE(sai_sels));
0253     hws[IMX6UL_CLK_QSPI1_SEL]     = imx_clk_hw_mux("qspi1_sel",    base + 0x1c, 7,  3, qspi1_sels, ARRAY_SIZE(qspi1_sels));
0254     hws[IMX6UL_CLK_PERCLK_SEL]    = imx_clk_hw_mux("perclk_sel",    base + 0x1c, 6,  1, perclk_sels, ARRAY_SIZE(perclk_sels));
0255     hws[IMX6UL_CLK_CAN_SEL]   = imx_clk_hw_mux("can_sel",   base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
0256     if (clk_on_imx6ull())
0257         hws[IMX6ULL_CLK_ESAI_SEL]     = imx_clk_hw_mux("esai_sel",  base + 0x20, 19, 2, esai_sels, ARRAY_SIZE(esai_sels));
0258     hws[IMX6UL_CLK_UART_SEL]      = imx_clk_hw_mux("uart_sel",  base + 0x24, 6,  1, uart_sels, ARRAY_SIZE(uart_sels));
0259     hws[IMX6UL_CLK_ENFC_SEL]      = imx_clk_hw_mux("enfc_sel",  base + 0x2c, 15, 3, enfc_sels, ARRAY_SIZE(enfc_sels));
0260     hws[IMX6UL_CLK_LDB_DI0_SEL]   = imx_clk_hw_mux("ldb_di0_sel",   base + 0x2c, 9,  3, ldb_di0_sels, ARRAY_SIZE(ldb_di0_sels));
0261     hws[IMX6UL_CLK_SPDIF_SEL]     = imx_clk_hw_mux("spdif_sel", base + 0x30, 20, 2, spdif_sels, ARRAY_SIZE(spdif_sels));
0262     if (clk_on_imx6ul()) {
0263         hws[IMX6UL_CLK_SIM_PRE_SEL] = imx_clk_hw_mux("sim_pre_sel", base + 0x34, 15, 3, sim_pre_sels, ARRAY_SIZE(sim_pre_sels));
0264         hws[IMX6UL_CLK_SIM_SEL]     = imx_clk_hw_mux("sim_sel", base + 0x34, 9, 3, sim_sels, ARRAY_SIZE(sim_sels));
0265     } else if (clk_on_imx6ull()) {
0266         hws[IMX6ULL_CLK_EPDC_PRE_SEL]   = imx_clk_hw_mux("epdc_pre_sel",    base + 0x34, 15, 3, epdc_pre_sels, ARRAY_SIZE(epdc_pre_sels));
0267         hws[IMX6ULL_CLK_EPDC_SEL]   = imx_clk_hw_mux("epdc_sel",    base + 0x34, 9, 3, epdc_sels, ARRAY_SIZE(epdc_sels));
0268     }
0269     hws[IMX6UL_CLK_ECSPI_SEL]     = imx_clk_hw_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, ARRAY_SIZE(ecspi_sels));
0270     hws[IMX6UL_CLK_LCDIF_PRE_SEL]     = imx_clk_hw_mux_flags("lcdif_pre_sel", base + 0x38, 15, 3, lcdif_pre_sels, ARRAY_SIZE(lcdif_pre_sels), CLK_SET_RATE_PARENT);
0271     hws[IMX6UL_CLK_LCDIF_SEL]     = imx_clk_hw_mux("lcdif_sel", base + 0x38, 9, 3, lcdif_sels, ARRAY_SIZE(lcdif_sels));
0272     hws[IMX6UL_CLK_CSI_SEL]       = imx_clk_hw_mux("csi_sel", base + 0x3c, 9, 2, csi_sels, ARRAY_SIZE(csi_sels));
0273 
0274     hws[IMX6UL_CLK_LDB_DI0_DIV_SEL]  = imx_clk_hw_mux("ldb_di0", base + 0x20, 10, 1, ldb_di0_div_sels, ARRAY_SIZE(ldb_di0_div_sels));
0275     hws[IMX6UL_CLK_LDB_DI1_DIV_SEL]  = imx_clk_hw_mux("ldb_di1", base + 0x20, 11, 1, ldb_di1_div_sels, ARRAY_SIZE(ldb_di1_div_sels));
0276 
0277     hws[IMX6UL_CLK_CKO1_SEL]      = imx_clk_hw_mux("cko1_sel", base + 0x60, 0,  4, cko1_sels, ARRAY_SIZE(cko1_sels));
0278     hws[IMX6UL_CLK_CKO2_SEL]      = imx_clk_hw_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
0279     hws[IMX6UL_CLK_CKO]       = imx_clk_hw_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
0280 
0281     hws[IMX6UL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
0282     hws[IMX6UL_CLK_LDB_DI0_DIV_7]    = imx_clk_hw_fixed_factor("ldb_di0_div_7",   "ldb_di0_sel", 1, 7);
0283     hws[IMX6UL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "qspi1_sel", 2, 7);
0284     hws[IMX6UL_CLK_LDB_DI1_DIV_7]    = imx_clk_hw_fixed_factor("ldb_di1_div_7",   "qspi1_sel", 1, 7);
0285 
0286     hws[IMX6UL_CLK_PERIPH]  = imx_clk_hw_busy_mux("periph",  base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
0287     hws[IMX6UL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26, 1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
0288 
0289     hws[IMX6UL_CLK_PERIPH_CLK2] = imx_clk_hw_divider("periph_clk2",   "periph_clk2_sel",    base + 0x14, 27, 3);
0290     hws[IMX6UL_CLK_PERIPH2_CLK2]    = imx_clk_hw_divider("periph2_clk2",  "periph2_clk2_sel",   base + 0x14, 0,  3);
0291     hws[IMX6UL_CLK_IPG]     = imx_clk_hw_divider("ipg",    "ahb",       base + 0x14, 8,  2);
0292     hws[IMX6UL_CLK_LCDIF_PODF]  = imx_clk_hw_divider("lcdif_podf",     "lcdif_pred",    base + 0x18, 23, 3);
0293     hws[IMX6UL_CLK_QSPI1_PDOF]  = imx_clk_hw_divider("qspi1_podf",     "qspi1_sel",     base + 0x1c, 26, 3);
0294     hws[IMX6UL_CLK_EIM_SLOW_PODF]   = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3);
0295     hws[IMX6UL_CLK_PERCLK]      = imx_clk_hw_divider("perclk",     "perclk_sel",    base + 0x1c, 0,  6);
0296     hws[IMX6UL_CLK_CAN_PODF]    = imx_clk_hw_divider("can_podf",       "can_sel",       base + 0x20, 2,  6);
0297     hws[IMX6UL_CLK_GPMI_PODF]   = imx_clk_hw_divider("gpmi_podf",      "gpmi_sel",      base + 0x24, 22, 3);
0298     hws[IMX6UL_CLK_BCH_PODF]    = imx_clk_hw_divider("bch_podf",       "bch_sel",       base + 0x24, 19, 3);
0299     hws[IMX6UL_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf",   "usdhc2_sel", base + 0x24, 16, 3);
0300     hws[IMX6UL_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf",   "usdhc1_sel", base + 0x24, 11, 3);
0301     hws[IMX6UL_CLK_UART_PODF]   = imx_clk_hw_divider("uart_podf",      "uart_sel",      base + 0x24, 0,  6);
0302     hws[IMX6UL_CLK_SAI3_PRED]   = imx_clk_hw_divider("sai3_pred",      "sai3_sel",      base + 0x28, 22, 3);
0303     hws[IMX6UL_CLK_SAI3_PODF]   = imx_clk_hw_divider("sai3_podf",      "sai3_pred",     base + 0x28, 16, 6);
0304     hws[IMX6UL_CLK_SAI1_PRED]   = imx_clk_hw_divider("sai1_pred",      "sai1_sel",      base + 0x28, 6,  3);
0305     hws[IMX6UL_CLK_SAI1_PODF]   = imx_clk_hw_divider("sai1_podf",      "sai1_pred",     base + 0x28, 0,  6);
0306     if (clk_on_imx6ull()) {
0307         hws[IMX6ULL_CLK_ESAI_PRED]  = imx_clk_hw_divider("esai_pred",     "esai_sel",       base + 0x28, 9,  3);
0308         hws[IMX6ULL_CLK_ESAI_PODF]  = imx_clk_hw_divider("esai_podf",     "esai_pred",      base + 0x28, 25, 3);
0309     }
0310     hws[IMX6UL_CLK_ENFC_PRED]   = imx_clk_hw_divider("enfc_pred",      "enfc_sel",      base + 0x2c, 18, 3);
0311     hws[IMX6UL_CLK_ENFC_PODF]   = imx_clk_hw_divider("enfc_podf",      "enfc_pred",     base + 0x2c, 21, 6);
0312     hws[IMX6UL_CLK_SAI2_PRED]   = imx_clk_hw_divider("sai2_pred",      "sai2_sel",      base + 0x2c, 6,  3);
0313     hws[IMX6UL_CLK_SAI2_PODF]   = imx_clk_hw_divider("sai2_podf",      "sai2_pred",     base + 0x2c, 0,  6);
0314     hws[IMX6UL_CLK_SPDIF_PRED]  = imx_clk_hw_divider("spdif_pred",     "spdif_sel",     base + 0x30, 25, 3);
0315     hws[IMX6UL_CLK_SPDIF_PODF]  = imx_clk_hw_divider("spdif_podf",     "spdif_pred",    base + 0x30, 22, 3);
0316     if (clk_on_imx6ul())
0317         hws[IMX6UL_CLK_SIM_PODF]    = imx_clk_hw_divider("sim_podf",       "sim_pre_sel",   base + 0x34, 12, 3);
0318     else if (clk_on_imx6ull())
0319         hws[IMX6ULL_CLK_EPDC_PODF]  = imx_clk_hw_divider("epdc_podf",      "epdc_pre_sel",  base + 0x34, 12, 3);
0320     hws[IMX6UL_CLK_ECSPI_PODF]  = imx_clk_hw_divider("ecspi_podf",     "ecspi_sel",     base + 0x38, 19, 6);
0321     hws[IMX6UL_CLK_LCDIF_PRED]  = imx_clk_hw_divider("lcdif_pred",     "lcdif_pre_sel", base + 0x38, 12, 3);
0322     hws[IMX6UL_CLK_CSI_PODF]       = imx_clk_hw_divider("csi_podf",      "csi_sel",           base + 0x3c, 11, 3);
0323 
0324     hws[IMX6UL_CLK_CKO1_PODF]   = imx_clk_hw_divider("cko1_podf",     "cko1_sel",          base + 0x60, 4,  3);
0325     hws[IMX6UL_CLK_CKO2_PODF]   = imx_clk_hw_divider("cko2_podf",     "cko2_sel",          base + 0x60, 21, 3);
0326 
0327     hws[IMX6UL_CLK_ARM]     = imx_clk_hw_busy_divider("arm",        "pll1_sw",  base +  0x10, 0,  3,  base + 0x48, 16);
0328     hws[IMX6UL_CLK_MMDC_PODF]   = imx_clk_hw_busy_divider("mmdc_podf", "periph2",   base +  0x14, 3,  3,  base + 0x48, 2);
0329     hws[IMX6UL_CLK_AXI_PODF]    = imx_clk_hw_busy_divider("axi_podf",  "axi_sel",   base +  0x14, 16, 3,  base + 0x48, 0);
0330     hws[IMX6UL_CLK_AHB]     = imx_clk_hw_busy_divider("ahb",        "periph",   base +  0x14, 10, 3,  base + 0x48, 1);
0331 
0332     /* CCGR0 */
0333     hws[IMX6UL_CLK_AIPSTZ1] = imx_clk_hw_gate2_flags("aips_tz1", "ahb", base + 0x68, 0, CLK_IS_CRITICAL);
0334     hws[IMX6UL_CLK_AIPSTZ2] = imx_clk_hw_gate2_flags("aips_tz2", "ahb", base + 0x68, 2, CLK_IS_CRITICAL);
0335     hws[IMX6UL_CLK_APBHDMA] = imx_clk_hw_gate2("apbh_dma",  "bch_podf", base + 0x68,    4);
0336     hws[IMX6UL_CLK_ASRC_IPG]    = imx_clk_hw_gate2_shared("asrc_ipg",   "ahb",  base + 0x68,    6, &share_count_asrc);
0337     hws[IMX6UL_CLK_ASRC_MEM]    = imx_clk_hw_gate2_shared("asrc_mem",   "ahb",  base + 0x68,    6, &share_count_asrc);
0338     if (clk_on_imx6ul()) {
0339         hws[IMX6UL_CLK_CAAM_MEM]    = imx_clk_hw_gate2("caam_mem",  "ahb",      base + 0x68,    8);
0340         hws[IMX6UL_CLK_CAAM_ACLK]   = imx_clk_hw_gate2("caam_aclk", "ahb",      base + 0x68,    10);
0341         hws[IMX6UL_CLK_CAAM_IPG]    = imx_clk_hw_gate2("caam_ipg",  "ipg",      base + 0x68,    12);
0342     } else if (clk_on_imx6ull()) {
0343         hws[IMX6ULL_CLK_DCP_CLK]    = imx_clk_hw_gate2("dcp",       "ahb",      base + 0x68,    10);
0344         hws[IMX6UL_CLK_ENET]        = imx_clk_hw_gate2("enet",      "ipg",      base + 0x68,    12);
0345         hws[IMX6UL_CLK_ENET_AHB]    = imx_clk_hw_gate2("enet_ahb",  "ahb",      base + 0x68,    12);
0346     }
0347     hws[IMX6UL_CLK_CAN1_IPG]    = imx_clk_hw_gate2("can1_ipg",  "ipg",      base + 0x68,    14);
0348     hws[IMX6UL_CLK_CAN1_SERIAL] = imx_clk_hw_gate2("can1_serial",   "can_podf", base + 0x68,    16);
0349     hws[IMX6UL_CLK_CAN2_IPG]    = imx_clk_hw_gate2("can2_ipg",  "ipg",      base + 0x68,    18);
0350     hws[IMX6UL_CLK_CAN2_SERIAL] = imx_clk_hw_gate2("can2_serial",   "can_podf", base + 0x68,    20);
0351     hws[IMX6UL_CLK_GPT2_BUS]    = imx_clk_hw_gate2("gpt2_bus",  "perclk",   base + 0x68,    24);
0352     hws[IMX6UL_CLK_GPT2_SERIAL] = imx_clk_hw_gate2("gpt2_serial",   "perclk",   base + 0x68,    26);
0353     hws[IMX6UL_CLK_UART2_IPG]   = imx_clk_hw_gate2("uart2_ipg", "ipg",      base + 0x68,    28);
0354     hws[IMX6UL_CLK_UART2_SERIAL]    = imx_clk_hw_gate2("uart2_serial",  "uart_podf",    base + 0x68,    28);
0355     if (clk_on_imx6ull())
0356         hws[IMX6UL_CLK_AIPSTZ3] = imx_clk_hw_gate2("aips_tz3",  "ahb",       base + 0x80,   18);
0357     hws[IMX6UL_CLK_GPIO2]       = imx_clk_hw_gate2("gpio2", "ipg",      base + 0x68,    30);
0358 
0359     /* CCGR1 */
0360     hws[IMX6UL_CLK_ECSPI1]      = imx_clk_hw_gate2("ecspi1",    "ecspi_podf",   base + 0x6c,    0);
0361     hws[IMX6UL_CLK_ECSPI2]      = imx_clk_hw_gate2("ecspi2",    "ecspi_podf",   base + 0x6c,    2);
0362     hws[IMX6UL_CLK_ECSPI3]      = imx_clk_hw_gate2("ecspi3",    "ecspi_podf",   base + 0x6c,    4);
0363     hws[IMX6UL_CLK_ECSPI4]      = imx_clk_hw_gate2("ecspi4",    "ecspi_podf",   base + 0x6c,    6);
0364     hws[IMX6UL_CLK_ADC2]        = imx_clk_hw_gate2("adc2",      "ipg",      base + 0x6c,    8);
0365     hws[IMX6UL_CLK_UART3_IPG]   = imx_clk_hw_gate2("uart3_ipg", "ipg",      base + 0x6c,    10);
0366     hws[IMX6UL_CLK_UART3_SERIAL]    = imx_clk_hw_gate2("uart3_serial",  "uart_podf",    base + 0x6c,    10);
0367     hws[IMX6UL_CLK_EPIT1]       = imx_clk_hw_gate2("epit1", "perclk",   base + 0x6c,    12);
0368     hws[IMX6UL_CLK_EPIT2]       = imx_clk_hw_gate2("epit2", "perclk",   base + 0x6c,    14);
0369     hws[IMX6UL_CLK_ADC1]        = imx_clk_hw_gate2("adc1",      "ipg",      base + 0x6c,    16);
0370     hws[IMX6UL_CLK_GPT1_BUS]    = imx_clk_hw_gate2("gpt1_bus",  "perclk",   base + 0x6c,    20);
0371     hws[IMX6UL_CLK_GPT1_SERIAL] = imx_clk_hw_gate2("gpt1_serial",   "perclk",   base + 0x6c,    22);
0372     hws[IMX6UL_CLK_UART4_IPG]   = imx_clk_hw_gate2("uart4_ipg", "ipg",      base + 0x6c,    24);
0373     hws[IMX6UL_CLK_UART4_SERIAL]    = imx_clk_hw_gate2("uart4_serial",  "uart_podf",    base + 0x6c,    24);
0374     hws[IMX6UL_CLK_GPIO1]       = imx_clk_hw_gate2("gpio1", "ipg",      base + 0x6c,    26);
0375     hws[IMX6UL_CLK_GPIO5]       = imx_clk_hw_gate2("gpio5", "ipg",      base + 0x6c,    30);
0376 
0377     /* CCGR2 */
0378     if (clk_on_imx6ull()) {
0379         hws[IMX6ULL_CLK_ESAI_EXTAL] = imx_clk_hw_gate2_shared("esai_extal", "esai_podf",    base + 0x70,    0, &share_count_esai);
0380         hws[IMX6ULL_CLK_ESAI_IPG]   = imx_clk_hw_gate2_shared("esai_ipg",   "ahb",      base + 0x70,    0, &share_count_esai);
0381         hws[IMX6ULL_CLK_ESAI_MEM]   = imx_clk_hw_gate2_shared("esai_mem",   "ahb",      base + 0x70,    0, &share_count_esai);
0382     }
0383     hws[IMX6UL_CLK_I2C1]        = imx_clk_hw_gate2("i2c1",      "perclk",   base + 0x70,    6);
0384     hws[IMX6UL_CLK_I2C2]        = imx_clk_hw_gate2("i2c2",      "perclk",   base + 0x70,    8);
0385     hws[IMX6UL_CLK_I2C3]        = imx_clk_hw_gate2("i2c3",      "perclk",   base + 0x70,    10);
0386     hws[IMX6UL_CLK_OCOTP]       = imx_clk_hw_gate2("ocotp", "ipg",      base + 0x70,    12);
0387     hws[IMX6UL_CLK_IOMUXC]      = imx_clk_hw_gate2("iomuxc",    "lcdif_podf",   base + 0x70,    14);
0388     hws[IMX6UL_CLK_GPIO3]       = imx_clk_hw_gate2("gpio3", "ipg",      base + 0x70,    26);
0389     hws[IMX6UL_CLK_LCDIF_APB]   = imx_clk_hw_gate2("lcdif_apb", "axi",      base + 0x70,    28);
0390     hws[IMX6UL_CLK_PXP]     = imx_clk_hw_gate2("pxp",       "axi",      base + 0x70,    30);
0391 
0392     /* CCGR3 */
0393     /*
0394      * Although the imx6ull reference manual lists CCGR2 as the csi clk
0395      * gate register, tests have shown that it is actually the CCGR3
0396      * register bit 0/1, same as for the imx6ul.
0397      */
0398     hws[IMX6UL_CLK_CSI]     = imx_clk_hw_gate2("csi",   "csi_podf", base + 0x74,    0);
0399     hws[IMX6UL_CLK_UART5_IPG]   = imx_clk_hw_gate2("uart5_ipg", "ipg",      base + 0x74,    2);
0400     hws[IMX6UL_CLK_UART5_SERIAL]    = imx_clk_hw_gate2("uart5_serial",  "uart_podf",    base + 0x74,    2);
0401     if (clk_on_imx6ul()) {
0402         hws[IMX6UL_CLK_ENET]        = imx_clk_hw_gate2("enet",      "ipg",      base + 0x74,    4);
0403         hws[IMX6UL_CLK_ENET_AHB]    = imx_clk_hw_gate2("enet_ahb",  "ahb",      base + 0x74,    4);
0404     } else if (clk_on_imx6ull()) {
0405         hws[IMX6ULL_CLK_EPDC_ACLK]  = imx_clk_hw_gate2("epdc_aclk", "axi",      base + 0x74,    4);
0406         hws[IMX6ULL_CLK_EPDC_PIX]   = imx_clk_hw_gate2("epdc_pix",  "epdc_podf",    base + 0x74,    4);
0407     }
0408     hws[IMX6UL_CLK_UART6_IPG]   = imx_clk_hw_gate2("uart6_ipg", "ipg",      base + 0x74,    6);
0409     hws[IMX6UL_CLK_UART6_SERIAL]    = imx_clk_hw_gate2("uart6_serial",  "uart_podf",    base + 0x74,    6);
0410     hws[IMX6UL_CLK_LCDIF_PIX]   = imx_clk_hw_gate2("lcdif_pix", "lcdif_podf",   base + 0x74,    10);
0411     hws[IMX6UL_CLK_GPIO4]       = imx_clk_hw_gate2("gpio4", "ipg",      base + 0x74,    12);
0412     hws[IMX6UL_CLK_QSPI]        = imx_clk_hw_gate2("qspi1", "qspi1_podf",   base + 0x74,    14);
0413     hws[IMX6UL_CLK_WDOG1]       = imx_clk_hw_gate2("wdog1", "ipg",      base + 0x74,    16);
0414     hws[IMX6UL_CLK_MMDC_P0_FAST]    = imx_clk_hw_gate_flags("mmdc_p0_fast", "mmdc_podf", base + 0x74,   20, CLK_IS_CRITICAL);
0415     hws[IMX6UL_CLK_MMDC_P0_IPG] = imx_clk_hw_gate2_flags("mmdc_p0_ipg", "ipg",      base + 0x74,    24, CLK_IS_CRITICAL);
0416     hws[IMX6UL_CLK_MMDC_P1_IPG] = imx_clk_hw_gate2_flags("mmdc_p1_ipg", "ipg",      base + 0x74,    26, CLK_IS_CRITICAL);
0417     hws[IMX6UL_CLK_AXI]     = imx_clk_hw_gate_flags("axi",  "axi_podf", base + 0x74,    28, CLK_IS_CRITICAL);
0418 
0419     /* CCGR4 */
0420     hws[IMX6UL_CLK_PER_BCH] = imx_clk_hw_gate2("per_bch",   "bch_podf", base + 0x78,    12);
0421     hws[IMX6UL_CLK_PWM1]        = imx_clk_hw_gate2("pwm1",      "perclk",   base + 0x78,    16);
0422     hws[IMX6UL_CLK_PWM2]        = imx_clk_hw_gate2("pwm2",      "perclk",   base + 0x78,    18);
0423     hws[IMX6UL_CLK_PWM3]        = imx_clk_hw_gate2("pwm3",      "perclk",   base + 0x78,    20);
0424     hws[IMX6UL_CLK_PWM4]        = imx_clk_hw_gate2("pwm4",      "perclk",   base + 0x78,    22);
0425     hws[IMX6UL_CLK_GPMI_BCH_APB]    = imx_clk_hw_gate2("gpmi_bch_apb",  "bch_podf", base + 0x78,    24);
0426     hws[IMX6UL_CLK_GPMI_BCH]    = imx_clk_hw_gate2("gpmi_bch",  "gpmi_podf",    base + 0x78,    26);
0427     hws[IMX6UL_CLK_GPMI_IO] = imx_clk_hw_gate2("gpmi_io",   "enfc_podf",    base + 0x78,    28);
0428     hws[IMX6UL_CLK_GPMI_APB]    = imx_clk_hw_gate2("gpmi_apb",  "bch_podf", base + 0x78,    30);
0429 
0430     /* CCGR5 */
0431     hws[IMX6UL_CLK_ROM]     = imx_clk_hw_gate2_flags("rom", "ahb",      base + 0x7c,    0,  CLK_IS_CRITICAL);
0432     hws[IMX6UL_CLK_SDMA]        = imx_clk_hw_gate2("sdma",      "ahb",      base + 0x7c,    6);
0433     hws[IMX6UL_CLK_KPP]     = imx_clk_hw_gate2("kpp",       "ipg",      base + 0x7c,    8);
0434     hws[IMX6UL_CLK_WDOG2]       = imx_clk_hw_gate2("wdog2", "ipg",      base + 0x7c,    10);
0435     hws[IMX6UL_CLK_SPBA]        = imx_clk_hw_gate2("spba",      "ipg",      base + 0x7c,    12);
0436     hws[IMX6UL_CLK_SPDIF]       = imx_clk_hw_gate2_shared("spdif",      "spdif_podf",   base + 0x7c,    14, &share_count_audio);
0437     hws[IMX6UL_CLK_SPDIF_GCLK]  = imx_clk_hw_gate2_shared("spdif_gclk", "ipg",      base + 0x7c,    14, &share_count_audio);
0438     hws[IMX6UL_CLK_SAI3]        = imx_clk_hw_gate2_shared("sai3",       "sai3_podf",    base + 0x7c,    22, &share_count_sai3);
0439     hws[IMX6UL_CLK_SAI3_IPG]    = imx_clk_hw_gate2_shared("sai3_ipg",   "ipg",      base + 0x7c,    22, &share_count_sai3);
0440     hws[IMX6UL_CLK_UART1_IPG]   = imx_clk_hw_gate2("uart1_ipg", "ipg",      base + 0x7c,    24);
0441     hws[IMX6UL_CLK_UART1_SERIAL]    = imx_clk_hw_gate2("uart1_serial",  "uart_podf",    base + 0x7c,    24);
0442     hws[IMX6UL_CLK_UART7_IPG]   = imx_clk_hw_gate2("uart7_ipg", "ipg",      base + 0x7c,    26);
0443     hws[IMX6UL_CLK_UART7_SERIAL]    = imx_clk_hw_gate2("uart7_serial",  "uart_podf",    base + 0x7c,    26);
0444     hws[IMX6UL_CLK_SAI1]        = imx_clk_hw_gate2_shared("sai1",       "sai1_podf",    base + 0x7c,    28, &share_count_sai1);
0445     hws[IMX6UL_CLK_SAI1_IPG]    = imx_clk_hw_gate2_shared("sai1_ipg",   "ipg",      base + 0x7c,    28, &share_count_sai1);
0446     hws[IMX6UL_CLK_SAI2]        = imx_clk_hw_gate2_shared("sai2",       "sai2_podf",    base + 0x7c,    30, &share_count_sai2);
0447     hws[IMX6UL_CLK_SAI2_IPG]    = imx_clk_hw_gate2_shared("sai2_ipg",   "ipg",      base + 0x7c,    30, &share_count_sai2);
0448 
0449     /* CCGR6 */
0450     hws[IMX6UL_CLK_USBOH3]      = imx_clk_hw_gate2("usboh3",    "ipg",       base + 0x80,   0);
0451     hws[IMX6UL_CLK_USDHC1]      = imx_clk_hw_gate2("usdhc1",    "usdhc1_podf",   base + 0x80,   2);
0452     hws[IMX6UL_CLK_USDHC2]      = imx_clk_hw_gate2("usdhc2",    "usdhc2_podf",   base + 0x80,   4);
0453     if (clk_on_imx6ul()) {
0454         hws[IMX6UL_CLK_SIM1]        = imx_clk_hw_gate2("sim1",      "sim_sel",   base + 0x80,   6);
0455         hws[IMX6UL_CLK_SIM2]        = imx_clk_hw_gate2("sim2",      "sim_sel",   base + 0x80,   8);
0456     }
0457     hws[IMX6UL_CLK_EIM]     = imx_clk_hw_gate2("eim",       "eim_slow_podf", base + 0x80,   10);
0458     hws[IMX6UL_CLK_PWM8]        = imx_clk_hw_gate2("pwm8",      "perclk",    base + 0x80,   16);
0459     hws[IMX6UL_CLK_UART8_IPG]   = imx_clk_hw_gate2("uart8_ipg", "ipg",       base + 0x80,   14);
0460     hws[IMX6UL_CLK_UART8_SERIAL]    = imx_clk_hw_gate2("uart8_serial", "uart_podf",  base + 0x80,   14);
0461     hws[IMX6UL_CLK_WDOG3]       = imx_clk_hw_gate2("wdog3", "ipg",       base + 0x80,   20);
0462     hws[IMX6UL_CLK_I2C4]        = imx_clk_hw_gate2("i2c4",      "perclk",    base + 0x80,   24);
0463     hws[IMX6UL_CLK_PWM5]        = imx_clk_hw_gate2("pwm5",      "perclk",    base + 0x80,   26);
0464     hws[IMX6UL_CLK_PWM6]        = imx_clk_hw_gate2("pwm6",      "perclk",    base + 0x80,   28);
0465     hws[IMX6UL_CLK_PWM7]        = imx_clk_hw_gate2("pwm7",      "perclk",    base + 0x80,   30);
0466 
0467     /* CCOSR */
0468     hws[IMX6UL_CLK_CKO1]        = imx_clk_hw_gate("cko1",       "cko1_podf",     base + 0x60,   7);
0469     hws[IMX6UL_CLK_CKO2]        = imx_clk_hw_gate("cko2",       "cko2_podf",     base + 0x60,   24);
0470 
0471     /* mask handshake of mmdc */
0472     imx_mmdc_mask_handshake(base, 0);
0473 
0474     imx_check_clk_hws(hws, IMX6UL_CLK_END);
0475 
0476     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
0477 
0478     /*
0479      * Lower the AHB clock rate before changing the parent clock source,
0480      * as AHB clock rate can NOT be higher than 133MHz, but its parent
0481      * will be switched from 396MHz PFD to 528MHz PLL in order to increase
0482      * AXI clock rate, so we need to lower AHB rate first to make sure at
0483      * any time, AHB rate is <= 133MHz.
0484      */
0485     clk_set_rate(hws[IMX6UL_CLK_AHB]->clk, 99000000);
0486 
0487     /* Change periph_pre clock to pll2_bus to adjust AXI rate to 264MHz */
0488     clk_set_parent(hws[IMX6UL_CLK_PERIPH_CLK2_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk);
0489     clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_CLK2]->clk);
0490     clk_set_parent(hws[IMX6UL_CLK_PERIPH_PRE]->clk, hws[IMX6UL_CLK_PLL2_BUS]->clk);
0491     clk_set_parent(hws[IMX6UL_CLK_PERIPH]->clk, hws[IMX6UL_CLK_PERIPH_PRE]->clk);
0492 
0493     /* Make sure AHB rate is 132MHz  */
0494     clk_set_rate(hws[IMX6UL_CLK_AHB]->clk, 132000000);
0495 
0496     /* set perclk to from OSC */
0497     clk_set_parent(hws[IMX6UL_CLK_PERCLK_SEL]->clk, hws[IMX6UL_CLK_OSC]->clk);
0498 
0499     clk_set_rate(hws[IMX6UL_CLK_ENET_REF]->clk, 50000000);
0500     clk_set_rate(hws[IMX6UL_CLK_ENET2_REF]->clk, 50000000);
0501     clk_set_rate(hws[IMX6UL_CLK_CSI]->clk, 24000000);
0502 
0503     if (clk_on_imx6ull())
0504         clk_prepare_enable(hws[IMX6UL_CLK_AIPSTZ3]->clk);
0505 
0506     if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
0507         clk_prepare_enable(hws[IMX6UL_CLK_USBPHY1_GATE]->clk);
0508         clk_prepare_enable(hws[IMX6UL_CLK_USBPHY2_GATE]->clk);
0509     }
0510 
0511     clk_set_parent(hws[IMX6UL_CLK_CAN_SEL]->clk, hws[IMX6UL_CLK_PLL3_80M]->clk);
0512     if (clk_on_imx6ul())
0513         clk_set_parent(hws[IMX6UL_CLK_SIM_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_USB_OTG]->clk);
0514     else if (clk_on_imx6ull())
0515         clk_set_parent(hws[IMX6ULL_CLK_EPDC_PRE_SEL]->clk, hws[IMX6UL_CLK_PLL3_PFD2]->clk);
0516 
0517     clk_set_parent(hws[IMX6UL_CLK_ENFC_SEL]->clk, hws[IMX6UL_CLK_PLL2_PFD2]->clk);
0518 }
0519 
0520 CLK_OF_DECLARE(imx6ul, "fsl,imx6ul-ccm", imx6ul_clocks_init);
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