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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2011-2013 Freescale Semiconductor, Inc.
0004  * Copyright 2011 Linaro Ltd.
0005  */
0006 
0007 #include <linux/init.h>
0008 #include <linux/types.h>
0009 #include <linux/bits.h>
0010 #include <linux/clk.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/clk-provider.h>
0013 #include <linux/err.h>
0014 #include <linux/io.h>
0015 #include <linux/of.h>
0016 #include <linux/of_address.h>
0017 #include <linux/of_irq.h>
0018 #include <soc/imx/revision.h>
0019 #include <dt-bindings/clock/imx6qdl-clock.h>
0020 
0021 #include "clk.h"
0022 
0023 static const char *step_sels[]  = { "osc", "pll2_pfd2_396m", };
0024 static const char *pll1_sw_sels[]   = { "pll1_sys", "step", };
0025 static const char *periph_pre_sels[]    = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", };
0026 static const char *periph_clk2_sels[]   = { "pll3_usb_otg", "osc", "osc", "dummy", };
0027 static const char *periph2_clk2_sels[]  = { "pll3_usb_otg", "pll2_bus", };
0028 static const char *periph_sels[]    = { "periph_pre", "periph_clk2", };
0029 static const char *periph2_sels[]   = { "periph2_pre", "periph2_clk2", };
0030 static const char *axi_sels[]       = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", };
0031 static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", };
0032 static const char *gpu_axi_sels[]   = { "axi", "ahb", };
0033 static const char *pre_axi_sels[]   = { "axi", "ahb", };
0034 static const char *gpu2d_core_sels[]    = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", };
0035 static const char *gpu2d_core_sels_2[]  = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m",};
0036 static const char *gpu3d_core_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", };
0037 static const char *gpu3d_shader_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll3_pfd0_720m", };
0038 static const char *ipu_sels[]       = { "mmdc_ch0_axi", "pll2_pfd2_396m", "pll3_120m", "pll3_pfd1_540m", };
0039 static const char *ldb_di_sels[]    = { "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "mmdc_ch1_axi", "pll3_usb_otg", };
0040 static const char *ipu_di_pre_sels[]    = { "mmdc_ch0_axi", "pll3_usb_otg", "pll5_video_div", "pll2_pfd0_352m", "pll2_pfd2_396m", "pll3_pfd1_540m", };
0041 static const char *ipu1_di0_sels[]  = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
0042 static const char *ipu1_di1_sels[]  = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
0043 static const char *ipu2_di0_sels[]  = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
0044 static const char *ipu2_di1_sels[]  = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", };
0045 static const char *ipu1_di0_sels_2[]    = { "ipu1_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
0046 static const char *ipu1_di1_sels_2[]    = { "ipu1_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
0047 static const char *ipu2_di0_sels_2[]    = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
0048 static const char *ipu2_di1_sels_2[]    = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0_podf", "ldb_di1_podf", };
0049 static const char *hsi_tx_sels[]    = { "pll3_120m", "pll2_pfd2_396m", };
0050 static const char *pcie_axi_sels[]  = { "axi", "ahb", };
0051 static const char *ssi_sels[]       = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", };
0052 static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
0053 static const char *enfc_sels[]  = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", };
0054 static const char *enfc_sels_2[] = {"pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", "pll3_pfd3_454m", "dummy", };
0055 static const char *eim_sels[]       = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", };
0056 static const char *eim_slow_sels[]      = { "axi", "pll3_usb_otg", "pll2_pfd2_396m", "pll2_pfd0_352m", };
0057 static const char *vdo_axi_sels[]   = { "axi", "ahb", };
0058 static const char *vpu_axi_sels[]   = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", };
0059 static const char *uart_sels[] = { "pll3_80m", "osc", };
0060 static const char *ipg_per_sels[] = { "ipg", "osc", };
0061 static const char *ecspi_sels[] = { "pll3_60m", "osc", };
0062 static const char *can_sels[] = { "pll3_60m", "osc", "pll3_80m", };
0063 static const char *cko1_sels[]  = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div",
0064                     "video_27m", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0",
0065                     "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", };
0066 static const char *cko2_sels[] = {
0067     "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1",
0068     "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi",
0069     "usdhc3", "dummy", "arm", "ipu1",
0070     "ipu2", "vdo_axi", "osc", "gpu2d_core",
0071     "gpu3d_core", "usdhc2", "ssi1", "ssi2",
0072     "ssi3", "gpu3d_shader", "vpu_axi", "can_root",
0073     "ldb_di0", "ldb_di1", "esai_extal", "eim_slow",
0074     "uart_serial", "spdif", "asrc", "hsi_tx",
0075 };
0076 static const char *cko_sels[] = { "cko1", "cko2", };
0077 static const char *lvds_sels[] = {
0078     "dummy", "dummy", "dummy", "dummy", "dummy", "dummy",
0079     "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref",
0080     "pcie_ref_125m", "sata_ref_100m",  "usbphy1", "usbphy2",
0081     "dummy", "dummy", "dummy", "dummy", "osc",
0082 };
0083 static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };
0084 static const char *pll1_bypass_sels[] = { "pll1", "pll1_bypass_src", };
0085 static const char *pll2_bypass_sels[] = { "pll2", "pll2_bypass_src", };
0086 static const char *pll3_bypass_sels[] = { "pll3", "pll3_bypass_src", };
0087 static const char *pll4_bypass_sels[] = { "pll4", "pll4_bypass_src", };
0088 static const char *pll5_bypass_sels[] = { "pll5", "pll5_bypass_src", };
0089 static const char *pll6_bypass_sels[] = { "pll6", "pll6_bypass_src", };
0090 static const char *pll7_bypass_sels[] = { "pll7", "pll7_bypass_src", };
0091 
0092 static struct clk_hw **hws;
0093 static struct clk_hw_onecell_data *clk_hw_data;
0094 
0095 static struct clk_div_table clk_enet_ref_table[] = {
0096     { .val = 0, .div = 20, },
0097     { .val = 1, .div = 10, },
0098     { .val = 2, .div = 5, },
0099     { .val = 3, .div = 4, },
0100     { /* sentinel */ }
0101 };
0102 
0103 static struct clk_div_table post_div_table[] = {
0104     { .val = 2, .div = 1, },
0105     { .val = 1, .div = 2, },
0106     { .val = 0, .div = 4, },
0107     { /* sentinel */ }
0108 };
0109 
0110 static struct clk_div_table video_div_table[] = {
0111     { .val = 0, .div = 1, },
0112     { .val = 1, .div = 2, },
0113     { .val = 2, .div = 1, },
0114     { .val = 3, .div = 4, },
0115     { /* sentinel */ }
0116 };
0117 
0118 static unsigned int share_count_esai;
0119 static unsigned int share_count_asrc;
0120 static unsigned int share_count_ssi1;
0121 static unsigned int share_count_ssi2;
0122 static unsigned int share_count_ssi3;
0123 static unsigned int share_count_mipi_core_cfg;
0124 static unsigned int share_count_spdif;
0125 static unsigned int share_count_prg0;
0126 static unsigned int share_count_prg1;
0127 
0128 static inline int clk_on_imx6q(void)
0129 {
0130     return of_machine_is_compatible("fsl,imx6q");
0131 }
0132 
0133 static inline int clk_on_imx6qp(void)
0134 {
0135     return of_machine_is_compatible("fsl,imx6qp");
0136 }
0137 
0138 static inline int clk_on_imx6dl(void)
0139 {
0140     return of_machine_is_compatible("fsl,imx6dl");
0141 }
0142 
0143 static int ldb_di_sel_by_clock_id(int clock_id)
0144 {
0145     switch (clock_id) {
0146     case IMX6QDL_CLK_PLL5_VIDEO_DIV:
0147         if (clk_on_imx6q() &&
0148             imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
0149             return -ENOENT;
0150         return 0;
0151     case IMX6QDL_CLK_PLL2_PFD0_352M:
0152         return 1;
0153     case IMX6QDL_CLK_PLL2_PFD2_396M:
0154         return 2;
0155     case IMX6QDL_CLK_MMDC_CH1_AXI:
0156         return 3;
0157     case IMX6QDL_CLK_PLL3_USB_OTG:
0158         return 4;
0159     default:
0160         return -ENOENT;
0161     }
0162 }
0163 
0164 static void of_assigned_ldb_sels(struct device_node *node,
0165                  unsigned int *ldb_di0_sel,
0166                  unsigned int *ldb_di1_sel)
0167 {
0168     struct of_phandle_args clkspec;
0169     int index, rc, num_parents;
0170     int parent, child, sel;
0171 
0172     num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
0173                          "#clock-cells");
0174     for (index = 0; index < num_parents; index++) {
0175         rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
0176                     "#clock-cells", index, &clkspec);
0177         if (rc < 0) {
0178             /* skip empty (null) phandles */
0179             if (rc == -ENOENT)
0180                 continue;
0181             else
0182                 return;
0183         }
0184         if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
0185             pr_err("ccm: parent clock %d not in ccm\n", index);
0186             return;
0187         }
0188         parent = clkspec.args[0];
0189 
0190         rc = of_parse_phandle_with_args(node, "assigned-clocks",
0191                 "#clock-cells", index, &clkspec);
0192         if (rc < 0)
0193             return;
0194         if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
0195             pr_err("ccm: child clock %d not in ccm\n", index);
0196             return;
0197         }
0198         child = clkspec.args[0];
0199 
0200         if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
0201             child != IMX6QDL_CLK_LDB_DI1_SEL)
0202             continue;
0203 
0204         sel = ldb_di_sel_by_clock_id(parent);
0205         if (sel < 0) {
0206             pr_err("ccm: invalid ldb_di%d parent clock: %d\n",
0207                    child == IMX6QDL_CLK_LDB_DI1_SEL, parent);
0208             continue;
0209         }
0210 
0211         if (child == IMX6QDL_CLK_LDB_DI0_SEL)
0212             *ldb_di0_sel = sel;
0213         if (child == IMX6QDL_CLK_LDB_DI1_SEL)
0214             *ldb_di1_sel = sel;
0215     }
0216 }
0217 
0218 static bool pll6_bypassed(struct device_node *node)
0219 {
0220     int index, ret, num_clocks;
0221     struct of_phandle_args clkspec;
0222 
0223     num_clocks = of_count_phandle_with_args(node, "assigned-clocks",
0224                         "#clock-cells");
0225     if (num_clocks < 0)
0226         return false;
0227 
0228     for (index = 0; index < num_clocks; index++) {
0229         ret = of_parse_phandle_with_args(node, "assigned-clocks",
0230                          "#clock-cells", index,
0231                          &clkspec);
0232         if (ret < 0)
0233             return false;
0234 
0235         if (clkspec.np == node &&
0236             clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
0237             break;
0238     }
0239 
0240     /* PLL6 bypass is not part of the assigned clock list */
0241     if (index == num_clocks)
0242         return false;
0243 
0244     ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
0245                      "#clock-cells", index, &clkspec);
0246 
0247     if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
0248         return true;
0249 
0250     return false;
0251 }
0252 
0253 #define CCM_CCSR        0x0c
0254 #define CCM_CS2CDR      0x2c
0255 
0256 #define CCSR_PLL3_SW_CLK_SEL        BIT(0)
0257 
0258 #define CS2CDR_LDB_DI0_CLK_SEL_SHIFT    9
0259 #define CS2CDR_LDB_DI1_CLK_SEL_SHIFT    12
0260 
0261 /*
0262  * The only way to disable the MMDC_CH1 clock is to move it to pll3_sw_clk
0263  * via periph2_clk2_sel and then to disable pll3_sw_clk by selecting the
0264  * bypass clock source, since there is no CG bit for mmdc_ch1.
0265  */
0266 static void mmdc_ch1_disable(void __iomem *ccm_base)
0267 {
0268     unsigned int reg;
0269 
0270     clk_set_parent(hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL]->clk,
0271                hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
0272 
0273     /* Disable pll3_sw_clk by selecting the bypass clock source */
0274     reg = readl_relaxed(ccm_base + CCM_CCSR);
0275     reg |= CCSR_PLL3_SW_CLK_SEL;
0276     writel_relaxed(reg, ccm_base + CCM_CCSR);
0277 }
0278 
0279 static void mmdc_ch1_reenable(void __iomem *ccm_base)
0280 {
0281     unsigned int reg;
0282 
0283     /* Enable pll3_sw_clk by disabling the bypass */
0284     reg = readl_relaxed(ccm_base + CCM_CCSR);
0285     reg &= ~CCSR_PLL3_SW_CLK_SEL;
0286     writel_relaxed(reg, ccm_base + CCM_CCSR);
0287 }
0288 
0289 /*
0290  * We have to follow a strict procedure when changing the LDB clock source,
0291  * otherwise we risk introducing a glitch that can lock up the LDB divider.
0292  * Things to keep in mind:
0293  *
0294  * 1. The current and new parent clock inputs to the mux must be disabled.
0295  * 2. The default clock input for ldb_di0/1_clk_sel is mmdc_ch1_axi, which
0296  *    has no CG bit.
0297  * 3. pll2_pfd2_396m can not be gated if it is used as memory clock.
0298  * 4. In the RTL implementation of the LDB_DI_CLK_SEL muxes the top four
0299  *    options are in one mux and the PLL3 option along with three unused
0300  *    inputs is in a second mux. There is a third mux with two inputs used
0301  *    to decide between the first and second 4-port mux:
0302  *
0303  *    pll5_video_div 0 --|\
0304  *    pll2_pfd0_352m 1 --| |_
0305  *    pll2_pfd2_396m 2 --| | `-|\
0306  *    mmdc_ch1_axi   3 --|/    | |
0307  *                             | |--
0308  *    pll3_usb_otg   4 --|\    | |
0309  *                   5 --| |_,-|/
0310  *                   6 --| |
0311  *                   7 --|/
0312  *
0313  * The ldb_di0/1_clk_sel[1:0] bits control both 4-port muxes at the same time.
0314  * The ldb_di0/1_clk_sel[2] bit controls the 2-port mux. The code below
0315  * switches the parent to the bottom mux first and then manipulates the top
0316  * mux to ensure that no glitch will enter the divider.
0317  */
0318 static void init_ldb_clks(struct device_node *np, void __iomem *ccm_base)
0319 {
0320     unsigned int reg;
0321     unsigned int sel[2][4];
0322     int i;
0323 
0324     reg = readl_relaxed(ccm_base + CCM_CS2CDR);
0325     sel[0][0] = (reg >> CS2CDR_LDB_DI0_CLK_SEL_SHIFT) & 7;
0326     sel[1][0] = (reg >> CS2CDR_LDB_DI1_CLK_SEL_SHIFT) & 7;
0327 
0328     sel[0][3] = sel[0][2] = sel[0][1] = sel[0][0];
0329     sel[1][3] = sel[1][2] = sel[1][1] = sel[1][0];
0330 
0331     of_assigned_ldb_sels(np, &sel[0][3], &sel[1][3]);
0332 
0333     for (i = 0; i < 2; i++) {
0334         /* Print a notice if a glitch might have been introduced already */
0335         if (sel[i][0] != 3) {
0336             pr_notice("ccm: possible glitch: ldb_di%d_sel already changed from reset value: %d\n",
0337                   i, sel[i][0]);
0338         }
0339 
0340         if (sel[i][0] == sel[i][3])
0341             continue;
0342 
0343         /* Only switch to or from pll2_pfd2_396m if it is disabled */
0344         if ((sel[i][0] == 2 || sel[i][3] == 2) &&
0345             (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
0346              hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)) {
0347             pr_err("ccm: ldb_di%d_sel: couldn't disable pll2_pfd2_396m\n",
0348                    i);
0349             sel[i][3] = sel[i][2] = sel[i][1] = sel[i][0];
0350             continue;
0351         }
0352 
0353         /* First switch to the bottom mux */
0354         sel[i][1] = sel[i][0] | 4;
0355 
0356         /* Then configure the top mux before switching back to it */
0357         sel[i][2] = sel[i][3] | 4;
0358 
0359         pr_debug("ccm: switching ldb_di%d_sel: %d->%d->%d->%d\n", i,
0360              sel[i][0], sel[i][1], sel[i][2], sel[i][3]);
0361     }
0362 
0363     if (sel[0][0] == sel[0][3] && sel[1][0] == sel[1][3])
0364         return;
0365 
0366     mmdc_ch1_disable(ccm_base);
0367 
0368     for (i = 1; i < 4; i++) {
0369         reg = readl_relaxed(ccm_base + CCM_CS2CDR);
0370         reg &= ~((7 << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
0371              (7 << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
0372         reg |= ((sel[0][i] << CS2CDR_LDB_DI0_CLK_SEL_SHIFT) |
0373             (sel[1][i] << CS2CDR_LDB_DI1_CLK_SEL_SHIFT));
0374         writel_relaxed(reg, ccm_base + CCM_CS2CDR);
0375     }
0376 
0377     mmdc_ch1_reenable(ccm_base);
0378 }
0379 
0380 #define CCM_ANALOG_PLL_VIDEO    0xa0
0381 #define CCM_ANALOG_PFD_480  0xf0
0382 #define CCM_ANALOG_PFD_528  0x100
0383 
0384 #define PLL_ENABLE      BIT(13)
0385 
0386 #define PFD0_CLKGATE        BIT(7)
0387 #define PFD1_CLKGATE        BIT(15)
0388 #define PFD2_CLKGATE        BIT(23)
0389 #define PFD3_CLKGATE        BIT(31)
0390 
0391 static void disable_anatop_clocks(void __iomem *anatop_base)
0392 {
0393     unsigned int reg;
0394 
0395     /* Make sure PLL2 PFDs 0-2 are gated */
0396     reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_528);
0397     /* Cannot gate PFD2 if pll2_pfd2_396m is the parent of MMDC clock */
0398     if (clk_get_parent(hws[IMX6QDL_CLK_PERIPH_PRE]->clk) ==
0399         hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk)
0400         reg |= PFD0_CLKGATE | PFD1_CLKGATE;
0401     else
0402         reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE;
0403     writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_528);
0404 
0405     /* Make sure PLL3 PFDs 0-3 are gated */
0406     reg = readl_relaxed(anatop_base + CCM_ANALOG_PFD_480);
0407     reg |= PFD0_CLKGATE | PFD1_CLKGATE | PFD2_CLKGATE | PFD3_CLKGATE;
0408     writel_relaxed(reg, anatop_base + CCM_ANALOG_PFD_480);
0409 
0410     /* Make sure PLL5 is disabled */
0411     reg = readl_relaxed(anatop_base + CCM_ANALOG_PLL_VIDEO);
0412     reg &= ~PLL_ENABLE;
0413     writel_relaxed(reg, anatop_base + CCM_ANALOG_PLL_VIDEO);
0414 }
0415 
0416 static struct clk_hw * __init imx6q_obtain_fixed_clk_hw(struct device_node *np,
0417                             const char *name,
0418                             unsigned long rate)
0419 {
0420     struct clk *clk = of_clk_get_by_name(np, name);
0421     struct clk_hw *hw;
0422 
0423     if (IS_ERR(clk))
0424         hw = imx_obtain_fixed_clock_hw(name, rate);
0425     else
0426         hw = __clk_get_hw(clk);
0427 
0428     return hw;
0429 }
0430 
0431 static void __init imx6q_clocks_init(struct device_node *ccm_node)
0432 {
0433     struct device_node *np;
0434     void __iomem *anatop_base, *base;
0435     int ret;
0436 
0437     clk_hw_data = kzalloc(struct_size(clk_hw_data, hws,
0438                       IMX6QDL_CLK_END), GFP_KERNEL);
0439     if (WARN_ON(!clk_hw_data))
0440         return;
0441 
0442     clk_hw_data->num = IMX6QDL_CLK_END;
0443     hws = clk_hw_data->hws;
0444 
0445     hws[IMX6QDL_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0);
0446 
0447     hws[IMX6QDL_CLK_CKIL] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckil", 0);
0448     hws[IMX6QDL_CLK_CKIH] = imx6q_obtain_fixed_clk_hw(ccm_node, "ckih1", 0);
0449     hws[IMX6QDL_CLK_OSC] = imx6q_obtain_fixed_clk_hw(ccm_node, "osc", 0);
0450 
0451     /* Clock source from external clock via CLK1/2 PADs */
0452     hws[IMX6QDL_CLK_ANACLK1] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk1", 0);
0453     hws[IMX6QDL_CLK_ANACLK2] = imx6q_obtain_fixed_clk_hw(ccm_node, "anaclk2", 0);
0454 
0455     np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-anatop");
0456     anatop_base = base = of_iomap(np, 0);
0457     WARN_ON(!base);
0458     of_node_put(np);
0459 
0460     /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */
0461     if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) {
0462         post_div_table[1].div = 1;
0463         post_div_table[2].div = 1;
0464         video_div_table[1].div = 1;
0465         video_div_table[3].div = 1;
0466     }
0467 
0468     hws[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_hw_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0469     hws[IMX6QDL_PLL2_BYPASS_SRC] = imx_clk_hw_mux("pll2_bypass_src", base + 0x30, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0470     hws[IMX6QDL_PLL3_BYPASS_SRC] = imx_clk_hw_mux("pll3_bypass_src", base + 0x10, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0471     hws[IMX6QDL_PLL4_BYPASS_SRC] = imx_clk_hw_mux("pll4_bypass_src", base + 0x70, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0472     hws[IMX6QDL_PLL5_BYPASS_SRC] = imx_clk_hw_mux("pll5_bypass_src", base + 0xa0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0473     hws[IMX6QDL_PLL6_BYPASS_SRC] = imx_clk_hw_mux("pll6_bypass_src", base + 0xe0, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0474     hws[IMX6QDL_PLL7_BYPASS_SRC] = imx_clk_hw_mux("pll7_bypass_src", base + 0x20, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
0475 
0476     /*                                    type               name    parent_name        base         div_mask */
0477     hws[IMX6QDL_CLK_PLL1] = imx_clk_hw_pllv3(IMX_PLLV3_SYS,     "pll1", "osc", base + 0x00, 0x7f);
0478     hws[IMX6QDL_CLK_PLL2] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2", "osc", base + 0x30, 0x1);
0479     hws[IMX6QDL_CLK_PLL3] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll3", "osc", base + 0x10, 0x3);
0480     hws[IMX6QDL_CLK_PLL4] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll4", "osc", base + 0x70, 0x7f);
0481     hws[IMX6QDL_CLK_PLL5] = imx_clk_hw_pllv3(IMX_PLLV3_AV,      "pll5", "osc", base + 0xa0, 0x7f);
0482     hws[IMX6QDL_CLK_PLL6] = imx_clk_hw_pllv3(IMX_PLLV3_ENET,    "pll6", "osc", base + 0xe0, 0x3);
0483     hws[IMX6QDL_CLK_PLL7] = imx_clk_hw_pllv3(IMX_PLLV3_USB,     "pll7", "osc", base + 0x20, 0x3);
0484 
0485     hws[IMX6QDL_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", base + 0x00, 16, 1, pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
0486     hws[IMX6QDL_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", base + 0x30, 16, 1, pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
0487     hws[IMX6QDL_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", base + 0x10, 16, 1, pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
0488     hws[IMX6QDL_PLL4_BYPASS] = imx_clk_hw_mux_flags("pll4_bypass", base + 0x70, 16, 1, pll4_bypass_sels, ARRAY_SIZE(pll4_bypass_sels), CLK_SET_RATE_PARENT);
0489     hws[IMX6QDL_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", base + 0xa0, 16, 1, pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
0490     hws[IMX6QDL_PLL6_BYPASS] = imx_clk_hw_mux_flags("pll6_bypass", base + 0xe0, 16, 1, pll6_bypass_sels, ARRAY_SIZE(pll6_bypass_sels), CLK_SET_RATE_PARENT);
0491     hws[IMX6QDL_PLL7_BYPASS] = imx_clk_hw_mux_flags("pll7_bypass", base + 0x20, 16, 1, pll7_bypass_sels, ARRAY_SIZE(pll7_bypass_sels), CLK_SET_RATE_PARENT);
0492 
0493     /* Do not bypass PLLs initially */
0494     clk_set_parent(hws[IMX6QDL_PLL1_BYPASS]->clk, hws[IMX6QDL_CLK_PLL1]->clk);
0495     clk_set_parent(hws[IMX6QDL_PLL2_BYPASS]->clk, hws[IMX6QDL_CLK_PLL2]->clk);
0496     clk_set_parent(hws[IMX6QDL_PLL3_BYPASS]->clk, hws[IMX6QDL_CLK_PLL3]->clk);
0497     clk_set_parent(hws[IMX6QDL_PLL4_BYPASS]->clk, hws[IMX6QDL_CLK_PLL4]->clk);
0498     clk_set_parent(hws[IMX6QDL_PLL5_BYPASS]->clk, hws[IMX6QDL_CLK_PLL5]->clk);
0499     clk_set_parent(hws[IMX6QDL_PLL6_BYPASS]->clk, hws[IMX6QDL_CLK_PLL6]->clk);
0500     clk_set_parent(hws[IMX6QDL_PLL7_BYPASS]->clk, hws[IMX6QDL_CLK_PLL7]->clk);
0501 
0502     hws[IMX6QDL_CLK_PLL1_SYS]      = imx_clk_hw_gate("pll1_sys",      "pll1_bypass", base + 0x00, 13);
0503     hws[IMX6QDL_CLK_PLL2_BUS]      = imx_clk_hw_gate("pll2_bus",      "pll2_bypass", base + 0x30, 13);
0504     hws[IMX6QDL_CLK_PLL3_USB_OTG]  = imx_clk_hw_gate("pll3_usb_otg",  "pll3_bypass", base + 0x10, 13);
0505     hws[IMX6QDL_CLK_PLL4_AUDIO]    = imx_clk_hw_gate("pll4_audio",    "pll4_bypass", base + 0x70, 13);
0506     hws[IMX6QDL_CLK_PLL5_VIDEO]    = imx_clk_hw_gate("pll5_video",    "pll5_bypass", base + 0xa0, 13);
0507     hws[IMX6QDL_CLK_PLL6_ENET]     = imx_clk_hw_gate("pll6_enet",     "pll6_bypass", base + 0xe0, 13);
0508     hws[IMX6QDL_CLK_PLL7_USB_HOST] = imx_clk_hw_gate("pll7_usb_host", "pll7_bypass", base + 0x20, 13);
0509 
0510     /*
0511      * Bit 20 is the reserved and read-only bit, we do this only for:
0512      * - Do nothing for usbphy clk_enable/disable
0513      * - Keep refcount when do usbphy clk_enable/disable, in that case,
0514      * the clk framework may need to enable/disable usbphy's parent
0515      */
0516     hws[IMX6QDL_CLK_USBPHY1] = imx_clk_hw_gate("usbphy1", "pll3_usb_otg", base + 0x10, 20);
0517     hws[IMX6QDL_CLK_USBPHY2] = imx_clk_hw_gate("usbphy2", "pll7_usb_host", base + 0x20, 20);
0518 
0519     /*
0520      * usbphy*_gate needs to be on after system boots up, and software
0521      * never needs to control it anymore.
0522      */
0523     hws[IMX6QDL_CLK_USBPHY1_GATE] = imx_clk_hw_gate("usbphy1_gate", "dummy", base + 0x10, 6);
0524     hws[IMX6QDL_CLK_USBPHY2_GATE] = imx_clk_hw_gate("usbphy2_gate", "dummy", base + 0x20, 6);
0525 
0526     /*
0527      * The ENET PLL is special in that is has multiple outputs with
0528      * different post-dividers that are all affected by the single bypass
0529      * bit, so a single mux bit affects 3 independent branches of the clock
0530      * tree. There is no good way to model this in the clock framework and
0531      * dynamically changing the bypass bit, will yield unexpected results.
0532      * So we treat any configuration that bypasses the ENET PLL as
0533      * essentially static with the divider ratios reflecting the bypass
0534      * status.
0535      *
0536      */
0537     if (!pll6_bypassed(ccm_node)) {
0538         hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 5);
0539         hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 4);
0540         hws[IMX6QDL_CLK_ENET_REF] = clk_hw_register_divider_table(NULL, "enet_ref", "pll6_enet", 0,
0541                         base + 0xe0, 0, 2, 0, clk_enet_ref_table,
0542                         &imx_ccm_lock);
0543     } else {
0544         hws[IMX6QDL_CLK_SATA_REF] = imx_clk_hw_fixed_factor("sata_ref", "pll6_enet", 1, 1);
0545         hws[IMX6QDL_CLK_PCIE_REF] = imx_clk_hw_fixed_factor("pcie_ref", "pll6_enet", 1, 1);
0546         hws[IMX6QDL_CLK_ENET_REF] = imx_clk_hw_fixed_factor("enet_ref", "pll6_enet", 1, 1);
0547     }
0548 
0549     hws[IMX6QDL_CLK_SATA_REF_100M] = imx_clk_hw_gate("sata_ref_100m", "sata_ref", base + 0xe0, 20);
0550     hws[IMX6QDL_CLK_PCIE_REF_125M] = imx_clk_hw_gate("pcie_ref_125m", "pcie_ref", base + 0xe0, 19);
0551 
0552     hws[IMX6QDL_CLK_LVDS1_SEL] = imx_clk_hw_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
0553     hws[IMX6QDL_CLK_LVDS2_SEL] = imx_clk_hw_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels));
0554 
0555     /*
0556      * lvds1_gate and lvds2_gate are pseudo-gates.  Both can be
0557      * independently configured as clock inputs or outputs.  We treat
0558      * the "output_enable" bit as a gate, even though it's really just
0559      * enabling clock output. Initially the gate bits are cleared, as
0560      * otherwise the exclusive configuration gets locked in the setup done
0561      * by software running before the clock driver, with no way to change
0562      * it.
0563      */
0564     writel(readl(base + 0x160) & ~0x3c00, base + 0x160);
0565     hws[IMX6QDL_CLK_LVDS1_GATE] = imx_clk_hw_gate_exclusive("lvds1_gate", "lvds1_sel", base + 0x160, 10, BIT(12));
0566     hws[IMX6QDL_CLK_LVDS2_GATE] = imx_clk_hw_gate_exclusive("lvds2_gate", "lvds2_sel", base + 0x160, 11, BIT(13));
0567 
0568     hws[IMX6QDL_CLK_LVDS1_IN] = imx_clk_hw_gate_exclusive("lvds1_in", "anaclk1", base + 0x160, 12, BIT(10));
0569     hws[IMX6QDL_CLK_LVDS2_IN] = imx_clk_hw_gate_exclusive("lvds2_in", "anaclk2", base + 0x160, 13, BIT(11));
0570 
0571     /*                                            name              parent_name        reg       idx */
0572     hws[IMX6QDL_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_bus",     base + 0x100, 0);
0573     hws[IMX6QDL_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_bus",     base + 0x100, 1);
0574     hws[IMX6QDL_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_bus",     base + 0x100, 2);
0575     hws[IMX6QDL_CLK_PLL3_PFD0_720M] = imx_clk_hw_pfd("pll3_pfd0_720m", "pll3_usb_otg", base + 0xf0,  0);
0576     hws[IMX6QDL_CLK_PLL3_PFD1_540M] = imx_clk_hw_pfd("pll3_pfd1_540m", "pll3_usb_otg", base + 0xf0,  1);
0577     hws[IMX6QDL_CLK_PLL3_PFD2_508M] = imx_clk_hw_pfd("pll3_pfd2_508m", "pll3_usb_otg", base + 0xf0,  2);
0578     hws[IMX6QDL_CLK_PLL3_PFD3_454M] = imx_clk_hw_pfd("pll3_pfd3_454m", "pll3_usb_otg", base + 0xf0,  3);
0579 
0580     /*                                                name         parent_name     mult div */
0581     hws[IMX6QDL_CLK_PLL2_198M] = imx_clk_hw_fixed_factor("pll2_198m", "pll2_pfd2_396m", 1, 2);
0582     hws[IMX6QDL_CLK_PLL3_120M] = imx_clk_hw_fixed_factor("pll3_120m", "pll3_usb_otg",   1, 4);
0583     hws[IMX6QDL_CLK_PLL3_80M]  = imx_clk_hw_fixed_factor("pll3_80m",  "pll3_usb_otg",   1, 6);
0584     hws[IMX6QDL_CLK_PLL3_60M]  = imx_clk_hw_fixed_factor("pll3_60m",  "pll3_usb_otg",   1, 8);
0585     hws[IMX6QDL_CLK_TWD]       = imx_clk_hw_fixed_factor("twd",       "arm",            1, 2);
0586     hws[IMX6QDL_CLK_GPT_3M]    = imx_clk_hw_fixed_factor("gpt_3m",    "osc",            1, 8);
0587     hws[IMX6QDL_CLK_VIDEO_27M] = imx_clk_hw_fixed_factor("video_27m", "pll3_pfd1_540m", 1, 20);
0588     if (clk_on_imx6dl() || clk_on_imx6qp()) {
0589         hws[IMX6QDL_CLK_GPU2D_AXI] = imx_clk_hw_fixed_factor("gpu2d_axi", "mmdc_ch0_axi_podf", 1, 1);
0590         hws[IMX6QDL_CLK_GPU3D_AXI] = imx_clk_hw_fixed_factor("gpu3d_axi", "mmdc_ch0_axi_podf", 1, 1);
0591     }
0592 
0593     hws[IMX6QDL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock);
0594     if (clk_on_imx6q() || clk_on_imx6qp())
0595         hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = imx_clk_hw_fixed_factor("pll4_audio_div", "pll4_post_div", 1, 1);
0596     else
0597         hws[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_hw_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock);
0598     hws[IMX6QDL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock);
0599     hws[IMX6QDL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock);
0600 
0601     np = ccm_node;
0602     base = of_iomap(np, 0);
0603     WARN_ON(!base);
0604 
0605     /*                                              name                reg       shift width parent_names     num_parents */
0606     hws[IMX6QDL_CLK_STEP]             = imx_clk_hw_mux("step",              base + 0xc,  8,  1, step_sels,     ARRAY_SIZE(step_sels));
0607     hws[IMX6QDL_CLK_PLL1_SW]          = imx_clk_hw_mux("pll1_sw",       base + 0xc,  2,  1, pll1_sw_sels,      ARRAY_SIZE(pll1_sw_sels));
0608     hws[IMX6QDL_CLK_PERIPH_PRE]       = imx_clk_hw_mux("periph_pre",       base + 0x18, 18, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
0609     hws[IMX6QDL_CLK_PERIPH2_PRE]      = imx_clk_hw_mux("periph2_pre",      base + 0x18, 21, 2, periph_pre_sels,   ARRAY_SIZE(periph_pre_sels));
0610     hws[IMX6QDL_CLK_PERIPH_CLK2_SEL]  = imx_clk_hw_mux("periph_clk2_sel",  base + 0x18, 12, 2, periph_clk2_sels,  ARRAY_SIZE(periph_clk2_sels));
0611     hws[IMX6QDL_CLK_PERIPH2_CLK2_SEL] = imx_clk_hw_mux("periph2_clk2_sel", base + 0x18, 20, 1, periph2_clk2_sels, ARRAY_SIZE(periph2_clk2_sels));
0612     hws[IMX6QDL_CLK_AXI_SEL]          = imx_clk_hw_mux("axi_sel",          base + 0x14, 6,  2, axi_sels,          ARRAY_SIZE(axi_sels));
0613     hws[IMX6QDL_CLK_ESAI_SEL]         = imx_clk_hw_mux("esai_sel",         base + 0x20, 19, 2, audio_sels,        ARRAY_SIZE(audio_sels));
0614     hws[IMX6QDL_CLK_ASRC_SEL]         = imx_clk_hw_mux("asrc_sel",         base + 0x30, 7,  2, audio_sels,        ARRAY_SIZE(audio_sels));
0615     hws[IMX6QDL_CLK_SPDIF_SEL]        = imx_clk_hw_mux("spdif_sel",        base + 0x30, 20, 2, audio_sels,        ARRAY_SIZE(audio_sels));
0616     if (clk_on_imx6q()) {
0617         hws[IMX6QDL_CLK_GPU2D_AXI]        = imx_clk_hw_mux("gpu2d_axi",        base + 0x18, 0,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
0618         hws[IMX6QDL_CLK_GPU3D_AXI]        = imx_clk_hw_mux("gpu3d_axi",        base + 0x18, 1,  1, gpu_axi_sels,      ARRAY_SIZE(gpu_axi_sels));
0619     }
0620     if (clk_on_imx6qp()) {
0621         hws[IMX6QDL_CLK_CAN_SEL]   = imx_clk_hw_mux("can_sel",  base + 0x20, 8,  2, can_sels, ARRAY_SIZE(can_sels));
0622         hws[IMX6QDL_CLK_ECSPI_SEL] = imx_clk_hw_mux("ecspi_sel",    base + 0x38, 18, 1, ecspi_sels,  ARRAY_SIZE(ecspi_sels));
0623         hws[IMX6QDL_CLK_IPG_PER_SEL] = imx_clk_hw_mux("ipg_per_sel", base + 0x1c, 6, 1, ipg_per_sels, ARRAY_SIZE(ipg_per_sels));
0624         hws[IMX6QDL_CLK_UART_SEL] = imx_clk_hw_mux("uart_sel", base + 0x24, 6, 1, uart_sels, ARRAY_SIZE(uart_sels));
0625         hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 16, 2, gpu2d_core_sels_2, ARRAY_SIZE(gpu2d_core_sels_2));
0626     } else if (clk_on_imx6dl()) {
0627         hws[IMX6QDL_CLK_MLB_SEL] = imx_clk_hw_mux("mlb_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
0628     } else {
0629         hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel",   base + 0x18, 16, 2, gpu2d_core_sels,   ARRAY_SIZE(gpu2d_core_sels));
0630     }
0631     hws[IMX6QDL_CLK_GPU3D_CORE_SEL]   = imx_clk_hw_mux("gpu3d_core_sel",   base + 0x18, 4,  2, gpu3d_core_sels,   ARRAY_SIZE(gpu3d_core_sels));
0632     if (clk_on_imx6dl())
0633         hws[IMX6QDL_CLK_GPU2D_CORE_SEL] = imx_clk_hw_mux("gpu2d_core_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
0634     else
0635         hws[IMX6QDL_CLK_GPU3D_SHADER_SEL] = imx_clk_hw_mux("gpu3d_shader_sel", base + 0x18, 8,  2, gpu3d_shader_sels, ARRAY_SIZE(gpu3d_shader_sels));
0636     hws[IMX6QDL_CLK_IPU1_SEL]         = imx_clk_hw_mux("ipu1_sel",         base + 0x3c, 9,  2, ipu_sels,          ARRAY_SIZE(ipu_sels));
0637     hws[IMX6QDL_CLK_IPU2_SEL]         = imx_clk_hw_mux("ipu2_sel",         base + 0x3c, 14, 2, ipu_sels,          ARRAY_SIZE(ipu_sels));
0638 
0639     disable_anatop_clocks(anatop_base);
0640 
0641     imx_mmdc_mask_handshake(base, 1);
0642 
0643     if (clk_on_imx6qp()) {
0644         hws[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_hw_mux_flags("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
0645         hws[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_hw_mux_flags("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels), CLK_SET_RATE_PARENT);
0646     } else {
0647         /*
0648          * The LDB_DI0/1_SEL muxes are registered read-only due to a hardware
0649          * bug. Set the muxes to the requested values before registering the
0650          * ldb_di_sel clocks.
0651          */
0652         init_ldb_clks(np, base);
0653 
0654         hws[IMX6QDL_CLK_LDB_DI0_SEL]      = imx_clk_hw_mux_ldb("ldb_di0_sel", base + 0x2c, 9,  3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels));
0655         hws[IMX6QDL_CLK_LDB_DI1_SEL]      = imx_clk_hw_mux_ldb("ldb_di1_sel", base + 0x2c, 12, 3, ldb_di_sels,      ARRAY_SIZE(ldb_di_sels));
0656     }
0657 
0658     hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di0_pre_sel", base + 0x34, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
0659     hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu1_di1_pre_sel", base + 0x34, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
0660     hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di0_pre_sel", base + 0x38, 6,  3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
0661     hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL] = imx_clk_hw_mux_flags("ipu2_di1_pre_sel", base + 0x38, 15, 3, ipu_di_pre_sels,   ARRAY_SIZE(ipu_di_pre_sels), CLK_SET_RATE_PARENT);
0662     hws[IMX6QDL_CLK_HSI_TX_SEL]       = imx_clk_hw_mux("hsi_tx_sel",       base + 0x30, 28, 1, hsi_tx_sels,       ARRAY_SIZE(hsi_tx_sels));
0663     hws[IMX6QDL_CLK_PCIE_AXI_SEL]     = imx_clk_hw_mux("pcie_axi_sel",     base + 0x18, 10, 1, pcie_axi_sels,     ARRAY_SIZE(pcie_axi_sels));
0664 
0665     if (clk_on_imx6qp()) {
0666         hws[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_hw_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels_2,     ARRAY_SIZE(ipu1_di0_sels_2), CLK_SET_RATE_PARENT);
0667         hws[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_hw_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels_2,     ARRAY_SIZE(ipu1_di1_sels_2), CLK_SET_RATE_PARENT);
0668         hws[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_hw_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels_2,     ARRAY_SIZE(ipu2_di0_sels_2), CLK_SET_RATE_PARENT);
0669         hws[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_hw_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels_2,     ARRAY_SIZE(ipu2_di1_sels_2), CLK_SET_RATE_PARENT);
0670         hws[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_hw_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
0671         hws[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_hw_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
0672         hws[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_hw_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels));
0673         hws[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_hw_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
0674         hws[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_hw_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
0675         hws[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_hw_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
0676         hws[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_hw_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels));
0677         hws[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_hw_mux("enfc_sel",         base + 0x2c, 15, 3, enfc_sels_2,         ARRAY_SIZE(enfc_sels_2));
0678         hws[IMX6QDL_CLK_EIM_SEL]          = imx_clk_hw_mux("eim_sel",      base + 0x1c, 27, 2, eim_sels,        ARRAY_SIZE(eim_sels));
0679         hws[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_hw_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels,   ARRAY_SIZE(eim_slow_sels));
0680         hws[IMX6QDL_CLK_PRE_AXI]      = imx_clk_hw_mux("pre_axi",   base + 0x18, 1,  1, pre_axi_sels,    ARRAY_SIZE(pre_axi_sels));
0681     } else {
0682         hws[IMX6QDL_CLK_IPU1_DI0_SEL]     = imx_clk_hw_mux_flags("ipu1_di0_sel",     base + 0x34, 0,  3, ipu1_di0_sels,     ARRAY_SIZE(ipu1_di0_sels), CLK_SET_RATE_PARENT);
0683         hws[IMX6QDL_CLK_IPU1_DI1_SEL]     = imx_clk_hw_mux_flags("ipu1_di1_sel",     base + 0x34, 9,  3, ipu1_di1_sels,     ARRAY_SIZE(ipu1_di1_sels), CLK_SET_RATE_PARENT);
0684         hws[IMX6QDL_CLK_IPU2_DI0_SEL]     = imx_clk_hw_mux_flags("ipu2_di0_sel",     base + 0x38, 0,  3, ipu2_di0_sels,     ARRAY_SIZE(ipu2_di0_sels), CLK_SET_RATE_PARENT);
0685         hws[IMX6QDL_CLK_IPU2_DI1_SEL]     = imx_clk_hw_mux_flags("ipu2_di1_sel",     base + 0x38, 9,  3, ipu2_di1_sels,     ARRAY_SIZE(ipu2_di1_sels), CLK_SET_RATE_PARENT);
0686         hws[IMX6QDL_CLK_SSI1_SEL]         = imx_clk_hw_fixup_mux("ssi1_sel",   base + 0x1c, 10, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
0687         hws[IMX6QDL_CLK_SSI2_SEL]         = imx_clk_hw_fixup_mux("ssi2_sel",   base + 0x1c, 12, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
0688         hws[IMX6QDL_CLK_SSI3_SEL]         = imx_clk_hw_fixup_mux("ssi3_sel",   base + 0x1c, 14, 2, ssi_sels,          ARRAY_SIZE(ssi_sels), imx_cscmr1_fixup);
0689         hws[IMX6QDL_CLK_USDHC1_SEL]       = imx_clk_hw_fixup_mux("usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
0690         hws[IMX6QDL_CLK_USDHC2_SEL]       = imx_clk_hw_fixup_mux("usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
0691         hws[IMX6QDL_CLK_USDHC3_SEL]       = imx_clk_hw_fixup_mux("usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
0692         hws[IMX6QDL_CLK_USDHC4_SEL]       = imx_clk_hw_fixup_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels,        ARRAY_SIZE(usdhc_sels), imx_cscmr1_fixup);
0693         hws[IMX6QDL_CLK_ENFC_SEL]         = imx_clk_hw_mux("enfc_sel",         base + 0x2c, 16, 2, enfc_sels,         ARRAY_SIZE(enfc_sels));
0694         hws[IMX6QDL_CLK_EIM_SEL]          = imx_clk_hw_fixup_mux("eim_sel",      base + 0x1c, 27, 2, eim_sels,        ARRAY_SIZE(eim_sels), imx_cscmr1_fixup);
0695         hws[IMX6QDL_CLK_EIM_SLOW_SEL]     = imx_clk_hw_fixup_mux("eim_slow_sel", base + 0x1c, 29, 2, eim_slow_sels,   ARRAY_SIZE(eim_slow_sels), imx_cscmr1_fixup);
0696     }
0697 
0698     hws[IMX6QDL_CLK_VDO_AXI_SEL]      = imx_clk_hw_mux("vdo_axi_sel",      base + 0x18, 11, 1, vdo_axi_sels,      ARRAY_SIZE(vdo_axi_sels));
0699     hws[IMX6QDL_CLK_VPU_AXI_SEL]      = imx_clk_hw_mux("vpu_axi_sel",      base + 0x18, 14, 2, vpu_axi_sels,      ARRAY_SIZE(vpu_axi_sels));
0700     hws[IMX6QDL_CLK_CKO1_SEL]         = imx_clk_hw_mux("cko1_sel",         base + 0x60, 0,  4, cko1_sels,         ARRAY_SIZE(cko1_sels));
0701     hws[IMX6QDL_CLK_CKO2_SEL]         = imx_clk_hw_mux("cko2_sel",         base + 0x60, 16, 5, cko2_sels,         ARRAY_SIZE(cko2_sels));
0702     hws[IMX6QDL_CLK_CKO]              = imx_clk_hw_mux("cko",              base + 0x60, 8, 1,  cko_sels,          ARRAY_SIZE(cko_sels));
0703 
0704     /*                                          name         reg      shift width busy: reg, shift parent_names  num_parents */
0705     hws[IMX6QDL_CLK_PERIPH]  = imx_clk_hw_busy_mux("periph",  base + 0x14, 25,  1,   base + 0x48, 5,  periph_sels,  ARRAY_SIZE(periph_sels));
0706     hws[IMX6QDL_CLK_PERIPH2] = imx_clk_hw_busy_mux("periph2", base + 0x14, 26,  1,   base + 0x48, 3,  periph2_sels, ARRAY_SIZE(periph2_sels));
0707 
0708     /*                                                  name                parent_name          reg       shift width */
0709     hws[IMX6QDL_CLK_PERIPH_CLK2]      = imx_clk_hw_divider("periph_clk2",      "periph_clk2_sel",   base + 0x14, 27, 3);
0710     hws[IMX6QDL_CLK_PERIPH2_CLK2]     = imx_clk_hw_divider("periph2_clk2",     "periph2_clk2_sel",  base + 0x14, 0,  3);
0711     hws[IMX6QDL_CLK_IPG]              = imx_clk_hw_divider("ipg",              "ahb",               base + 0x14, 8,  2);
0712     hws[IMX6QDL_CLK_ESAI_PRED]        = imx_clk_hw_divider("esai_pred",        "esai_sel",          base + 0x28, 9,  3);
0713     hws[IMX6QDL_CLK_ESAI_PODF]        = imx_clk_hw_divider("esai_podf",        "esai_pred",         base + 0x28, 25, 3);
0714     hws[IMX6QDL_CLK_ASRC_PRED]        = imx_clk_hw_divider("asrc_pred",        "asrc_sel",          base + 0x30, 12, 3);
0715     hws[IMX6QDL_CLK_ASRC_PODF]        = imx_clk_hw_divider("asrc_podf",        "asrc_pred",         base + 0x30, 9,  3);
0716     hws[IMX6QDL_CLK_SPDIF_PRED]       = imx_clk_hw_divider("spdif_pred",       "spdif_sel",         base + 0x30, 25, 3);
0717     hws[IMX6QDL_CLK_SPDIF_PODF]       = imx_clk_hw_divider("spdif_podf",       "spdif_pred",        base + 0x30, 22, 3);
0718 
0719     if (clk_on_imx6qp()) {
0720         hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_divider("ipg_per", "ipg_per_sel", base + 0x1c, 0, 6);
0721         hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6);
0722         hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "can_sel", base + 0x20, 2, 6);
0723         hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "uart_sel", base + 0x24, 0, 6);
0724         hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0", 2, 7);
0725         hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1", 2, 7);
0726     } else {
0727         hws[IMX6QDL_CLK_ECSPI_ROOT] = imx_clk_hw_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6);
0728         hws[IMX6QDL_CLK_CAN_ROOT] = imx_clk_hw_divider("can_root", "pll3_60m", base + 0x20, 2, 6);
0729         hws[IMX6QDL_CLK_IPG_PER] = imx_clk_hw_fixup_divider("ipg_per", "ipg", base + 0x1c, 0, 6, imx_cscmr1_fixup);
0730         hws[IMX6QDL_CLK_UART_SERIAL_PODF] = imx_clk_hw_divider("uart_serial_podf", "pll3_80m",          base + 0x24, 0,  6);
0731         hws[IMX6QDL_CLK_LDB_DI0_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
0732         hws[IMX6QDL_CLK_LDB_DI1_DIV_3_5] = imx_clk_hw_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
0733     }
0734 
0735     if (clk_on_imx6dl())
0736         hws[IMX6QDL_CLK_MLB_PODF]  = imx_clk_hw_divider("mlb_podf",  "mlb_sel",    base + 0x18, 23, 3);
0737     else
0738         hws[IMX6QDL_CLK_GPU2D_CORE_PODF]  = imx_clk_hw_divider("gpu2d_core_podf",  "gpu2d_core_sel",    base + 0x18, 23, 3);
0739     hws[IMX6QDL_CLK_GPU3D_CORE_PODF]  = imx_clk_hw_divider("gpu3d_core_podf",  "gpu3d_core_sel",    base + 0x18, 26, 3);
0740     if (clk_on_imx6dl())
0741         hws[IMX6QDL_CLK_GPU2D_CORE_PODF]  = imx_clk_hw_divider("gpu2d_core_podf",     "gpu2d_core_sel",  base + 0x18, 29, 3);
0742     else
0743         hws[IMX6QDL_CLK_GPU3D_SHADER]     = imx_clk_hw_divider("gpu3d_shader",     "gpu3d_shader_sel",  base + 0x18, 29, 3);
0744     hws[IMX6QDL_CLK_IPU1_PODF]        = imx_clk_hw_divider("ipu1_podf",        "ipu1_sel",          base + 0x3c, 11, 3);
0745     hws[IMX6QDL_CLK_IPU2_PODF]        = imx_clk_hw_divider("ipu2_podf",        "ipu2_sel",          base + 0x3c, 16, 3);
0746     hws[IMX6QDL_CLK_LDB_DI0_PODF]     = imx_clk_hw_divider_flags("ldb_di0_podf", "ldb_di0_div_3_5", base + 0x20, 10, 1, 0);
0747     hws[IMX6QDL_CLK_LDB_DI1_PODF]     = imx_clk_hw_divider_flags("ldb_di1_podf", "ldb_di1_div_3_5", base + 0x20, 11, 1, 0);
0748     hws[IMX6QDL_CLK_IPU1_DI0_PRE]     = imx_clk_hw_divider("ipu1_di0_pre",     "ipu1_di0_pre_sel",  base + 0x34, 3,  3);
0749     hws[IMX6QDL_CLK_IPU1_DI1_PRE]     = imx_clk_hw_divider("ipu1_di1_pre",     "ipu1_di1_pre_sel",  base + 0x34, 12, 3);
0750     hws[IMX6QDL_CLK_IPU2_DI0_PRE]     = imx_clk_hw_divider("ipu2_di0_pre",     "ipu2_di0_pre_sel",  base + 0x38, 3,  3);
0751     hws[IMX6QDL_CLK_IPU2_DI1_PRE]     = imx_clk_hw_divider("ipu2_di1_pre",     "ipu2_di1_pre_sel",  base + 0x38, 12, 3);
0752     hws[IMX6QDL_CLK_HSI_TX_PODF]      = imx_clk_hw_divider("hsi_tx_podf",      "hsi_tx_sel",        base + 0x30, 29, 3);
0753     hws[IMX6QDL_CLK_SSI1_PRED]        = imx_clk_hw_divider("ssi1_pred",        "ssi1_sel",          base + 0x28, 6,  3);
0754     hws[IMX6QDL_CLK_SSI1_PODF]        = imx_clk_hw_divider("ssi1_podf",        "ssi1_pred",         base + 0x28, 0,  6);
0755     hws[IMX6QDL_CLK_SSI2_PRED]        = imx_clk_hw_divider("ssi2_pred",        "ssi2_sel",          base + 0x2c, 6,  3);
0756     hws[IMX6QDL_CLK_SSI2_PODF]        = imx_clk_hw_divider("ssi2_podf",        "ssi2_pred",         base + 0x2c, 0,  6);
0757     hws[IMX6QDL_CLK_SSI3_PRED]        = imx_clk_hw_divider("ssi3_pred",        "ssi3_sel",          base + 0x28, 22, 3);
0758     hws[IMX6QDL_CLK_SSI3_PODF]        = imx_clk_hw_divider("ssi3_podf",        "ssi3_pred",         base + 0x28, 16, 6);
0759     hws[IMX6QDL_CLK_USDHC1_PODF]      = imx_clk_hw_divider("usdhc1_podf",      "usdhc1_sel",        base + 0x24, 11, 3);
0760     hws[IMX6QDL_CLK_USDHC2_PODF]      = imx_clk_hw_divider("usdhc2_podf",      "usdhc2_sel",        base + 0x24, 16, 3);
0761     hws[IMX6QDL_CLK_USDHC3_PODF]      = imx_clk_hw_divider("usdhc3_podf",      "usdhc3_sel",        base + 0x24, 19, 3);
0762     hws[IMX6QDL_CLK_USDHC4_PODF]      = imx_clk_hw_divider("usdhc4_podf",      "usdhc4_sel",        base + 0x24, 22, 3);
0763     hws[IMX6QDL_CLK_ENFC_PRED]        = imx_clk_hw_divider("enfc_pred",        "enfc_sel",          base + 0x2c, 18, 3);
0764     hws[IMX6QDL_CLK_ENFC_PODF]        = imx_clk_hw_divider("enfc_podf",        "enfc_pred",         base + 0x2c, 21, 6);
0765     if (clk_on_imx6qp()) {
0766         hws[IMX6QDL_CLK_EIM_PODF]         = imx_clk_hw_divider("eim_podf",   "eim_sel",           base + 0x1c, 20, 3);
0767         hws[IMX6QDL_CLK_EIM_SLOW_PODF]    = imx_clk_hw_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3);
0768     } else {
0769         hws[IMX6QDL_CLK_EIM_PODF]         = imx_clk_hw_fixup_divider("eim_podf",   "eim_sel",           base + 0x1c, 20, 3, imx_cscmr1_fixup);
0770         hws[IMX6QDL_CLK_EIM_SLOW_PODF]    = imx_clk_hw_fixup_divider("eim_slow_podf", "eim_slow_sel",   base + 0x1c, 23, 3, imx_cscmr1_fixup);
0771     }
0772 
0773     hws[IMX6QDL_CLK_VPU_AXI_PODF]     = imx_clk_hw_divider("vpu_axi_podf",     "vpu_axi_sel",       base + 0x24, 25, 3);
0774     hws[IMX6QDL_CLK_CKO1_PODF]        = imx_clk_hw_divider("cko1_podf",        "cko1_sel",          base + 0x60, 4,  3);
0775     hws[IMX6QDL_CLK_CKO2_PODF]        = imx_clk_hw_divider("cko2_podf",        "cko2_sel",          base + 0x60, 21, 3);
0776 
0777     /*                                                        name                 parent_name    reg        shift width busy: reg, shift */
0778     hws[IMX6QDL_CLK_AXI]               = imx_clk_hw_busy_divider("axi",               "axi_sel",     base + 0x14, 16,  3,   base + 0x48, 0);
0779     hws[IMX6QDL_CLK_MMDC_CH0_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch0_axi_podf", "periph",      base + 0x14, 19,  3,   base + 0x48, 4);
0780     if (clk_on_imx6qp()) {
0781         hws[IMX6QDL_CLK_MMDC_CH1_AXI_CG] = imx_clk_hw_gate("mmdc_ch1_axi_cg", "periph2", base + 0x4, 18);
0782         hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "mmdc_ch1_axi_cg", base + 0x14, 3, 3, base + 0x48, 2);
0783     } else {
0784         hws[IMX6QDL_CLK_MMDC_CH1_AXI_PODF] = imx_clk_hw_busy_divider("mmdc_ch1_axi_podf", "periph2",     base + 0x14, 3,   3,   base + 0x48, 2);
0785     }
0786     hws[IMX6QDL_CLK_ARM]               = imx_clk_hw_busy_divider("arm",               "pll1_sw",     base + 0x10, 0,   3,   base + 0x48, 16);
0787     hws[IMX6QDL_CLK_AHB]               = imx_clk_hw_busy_divider("ahb",               "periph",      base + 0x14, 10,  3,   base + 0x48, 1);
0788 
0789     /*                                            name             parent_name          reg         shift */
0790     hws[IMX6QDL_CLK_APBH_DMA]     = imx_clk_hw_gate2("apbh_dma",      "usdhc3",            base + 0x68, 4);
0791     hws[IMX6QDL_CLK_ASRC]         = imx_clk_hw_gate2_shared("asrc",         "asrc_podf",   base + 0x68, 6, &share_count_asrc);
0792     hws[IMX6QDL_CLK_ASRC_IPG]     = imx_clk_hw_gate2_shared("asrc_ipg",     "ahb",         base + 0x68, 6, &share_count_asrc);
0793     hws[IMX6QDL_CLK_ASRC_MEM]     = imx_clk_hw_gate2_shared("asrc_mem",     "ahb",         base + 0x68, 6, &share_count_asrc);
0794     hws[IMX6QDL_CLK_CAAM_MEM]     = imx_clk_hw_gate2("caam_mem",      "ahb",               base + 0x68, 8);
0795     hws[IMX6QDL_CLK_CAAM_ACLK]    = imx_clk_hw_gate2("caam_aclk",     "ahb",               base + 0x68, 10);
0796     hws[IMX6QDL_CLK_CAAM_IPG]     = imx_clk_hw_gate2("caam_ipg",      "ipg",               base + 0x68, 12);
0797     hws[IMX6QDL_CLK_CAN1_IPG]     = imx_clk_hw_gate2("can1_ipg",      "ipg",               base + 0x68, 14);
0798     hws[IMX6QDL_CLK_CAN1_SERIAL]  = imx_clk_hw_gate2("can1_serial",   "can_root",          base + 0x68, 16);
0799     hws[IMX6QDL_CLK_CAN2_IPG]     = imx_clk_hw_gate2("can2_ipg",      "ipg",               base + 0x68, 18);
0800     hws[IMX6QDL_CLK_CAN2_SERIAL]  = imx_clk_hw_gate2("can2_serial",   "can_root",          base + 0x68, 20);
0801     hws[IMX6QDL_CLK_DCIC1]        = imx_clk_hw_gate2("dcic1",         "ipu1_podf",         base + 0x68, 24);
0802     hws[IMX6QDL_CLK_DCIC2]        = imx_clk_hw_gate2("dcic2",         "ipu2_podf",         base + 0x68, 26);
0803     hws[IMX6QDL_CLK_ECSPI1]       = imx_clk_hw_gate2("ecspi1",        "ecspi_root",        base + 0x6c, 0);
0804     hws[IMX6QDL_CLK_ECSPI2]       = imx_clk_hw_gate2("ecspi2",        "ecspi_root",        base + 0x6c, 2);
0805     hws[IMX6QDL_CLK_ECSPI3]       = imx_clk_hw_gate2("ecspi3",        "ecspi_root",        base + 0x6c, 4);
0806     hws[IMX6QDL_CLK_ECSPI4]       = imx_clk_hw_gate2("ecspi4",        "ecspi_root",        base + 0x6c, 6);
0807     if (clk_on_imx6dl())
0808         hws[IMX6DL_CLK_I2C4]  = imx_clk_hw_gate2("i2c4",          "ipg_per",           base + 0x6c, 8);
0809     else
0810         hws[IMX6Q_CLK_ECSPI5] = imx_clk_hw_gate2("ecspi5",        "ecspi_root",        base + 0x6c, 8);
0811     hws[IMX6QDL_CLK_ENET]         = imx_clk_hw_gate2("enet",          "ipg",               base + 0x6c, 10);
0812     hws[IMX6QDL_CLK_EPIT1]        = imx_clk_hw_gate2("epit1",         "ipg",               base + 0x6c, 12);
0813     hws[IMX6QDL_CLK_EPIT2]        = imx_clk_hw_gate2("epit2",         "ipg",               base + 0x6c, 14);
0814     hws[IMX6QDL_CLK_ESAI_EXTAL]   = imx_clk_hw_gate2_shared("esai_extal",   "esai_podf",   base + 0x6c, 16, &share_count_esai);
0815     hws[IMX6QDL_CLK_ESAI_IPG]     = imx_clk_hw_gate2_shared("esai_ipg",   "ahb",           base + 0x6c, 16, &share_count_esai);
0816     hws[IMX6QDL_CLK_ESAI_MEM]     = imx_clk_hw_gate2_shared("esai_mem", "ahb",             base + 0x6c, 16, &share_count_esai);
0817     hws[IMX6QDL_CLK_GPT_IPG]      = imx_clk_hw_gate2("gpt_ipg",       "ipg",               base + 0x6c, 20);
0818     hws[IMX6QDL_CLK_GPT_IPG_PER]  = imx_clk_hw_gate2("gpt_ipg_per",   "ipg_per",           base + 0x6c, 22);
0819     hws[IMX6QDL_CLK_GPU2D_CORE] = imx_clk_hw_gate2("gpu2d_core", "gpu2d_core_podf", base + 0x6c, 24);
0820     hws[IMX6QDL_CLK_GPU3D_CORE]   = imx_clk_hw_gate2("gpu3d_core",    "gpu3d_core_podf",   base + 0x6c, 26);
0821     hws[IMX6QDL_CLK_HDMI_IAHB]    = imx_clk_hw_gate2("hdmi_iahb",     "ahb",               base + 0x70, 0);
0822     hws[IMX6QDL_CLK_HDMI_ISFR]    = imx_clk_hw_gate2("hdmi_isfr",     "mipi_core_cfg",     base + 0x70, 4);
0823     hws[IMX6QDL_CLK_I2C1]         = imx_clk_hw_gate2("i2c1",          "ipg_per",           base + 0x70, 6);
0824     hws[IMX6QDL_CLK_I2C2]         = imx_clk_hw_gate2("i2c2",          "ipg_per",           base + 0x70, 8);
0825     hws[IMX6QDL_CLK_I2C3]         = imx_clk_hw_gate2("i2c3",          "ipg_per",           base + 0x70, 10);
0826     hws[IMX6QDL_CLK_IIM]          = imx_clk_hw_gate2("iim",           "ipg",               base + 0x70, 12);
0827     hws[IMX6QDL_CLK_ENFC]         = imx_clk_hw_gate2("enfc",          "enfc_podf",         base + 0x70, 14);
0828     hws[IMX6QDL_CLK_VDOA]         = imx_clk_hw_gate2("vdoa",          "vdo_axi",           base + 0x70, 26);
0829     hws[IMX6QDL_CLK_IPU1]         = imx_clk_hw_gate2("ipu1",          "ipu1_podf",         base + 0x74, 0);
0830     hws[IMX6QDL_CLK_IPU1_DI0]     = imx_clk_hw_gate2("ipu1_di0",      "ipu1_di0_sel",      base + 0x74, 2);
0831     hws[IMX6QDL_CLK_IPU1_DI1]     = imx_clk_hw_gate2("ipu1_di1",      "ipu1_di1_sel",      base + 0x74, 4);
0832     hws[IMX6QDL_CLK_IPU2]         = imx_clk_hw_gate2("ipu2",          "ipu2_podf",         base + 0x74, 6);
0833     hws[IMX6QDL_CLK_IPU2_DI0]     = imx_clk_hw_gate2("ipu2_di0",      "ipu2_di0_sel",      base + 0x74, 8);
0834     if (clk_on_imx6qp()) {
0835         hws[IMX6QDL_CLK_LDB_DI0]      = imx_clk_hw_gate2("ldb_di0",       "ldb_di0_sel",      base + 0x74, 12);
0836         hws[IMX6QDL_CLK_LDB_DI1]      = imx_clk_hw_gate2("ldb_di1",       "ldb_di1_sel",      base + 0x74, 14);
0837     } else {
0838         hws[IMX6QDL_CLK_LDB_DI0]      = imx_clk_hw_gate2("ldb_di0",       "ldb_di0_podf",      base + 0x74, 12);
0839         hws[IMX6QDL_CLK_LDB_DI1]      = imx_clk_hw_gate2("ldb_di1",       "ldb_di1_podf",      base + 0x74, 14);
0840     }
0841     hws[IMX6QDL_CLK_IPU2_DI1]     = imx_clk_hw_gate2("ipu2_di1",      "ipu2_di1_sel",      base + 0x74, 10);
0842     hws[IMX6QDL_CLK_HSI_TX]       = imx_clk_hw_gate2_shared("hsi_tx", "hsi_tx_podf",       base + 0x74, 16, &share_count_mipi_core_cfg);
0843     hws[IMX6QDL_CLK_MIPI_CORE_CFG] = imx_clk_hw_gate2_shared("mipi_core_cfg", "video_27m", base + 0x74, 16, &share_count_mipi_core_cfg);
0844     hws[IMX6QDL_CLK_MIPI_IPG]     = imx_clk_hw_gate2_shared("mipi_ipg", "ipg",             base + 0x74, 16, &share_count_mipi_core_cfg);
0845 
0846     if (clk_on_imx6dl())
0847         /*
0848          * The multiplexer and divider of the imx6q clock gpu2d get
0849          * redefined/reused as mlb_sys_sel and mlb_sys_clk_podf on imx6dl.
0850          */
0851         hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb",            "mlb_podf",   base + 0x74, 18);
0852     else
0853         hws[IMX6QDL_CLK_MLB] = imx_clk_hw_gate2("mlb",            "axi",               base + 0x74, 18);
0854     hws[IMX6QDL_CLK_MMDC_CH0_AXI] = imx_clk_hw_gate2_flags("mmdc_ch0_axi",  "mmdc_ch0_axi_podf", base + 0x74, 20, CLK_IS_CRITICAL);
0855     hws[IMX6QDL_CLK_MMDC_CH1_AXI] = imx_clk_hw_gate2("mmdc_ch1_axi",  "mmdc_ch1_axi_podf", base + 0x74, 22);
0856     hws[IMX6QDL_CLK_MMDC_P0_IPG]  = imx_clk_hw_gate2_flags("mmdc_p0_ipg",   "ipg",         base + 0x74, 24, CLK_IS_CRITICAL);
0857     hws[IMX6QDL_CLK_OCRAM]        = imx_clk_hw_gate2("ocram",         "ahb",               base + 0x74, 28);
0858     hws[IMX6QDL_CLK_OPENVG_AXI]   = imx_clk_hw_gate2("openvg_axi",    "axi",               base + 0x74, 30);
0859     hws[IMX6QDL_CLK_PCIE_AXI]     = imx_clk_hw_gate2("pcie_axi",      "pcie_axi_sel",      base + 0x78, 0);
0860     hws[IMX6QDL_CLK_PER1_BCH]     = imx_clk_hw_gate2("per1_bch",      "usdhc3",            base + 0x78, 12);
0861     hws[IMX6QDL_CLK_PWM1]         = imx_clk_hw_gate2("pwm1",          "ipg_per",           base + 0x78, 16);
0862     hws[IMX6QDL_CLK_PWM2]         = imx_clk_hw_gate2("pwm2",          "ipg_per",           base + 0x78, 18);
0863     hws[IMX6QDL_CLK_PWM3]         = imx_clk_hw_gate2("pwm3",          "ipg_per",           base + 0x78, 20);
0864     hws[IMX6QDL_CLK_PWM4]         = imx_clk_hw_gate2("pwm4",          "ipg_per",           base + 0x78, 22);
0865     hws[IMX6QDL_CLK_GPMI_BCH_APB] = imx_clk_hw_gate2("gpmi_bch_apb",  "usdhc3",            base + 0x78, 24);
0866     hws[IMX6QDL_CLK_GPMI_BCH]     = imx_clk_hw_gate2("gpmi_bch",      "usdhc4",            base + 0x78, 26);
0867     hws[IMX6QDL_CLK_GPMI_IO]      = imx_clk_hw_gate2("gpmi_io",       "enfc",              base + 0x78, 28);
0868     hws[IMX6QDL_CLK_GPMI_APB]     = imx_clk_hw_gate2("gpmi_apb",      "usdhc3",            base + 0x78, 30);
0869     hws[IMX6QDL_CLK_ROM]          = imx_clk_hw_gate2_flags("rom",     "ahb",               base + 0x7c, 0, CLK_IS_CRITICAL);
0870     hws[IMX6QDL_CLK_SATA]         = imx_clk_hw_gate2("sata",          "ahb",               base + 0x7c, 4);
0871     hws[IMX6QDL_CLK_SDMA]         = imx_clk_hw_gate2("sdma",          "ahb",               base + 0x7c, 6);
0872     hws[IMX6QDL_CLK_SPBA]         = imx_clk_hw_gate2("spba",          "ipg",               base + 0x7c, 12);
0873     hws[IMX6QDL_CLK_SPDIF]        = imx_clk_hw_gate2_shared("spdif",     "spdif_podf",     base + 0x7c, 14, &share_count_spdif);
0874     hws[IMX6QDL_CLK_SPDIF_GCLK]   = imx_clk_hw_gate2_shared("spdif_gclk", "ipg",           base + 0x7c, 14, &share_count_spdif);
0875     hws[IMX6QDL_CLK_SSI1_IPG]     = imx_clk_hw_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
0876     hws[IMX6QDL_CLK_SSI2_IPG]     = imx_clk_hw_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
0877     hws[IMX6QDL_CLK_SSI3_IPG]     = imx_clk_hw_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);
0878     hws[IMX6QDL_CLK_SSI1]         = imx_clk_hw_gate2_shared("ssi1",          "ssi1_podf",  base + 0x7c, 18, &share_count_ssi1);
0879     hws[IMX6QDL_CLK_SSI2]         = imx_clk_hw_gate2_shared("ssi2",          "ssi2_podf",  base + 0x7c, 20, &share_count_ssi2);
0880     hws[IMX6QDL_CLK_SSI3]         = imx_clk_hw_gate2_shared("ssi3",          "ssi3_podf",  base + 0x7c, 22, &share_count_ssi3);
0881     hws[IMX6QDL_CLK_UART_IPG]     = imx_clk_hw_gate2("uart_ipg",      "ipg",               base + 0x7c, 24);
0882     hws[IMX6QDL_CLK_UART_SERIAL]  = imx_clk_hw_gate2("uart_serial",   "uart_serial_podf",  base + 0x7c, 26);
0883     hws[IMX6QDL_CLK_USBOH3]       = imx_clk_hw_gate2("usboh3",        "ipg",               base + 0x80, 0);
0884     hws[IMX6QDL_CLK_USDHC1]       = imx_clk_hw_gate2("usdhc1",        "usdhc1_podf",       base + 0x80, 2);
0885     hws[IMX6QDL_CLK_USDHC2]       = imx_clk_hw_gate2("usdhc2",        "usdhc2_podf",       base + 0x80, 4);
0886     hws[IMX6QDL_CLK_USDHC3]       = imx_clk_hw_gate2("usdhc3",        "usdhc3_podf",       base + 0x80, 6);
0887     hws[IMX6QDL_CLK_USDHC4]       = imx_clk_hw_gate2("usdhc4",        "usdhc4_podf",       base + 0x80, 8);
0888     hws[IMX6QDL_CLK_EIM_SLOW]     = imx_clk_hw_gate2("eim_slow",      "eim_slow_podf",     base + 0x80, 10);
0889     hws[IMX6QDL_CLK_VDO_AXI]      = imx_clk_hw_gate2("vdo_axi",       "vdo_axi_sel",       base + 0x80, 12);
0890     hws[IMX6QDL_CLK_VPU_AXI]      = imx_clk_hw_gate2("vpu_axi",       "vpu_axi_podf",      base + 0x80, 14);
0891     if (clk_on_imx6qp()) {
0892         hws[IMX6QDL_CLK_PRE0] = imx_clk_hw_gate2("pre0",           "pre_axi",       base + 0x80, 16);
0893         hws[IMX6QDL_CLK_PRE1] = imx_clk_hw_gate2("pre1",           "pre_axi",       base + 0x80, 18);
0894         hws[IMX6QDL_CLK_PRE2] = imx_clk_hw_gate2("pre2",           "pre_axi",         base + 0x80, 20);
0895         hws[IMX6QDL_CLK_PRE3] = imx_clk_hw_gate2("pre3",           "pre_axi",       base + 0x80, 22);
0896         hws[IMX6QDL_CLK_PRG0_AXI] = imx_clk_hw_gate2_shared("prg0_axi",  "ipu1_podf",  base + 0x80, 24, &share_count_prg0);
0897         hws[IMX6QDL_CLK_PRG1_AXI] = imx_clk_hw_gate2_shared("prg1_axi",  "ipu2_podf",  base + 0x80, 26, &share_count_prg1);
0898         hws[IMX6QDL_CLK_PRG0_APB] = imx_clk_hw_gate2_shared("prg0_apb",  "ipg",     base + 0x80, 24, &share_count_prg0);
0899         hws[IMX6QDL_CLK_PRG1_APB] = imx_clk_hw_gate2_shared("prg1_apb",  "ipg",     base + 0x80, 26, &share_count_prg1);
0900     }
0901     hws[IMX6QDL_CLK_CKO1]         = imx_clk_hw_gate("cko1",           "cko1_podf",         base + 0x60, 7);
0902     hws[IMX6QDL_CLK_CKO2]         = imx_clk_hw_gate("cko2",           "cko2_podf",         base + 0x60, 24);
0903 
0904     /*
0905      * The gpt_3m clock is not available on i.MX6Q TO1.0.  Let's point it
0906      * to clock gpt_ipg_per to ease the gpt driver code.
0907      */
0908     if (clk_on_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0)
0909         hws[IMX6QDL_CLK_GPT_3M] = hws[IMX6QDL_CLK_GPT_IPG_PER];
0910 
0911     imx_check_clk_hws(hws, IMX6QDL_CLK_END);
0912 
0913     of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
0914 
0915     clk_hw_register_clkdev(hws[IMX6QDL_CLK_ENET_REF], "enet_ref", NULL);
0916 
0917     clk_set_rate(hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk, 540000000);
0918     if (clk_on_imx6dl())
0919         clk_set_parent(hws[IMX6QDL_CLK_IPU1_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD1_540M]->clk);
0920 
0921     clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
0922     clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
0923     clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
0924     clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_PRE_SEL]->clk, hws[IMX6QDL_CLK_PLL5_VIDEO_DIV]->clk);
0925     clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI0_PRE]->clk);
0926     clk_set_parent(hws[IMX6QDL_CLK_IPU1_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU1_DI1_PRE]->clk);
0927     clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI0_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI0_PRE]->clk);
0928     clk_set_parent(hws[IMX6QDL_CLK_IPU2_DI1_SEL]->clk, hws[IMX6QDL_CLK_IPU2_DI1_PRE]->clk);
0929 
0930     /*
0931      * The gpmi needs 100MHz frequency in the EDO/Sync mode,
0932      * We can not get the 100MHz from the pll2_pfd0_352m.
0933      * So choose pll2_pfd2_396m as enfc_sel's parent.
0934      */
0935     clk_set_parent(hws[IMX6QDL_CLK_ENFC_SEL]->clk, hws[IMX6QDL_CLK_PLL2_PFD2_396M]->clk);
0936 
0937     if (IS_ENABLED(CONFIG_USB_MXS_PHY)) {
0938         clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY1_GATE]->clk);
0939         clk_prepare_enable(hws[IMX6QDL_CLK_USBPHY2_GATE]->clk);
0940     }
0941 
0942     /*
0943      * Let's initially set up CLKO with OSC24M, since this configuration
0944      * is widely used by imx6q board designs to clock audio codec.
0945      */
0946     ret = clk_set_parent(hws[IMX6QDL_CLK_CKO2_SEL]->clk, hws[IMX6QDL_CLK_OSC]->clk);
0947     if (!ret)
0948         ret = clk_set_parent(hws[IMX6QDL_CLK_CKO]->clk, hws[IMX6QDL_CLK_CKO2]->clk);
0949     if (ret)
0950         pr_warn("failed to set up CLKO: %d\n", ret);
0951 
0952     /* Audio-related clocks configuration */
0953     clk_set_parent(hws[IMX6QDL_CLK_SPDIF_SEL]->clk, hws[IMX6QDL_CLK_PLL3_PFD3_454M]->clk);
0954 
0955     /* All existing boards with PCIe use LVDS1 */
0956     if (IS_ENABLED(CONFIG_PCI_IMX6))
0957         clk_set_parent(hws[IMX6QDL_CLK_LVDS1_SEL]->clk, hws[IMX6QDL_CLK_SATA_REF_100M]->clk);
0958 
0959     /*
0960      * Initialize the GPU clock muxes, so that the maximum specified clock
0961      * rates for the respective SoC are not exceeded.
0962      */
0963     if (clk_on_imx6dl()) {
0964         clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
0965                    hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
0966         clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
0967                    hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
0968     } else if (clk_on_imx6q()) {
0969         clk_set_parent(hws[IMX6QDL_CLK_GPU3D_CORE_SEL]->clk,
0970                    hws[IMX6QDL_CLK_MMDC_CH0_AXI]->clk);
0971         clk_set_parent(hws[IMX6QDL_CLK_GPU3D_SHADER_SEL]->clk,
0972                    hws[IMX6QDL_CLK_PLL2_PFD1_594M]->clk);
0973         clk_set_parent(hws[IMX6QDL_CLK_GPU2D_CORE_SEL]->clk,
0974                    hws[IMX6QDL_CLK_PLL3_USB_OTG]->clk);
0975     }
0976 
0977     imx_register_uart_clocks(2);
0978 }
0979 CLK_OF_DECLARE(imx6q, "fsl,imx6q-ccm", imx6q_clocks_init);
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