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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
0004  */
0005 #include <linux/mm.h>
0006 #include <linux/delay.h>
0007 #include <linux/clk.h>
0008 #include <linux/io.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/clk-provider.h>
0011 #include <linux/err.h>
0012 #include <linux/of.h>
0013 #include <linux/of_address.h>
0014 #include <linux/of_irq.h>
0015 #include <linux/sizes.h>
0016 #include <soc/imx/revision.h>
0017 #include <dt-bindings/clock/imx5-clock.h>
0018 
0019 #include "clk.h"
0020 
0021 #define MX51_DPLL1_BASE     0x83f80000
0022 #define MX51_DPLL2_BASE     0x83f84000
0023 #define MX51_DPLL3_BASE     0x83f88000
0024 
0025 #define MX53_DPLL1_BASE     0x63f80000
0026 #define MX53_DPLL2_BASE     0x63f84000
0027 #define MX53_DPLL3_BASE     0x63f88000
0028 #define MX53_DPLL4_BASE     0x63f8c000
0029 
0030 #define MXC_CCM_CCR     (ccm_base + 0x00)
0031 #define MXC_CCM_CCDR        (ccm_base + 0x04)
0032 #define MXC_CCM_CSR     (ccm_base + 0x08)
0033 #define MXC_CCM_CCSR        (ccm_base + 0x0c)
0034 #define MXC_CCM_CACRR       (ccm_base + 0x10)
0035 #define MXC_CCM_CBCDR       (ccm_base + 0x14)
0036 #define MXC_CCM_CBCMR       (ccm_base + 0x18)
0037 #define MXC_CCM_CSCMR1      (ccm_base + 0x1c)
0038 #define MXC_CCM_CSCMR2      (ccm_base + 0x20)
0039 #define MXC_CCM_CSCDR1      (ccm_base + 0x24)
0040 #define MXC_CCM_CS1CDR      (ccm_base + 0x28)
0041 #define MXC_CCM_CS2CDR      (ccm_base + 0x2c)
0042 #define MXC_CCM_CDCDR       (ccm_base + 0x30)
0043 #define MXC_CCM_CHSCDR      (ccm_base + 0x34)
0044 #define MXC_CCM_CSCDR2      (ccm_base + 0x38)
0045 #define MXC_CCM_CSCDR3      (ccm_base + 0x3c)
0046 #define MXC_CCM_CSCDR4      (ccm_base + 0x40)
0047 #define MXC_CCM_CWDR        (ccm_base + 0x44)
0048 #define MXC_CCM_CDHIPR      (ccm_base + 0x48)
0049 #define MXC_CCM_CDCR        (ccm_base + 0x4c)
0050 #define MXC_CCM_CTOR        (ccm_base + 0x50)
0051 #define MXC_CCM_CLPCR       (ccm_base + 0x54)
0052 #define MXC_CCM_CISR        (ccm_base + 0x58)
0053 #define MXC_CCM_CIMR        (ccm_base + 0x5c)
0054 #define MXC_CCM_CCOSR       (ccm_base + 0x60)
0055 #define MXC_CCM_CGPR        (ccm_base + 0x64)
0056 #define MXC_CCM_CCGR0       (ccm_base + 0x68)
0057 #define MXC_CCM_CCGR1       (ccm_base + 0x6c)
0058 #define MXC_CCM_CCGR2       (ccm_base + 0x70)
0059 #define MXC_CCM_CCGR3       (ccm_base + 0x74)
0060 #define MXC_CCM_CCGR4       (ccm_base + 0x78)
0061 #define MXC_CCM_CCGR5       (ccm_base + 0x7c)
0062 #define MXC_CCM_CCGR6       (ccm_base + 0x80)
0063 #define MXC_CCM_CCGR7       (ccm_base + 0x84)
0064 
0065 /* Low-power Audio Playback Mode clock */
0066 static const char *lp_apm_sel[] = { "osc", };
0067 
0068 /* This is used multiple times */
0069 static const char *standard_pll_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "lp_apm", };
0070 static const char *periph_apm_sel[] = { "pll1_sw", "pll3_sw", "lp_apm", };
0071 static const char *main_bus_sel[] = { "pll2_sw", "periph_apm", };
0072 static const char *per_lp_apm_sel[] = { "main_bus", "lp_apm", };
0073 static const char *per_root_sel[] = { "per_podf", "ipg", };
0074 static const char *esdhc_c_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
0075 static const char *esdhc_d_sel[] = { "esdhc_a_podf", "esdhc_b_podf", };
0076 static const char *ssi_apm_sels[] = { "ckih1", "lp_amp", "ckih2", };
0077 static const char *ssi_clk_sels[] = { "pll1_sw", "pll2_sw", "pll3_sw", "ssi_apm", };
0078 static const char *ssi3_clk_sels[] = { "ssi1_root_gate", "ssi2_root_gate", };
0079 static const char *ssi_ext1_com_sels[] = { "ssi_ext1_podf", "ssi1_root_gate", };
0080 static const char *ssi_ext2_com_sels[] = { "ssi_ext2_podf", "ssi2_root_gate", };
0081 static const char *emi_slow_sel[] = { "main_bus", "ahb", };
0082 static const char *usb_phy_sel_str[] = { "osc", "usb_phy_podf", };
0083 static const char *mx51_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "tve_di", };
0084 static const char *mx53_ipu_di0_sel[] = { "di_pred", "osc", "ckih1", "di_pll4_podf", "dummy", "ldb_di0_gate", };
0085 static const char *mx53_ldb_di0_sel[] = { "pll3_sw", "pll4_sw", };
0086 static const char *mx51_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", };
0087 static const char *mx53_ipu_di1_sel[] = { "di_pred", "osc", "ckih1", "tve_di", "ipp_di1", "ldb_di1_gate", };
0088 static const char *mx53_ldb_di1_sel[] = { "pll3_sw", "pll4_sw", };
0089 static const char *mx51_tve_ext_sel[] = { "osc", "ckih1", };
0090 static const char *mx53_tve_ext_sel[] = { "pll4_sw", "ckih1", };
0091 static const char *mx51_tve_sel[] = { "tve_pred", "tve_ext_sel", };
0092 static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
0093 static const char *gpu3d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
0094 static const char *gpu2d_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb" };
0095 static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
0096 static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
0097 static const char *mx53_cko1_sel[] = {
0098     "cpu_podf", "pll1_sw", "pll2_sw", "pll3_sw",
0099     "emi_slow_podf", "pll4_sw", "nfc_podf", "dummy",
0100     "di_pred", "dummy", "dummy", "ahb",
0101     "ipg", "per_root", "ckil", "dummy",};
0102 static const char *mx53_cko2_sel[] = {
0103     "dummy"/* dptc_core */, "dummy"/* dptc_perich */,
0104     "dummy", "esdhc_a_podf",
0105     "usboh3_podf", "dummy"/* wrck_clk_root */,
0106     "ecspi_podf", "dummy"/* pll1_ref_clk */,
0107     "esdhc_b_podf", "dummy"/* ddr_clk_root */,
0108     "dummy"/* arm_axi_clk_root */, "dummy"/* usb_phy_out */,
0109     "vpu_sel", "ipu_sel",
0110     "osc", "ckih1",
0111     "dummy", "esdhc_c_sel",
0112     "ssi1_root_podf", "ssi2_root_podf",
0113     "dummy", "dummy",
0114     "dummy"/* lpsr_clk_root */, "dummy"/* pgc_clk_root */,
0115     "dummy"/* tve_out */, "usb_phy_sel",
0116     "tve_sel", "lp_apm",
0117     "uart_root", "dummy"/* spdif0_clk_root */,
0118     "dummy", "dummy", };
0119 static const char *mx51_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", };
0120 static const char *mx53_spdif_xtal_sel[] = { "osc", "ckih", "ckih2", "pll4_sw", };
0121 static const char *spdif_sel[] = { "pll1_sw", "pll2_sw", "pll3_sw", "spdif_xtal_sel", };
0122 static const char *spdif0_com_sel[] = { "spdif0_podf", "ssi1_root_gate", };
0123 static const char *mx51_spdif1_com_sel[] = { "spdif1_podf", "ssi2_root_gate", };
0124 static const char *step_sels[] = { "lp_apm", };
0125 static const char *cpu_podf_sels[] = { "pll1_sw", "step_sel" };
0126 static const char *ieee1588_sels[] = { "pll3_sw", "pll4_sw", "dummy" /* usbphy2_clk */, "dummy" /* fec_phy_clk */ };
0127 
0128 static struct clk *clk[IMX5_CLK_END];
0129 static struct clk_onecell_data clk_data;
0130 
0131 static void __init mx5_clocks_common_init(void __iomem *ccm_base)
0132 {
0133     clk[IMX5_CLK_DUMMY]     = imx_clk_fixed("dummy", 0);
0134     clk[IMX5_CLK_CKIL]      = imx_obtain_fixed_clock("ckil", 0);
0135     clk[IMX5_CLK_OSC]       = imx_obtain_fixed_clock("osc", 0);
0136     clk[IMX5_CLK_CKIH1]     = imx_obtain_fixed_clock("ckih1", 0);
0137     clk[IMX5_CLK_CKIH2]     = imx_obtain_fixed_clock("ckih2", 0);
0138 
0139     clk[IMX5_CLK_PER_LP_APM]    = imx_clk_mux("per_lp_apm", MXC_CCM_CBCMR, 1, 1,
0140                         per_lp_apm_sel, ARRAY_SIZE(per_lp_apm_sel));
0141     clk[IMX5_CLK_PER_PRED1]     = imx_clk_divider("per_pred1", "per_lp_apm", MXC_CCM_CBCDR, 6, 2);
0142     clk[IMX5_CLK_PER_PRED2]     = imx_clk_divider("per_pred2", "per_pred1", MXC_CCM_CBCDR, 3, 3);
0143     clk[IMX5_CLK_PER_PODF]      = imx_clk_divider("per_podf", "per_pred2", MXC_CCM_CBCDR, 0, 3);
0144     clk[IMX5_CLK_PER_ROOT]      = imx_clk_mux("per_root", MXC_CCM_CBCMR, 0, 1,
0145                         per_root_sel, ARRAY_SIZE(per_root_sel));
0146     clk[IMX5_CLK_AHB]       = imx_clk_divider("ahb", "main_bus", MXC_CCM_CBCDR, 10, 3);
0147     clk[IMX5_CLK_AHB_MAX]       = imx_clk_gate2_flags("ahb_max", "ahb", MXC_CCM_CCGR0, 28, CLK_IS_CRITICAL);
0148     clk[IMX5_CLK_AIPS_TZ1]      = imx_clk_gate2_flags("aips_tz1", "ahb", MXC_CCM_CCGR0, 24, CLK_IS_CRITICAL);
0149     clk[IMX5_CLK_AIPS_TZ2]      = imx_clk_gate2_flags("aips_tz2", "ahb", MXC_CCM_CCGR0, 26, CLK_IS_CRITICAL);
0150     clk[IMX5_CLK_TMAX1]     = imx_clk_gate2_flags("tmax1", "ahb", MXC_CCM_CCGR1, 0, CLK_IS_CRITICAL);
0151     clk[IMX5_CLK_TMAX2]     = imx_clk_gate2_flags("tmax2", "ahb", MXC_CCM_CCGR1, 2, CLK_IS_CRITICAL);
0152     clk[IMX5_CLK_TMAX3]     = imx_clk_gate2_flags("tmax3", "ahb", MXC_CCM_CCGR1, 4, CLK_IS_CRITICAL);
0153     clk[IMX5_CLK_SPBA]      = imx_clk_gate2_flags("spba", "ipg", MXC_CCM_CCGR5, 0, CLK_IS_CRITICAL);
0154     clk[IMX5_CLK_IPG]       = imx_clk_divider("ipg", "ahb", MXC_CCM_CBCDR, 8, 2);
0155     clk[IMX5_CLK_AXI_A]     = imx_clk_divider("axi_a", "main_bus", MXC_CCM_CBCDR, 16, 3);
0156     clk[IMX5_CLK_AXI_B]     = imx_clk_divider("axi_b", "main_bus", MXC_CCM_CBCDR, 19, 3);
0157     clk[IMX5_CLK_UART_SEL]      = imx_clk_mux("uart_sel", MXC_CCM_CSCMR1, 24, 2,
0158                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0159     clk[IMX5_CLK_UART_PRED]     = imx_clk_divider("uart_pred", "uart_sel", MXC_CCM_CSCDR1, 3, 3);
0160     clk[IMX5_CLK_UART_ROOT]     = imx_clk_divider("uart_root", "uart_pred", MXC_CCM_CSCDR1, 0, 3);
0161 
0162     clk[IMX5_CLK_ESDHC_A_PRED]  = imx_clk_divider("esdhc_a_pred", "esdhc_a_sel", MXC_CCM_CSCDR1, 16, 3);
0163     clk[IMX5_CLK_ESDHC_A_PODF]  = imx_clk_divider("esdhc_a_podf", "esdhc_a_pred", MXC_CCM_CSCDR1, 11, 3);
0164     clk[IMX5_CLK_ESDHC_B_PRED]  = imx_clk_divider("esdhc_b_pred", "esdhc_b_sel", MXC_CCM_CSCDR1, 22, 3);
0165     clk[IMX5_CLK_ESDHC_B_PODF]  = imx_clk_divider("esdhc_b_podf", "esdhc_b_pred", MXC_CCM_CSCDR1, 19, 3);
0166 
0167     clk[IMX5_CLK_EMI_SEL]       = imx_clk_mux("emi_sel", MXC_CCM_CBCDR, 26, 1,
0168                         emi_slow_sel, ARRAY_SIZE(emi_slow_sel));
0169     clk[IMX5_CLK_EMI_SLOW_PODF] = imx_clk_divider("emi_slow_podf", "emi_sel", MXC_CCM_CBCDR, 22, 3);
0170     clk[IMX5_CLK_NFC_PODF]      = imx_clk_divider("nfc_podf", "emi_slow_podf", MXC_CCM_CBCDR, 13, 3);
0171     clk[IMX5_CLK_ECSPI_SEL]     = imx_clk_mux("ecspi_sel", MXC_CCM_CSCMR1, 4, 2,
0172                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0173     clk[IMX5_CLK_ECSPI_PRED]    = imx_clk_divider("ecspi_pred", "ecspi_sel", MXC_CCM_CSCDR2, 25, 3);
0174     clk[IMX5_CLK_ECSPI_PODF]    = imx_clk_divider("ecspi_podf", "ecspi_pred", MXC_CCM_CSCDR2, 19, 6);
0175     clk[IMX5_CLK_USBOH3_SEL]    = imx_clk_mux("usboh3_sel", MXC_CCM_CSCMR1, 22, 2,
0176                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0177     clk[IMX5_CLK_USBOH3_PRED]   = imx_clk_divider("usboh3_pred", "usboh3_sel", MXC_CCM_CSCDR1, 8, 3);
0178     clk[IMX5_CLK_USBOH3_PODF]   = imx_clk_divider("usboh3_podf", "usboh3_pred", MXC_CCM_CSCDR1, 6, 2);
0179     clk[IMX5_CLK_USB_PHY_PRED]  = imx_clk_divider("usb_phy_pred", "pll3_sw", MXC_CCM_CDCDR, 3, 3);
0180     clk[IMX5_CLK_USB_PHY_PODF]  = imx_clk_divider("usb_phy_podf", "usb_phy_pred", MXC_CCM_CDCDR, 0, 3);
0181     clk[IMX5_CLK_USB_PHY_SEL]   = imx_clk_mux("usb_phy_sel", MXC_CCM_CSCMR1, 26, 1,
0182                         usb_phy_sel_str, ARRAY_SIZE(usb_phy_sel_str));
0183     clk[IMX5_CLK_STEP_SEL]      = imx_clk_mux("step_sel", MXC_CCM_CCSR, 7, 2, step_sels, ARRAY_SIZE(step_sels));
0184     clk[IMX5_CLK_CPU_PODF_SEL]  = imx_clk_mux("cpu_podf_sel", MXC_CCM_CCSR, 2, 1, cpu_podf_sels, ARRAY_SIZE(cpu_podf_sels));
0185     clk[IMX5_CLK_CPU_PODF]      = imx_clk_divider("cpu_podf", "cpu_podf_sel", MXC_CCM_CACRR, 0, 3);
0186     clk[IMX5_CLK_DI_PRED]       = imx_clk_divider("di_pred", "pll3_sw", MXC_CCM_CDCDR, 6, 3);
0187     clk[IMX5_CLK_IIM_GATE]      = imx_clk_gate2("iim_gate", "ipg", MXC_CCM_CCGR0, 30);
0188     clk[IMX5_CLK_UART1_IPG_GATE]    = imx_clk_gate2("uart1_ipg_gate", "ipg", MXC_CCM_CCGR1, 6);
0189     clk[IMX5_CLK_UART1_PER_GATE]    = imx_clk_gate2("uart1_per_gate", "uart_root", MXC_CCM_CCGR1, 8);
0190     clk[IMX5_CLK_UART2_IPG_GATE]    = imx_clk_gate2("uart2_ipg_gate", "ipg", MXC_CCM_CCGR1, 10);
0191     clk[IMX5_CLK_UART2_PER_GATE]    = imx_clk_gate2("uart2_per_gate", "uart_root", MXC_CCM_CCGR1, 12);
0192     clk[IMX5_CLK_UART3_IPG_GATE]    = imx_clk_gate2("uart3_ipg_gate", "ipg", MXC_CCM_CCGR1, 14);
0193     clk[IMX5_CLK_UART3_PER_GATE]    = imx_clk_gate2("uart3_per_gate", "uart_root", MXC_CCM_CCGR1, 16);
0194     clk[IMX5_CLK_I2C1_GATE]     = imx_clk_gate2("i2c1_gate", "per_root", MXC_CCM_CCGR1, 18);
0195     clk[IMX5_CLK_I2C2_GATE]     = imx_clk_gate2("i2c2_gate", "per_root", MXC_CCM_CCGR1, 20);
0196     clk[IMX5_CLK_PWM1_IPG_GATE] = imx_clk_gate2("pwm1_ipg_gate", "ipg", MXC_CCM_CCGR2, 10);
0197     clk[IMX5_CLK_PWM1_HF_GATE]  = imx_clk_gate2("pwm1_hf_gate", "per_root", MXC_CCM_CCGR2, 12);
0198     clk[IMX5_CLK_PWM2_IPG_GATE] = imx_clk_gate2("pwm2_ipg_gate", "ipg", MXC_CCM_CCGR2, 14);
0199     clk[IMX5_CLK_PWM2_HF_GATE]  = imx_clk_gate2("pwm2_hf_gate", "per_root", MXC_CCM_CCGR2, 16);
0200     clk[IMX5_CLK_GPT_IPG_GATE]  = imx_clk_gate2("gpt_ipg_gate", "ipg", MXC_CCM_CCGR2, 18);
0201     clk[IMX5_CLK_GPT_HF_GATE]   = imx_clk_gate2("gpt_hf_gate", "per_root", MXC_CCM_CCGR2, 20);
0202     clk[IMX5_CLK_FEC_GATE]      = imx_clk_gate2("fec_gate", "ipg", MXC_CCM_CCGR2, 24);
0203     clk[IMX5_CLK_USBOH3_GATE]   = imx_clk_gate2("usboh3_gate", "ipg", MXC_CCM_CCGR2, 26);
0204     clk[IMX5_CLK_USBOH3_PER_GATE]   = imx_clk_gate2("usboh3_per_gate", "usboh3_podf", MXC_CCM_CCGR2, 28);
0205     clk[IMX5_CLK_ESDHC1_IPG_GATE]   = imx_clk_gate2("esdhc1_ipg_gate", "ipg", MXC_CCM_CCGR3, 0);
0206     clk[IMX5_CLK_ESDHC2_IPG_GATE]   = imx_clk_gate2("esdhc2_ipg_gate", "ipg", MXC_CCM_CCGR3, 4);
0207     clk[IMX5_CLK_ESDHC3_IPG_GATE]   = imx_clk_gate2("esdhc3_ipg_gate", "ipg", MXC_CCM_CCGR3, 8);
0208     clk[IMX5_CLK_ESDHC4_IPG_GATE]   = imx_clk_gate2("esdhc4_ipg_gate", "ipg", MXC_CCM_CCGR3, 12);
0209     clk[IMX5_CLK_SSI1_IPG_GATE] = imx_clk_gate2("ssi1_ipg_gate", "ipg", MXC_CCM_CCGR3, 16);
0210     clk[IMX5_CLK_SSI2_IPG_GATE] = imx_clk_gate2("ssi2_ipg_gate", "ipg", MXC_CCM_CCGR3, 20);
0211     clk[IMX5_CLK_SSI3_IPG_GATE] = imx_clk_gate2("ssi3_ipg_gate", "ipg", MXC_CCM_CCGR3, 24);
0212     clk[IMX5_CLK_ECSPI1_IPG_GATE]   = imx_clk_gate2("ecspi1_ipg_gate", "ipg", MXC_CCM_CCGR4, 18);
0213     clk[IMX5_CLK_ECSPI1_PER_GATE]   = imx_clk_gate2("ecspi1_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 20);
0214     clk[IMX5_CLK_ECSPI2_IPG_GATE]   = imx_clk_gate2("ecspi2_ipg_gate", "ipg", MXC_CCM_CCGR4, 22);
0215     clk[IMX5_CLK_ECSPI2_PER_GATE]   = imx_clk_gate2("ecspi2_per_gate", "ecspi_podf", MXC_CCM_CCGR4, 24);
0216     clk[IMX5_CLK_CSPI_IPG_GATE] = imx_clk_gate2("cspi_ipg_gate", "ipg", MXC_CCM_CCGR4, 26);
0217     clk[IMX5_CLK_SDMA_GATE]     = imx_clk_gate2("sdma_gate", "ipg", MXC_CCM_CCGR4, 30);
0218     clk[IMX5_CLK_EMI_FAST_GATE] = imx_clk_gate2_flags("emi_fast_gate", "dummy", MXC_CCM_CCGR5, 14, CLK_IS_CRITICAL);
0219     clk[IMX5_CLK_EMI_SLOW_GATE] = imx_clk_gate2_flags("emi_slow_gate", "emi_slow_podf", MXC_CCM_CCGR5, 16, CLK_IS_CRITICAL);
0220     clk[IMX5_CLK_IPU_SEL]       = imx_clk_mux("ipu_sel", MXC_CCM_CBCMR, 6, 2, ipu_sel, ARRAY_SIZE(ipu_sel));
0221     clk[IMX5_CLK_IPU_GATE]      = imx_clk_gate2("ipu_gate", "ipu_sel", MXC_CCM_CCGR5, 10);
0222     clk[IMX5_CLK_NFC_GATE]      = imx_clk_gate2("nfc_gate", "nfc_podf", MXC_CCM_CCGR5, 20);
0223     clk[IMX5_CLK_IPU_DI0_GATE]  = imx_clk_gate2("ipu_di0_gate", "ipu_di0_sel", MXC_CCM_CCGR6, 10);
0224     clk[IMX5_CLK_IPU_DI1_GATE]  = imx_clk_gate2("ipu_di1_gate", "ipu_di1_sel", MXC_CCM_CCGR6, 12);
0225     clk[IMX5_CLK_GPU3D_SEL]     = imx_clk_mux("gpu3d_sel", MXC_CCM_CBCMR, 4, 2, gpu3d_sel, ARRAY_SIZE(gpu3d_sel));
0226     clk[IMX5_CLK_GPU2D_SEL]     = imx_clk_mux("gpu2d_sel", MXC_CCM_CBCMR, 16, 2, gpu2d_sel, ARRAY_SIZE(gpu2d_sel));
0227     clk[IMX5_CLK_GPU3D_GATE]    = imx_clk_gate2("gpu3d_gate", "gpu3d_sel", MXC_CCM_CCGR5, 2);
0228     clk[IMX5_CLK_GARB_GATE]     = imx_clk_gate2("garb_gate", "axi_a", MXC_CCM_CCGR5, 4);
0229     clk[IMX5_CLK_GPU2D_GATE]    = imx_clk_gate2("gpu2d_gate", "gpu2d_sel", MXC_CCM_CCGR6, 14);
0230     clk[IMX5_CLK_VPU_SEL]       = imx_clk_mux("vpu_sel", MXC_CCM_CBCMR, 14, 2, vpu_sel, ARRAY_SIZE(vpu_sel));
0231     clk[IMX5_CLK_VPU_GATE]      = imx_clk_gate2("vpu_gate", "vpu_sel", MXC_CCM_CCGR5, 6);
0232     clk[IMX5_CLK_VPU_REFERENCE_GATE] = imx_clk_gate2("vpu_reference_gate", "osc", MXC_CCM_CCGR5, 8);
0233     clk[IMX5_CLK_GPC_DVFS]      = imx_clk_gate2_flags("gpc_dvfs", "dummy", MXC_CCM_CCGR5, 24, CLK_IS_CRITICAL);
0234 
0235     clk[IMX5_CLK_SSI_APM]       = imx_clk_mux("ssi_apm", MXC_CCM_CSCMR1, 8, 2, ssi_apm_sels, ARRAY_SIZE(ssi_apm_sels));
0236     clk[IMX5_CLK_SSI1_ROOT_SEL] = imx_clk_mux("ssi1_root_sel", MXC_CCM_CSCMR1, 14, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
0237     clk[IMX5_CLK_SSI2_ROOT_SEL] = imx_clk_mux("ssi2_root_sel", MXC_CCM_CSCMR1, 12, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
0238     clk[IMX5_CLK_SSI3_ROOT_SEL] = imx_clk_mux("ssi3_root_sel", MXC_CCM_CSCMR1, 11, 1, ssi3_clk_sels, ARRAY_SIZE(ssi3_clk_sels));
0239     clk[IMX5_CLK_SSI_EXT1_SEL]  = imx_clk_mux("ssi_ext1_sel", MXC_CCM_CSCMR1, 28, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
0240     clk[IMX5_CLK_SSI_EXT2_SEL]  = imx_clk_mux("ssi_ext2_sel", MXC_CCM_CSCMR1, 30, 2, ssi_clk_sels, ARRAY_SIZE(ssi_clk_sels));
0241     clk[IMX5_CLK_SSI_EXT1_COM_SEL]  = imx_clk_mux("ssi_ext1_com_sel", MXC_CCM_CSCMR1, 0, 1, ssi_ext1_com_sels, ARRAY_SIZE(ssi_ext1_com_sels));
0242     clk[IMX5_CLK_SSI_EXT2_COM_SEL]  = imx_clk_mux("ssi_ext2_com_sel", MXC_CCM_CSCMR1, 1, 1, ssi_ext2_com_sels, ARRAY_SIZE(ssi_ext2_com_sels));
0243     clk[IMX5_CLK_SSI1_ROOT_PRED]    = imx_clk_divider("ssi1_root_pred", "ssi1_root_sel", MXC_CCM_CS1CDR, 6, 3);
0244     clk[IMX5_CLK_SSI1_ROOT_PODF]    = imx_clk_divider("ssi1_root_podf", "ssi1_root_pred", MXC_CCM_CS1CDR, 0, 6);
0245     clk[IMX5_CLK_SSI2_ROOT_PRED]    = imx_clk_divider("ssi2_root_pred", "ssi2_root_sel", MXC_CCM_CS2CDR, 6, 3);
0246     clk[IMX5_CLK_SSI2_ROOT_PODF]    = imx_clk_divider("ssi2_root_podf", "ssi2_root_pred", MXC_CCM_CS2CDR, 0, 6);
0247     clk[IMX5_CLK_SSI_EXT1_PRED] = imx_clk_divider("ssi_ext1_pred", "ssi_ext1_sel", MXC_CCM_CS1CDR, 22, 3);
0248     clk[IMX5_CLK_SSI_EXT1_PODF] = imx_clk_divider("ssi_ext1_podf", "ssi_ext1_pred", MXC_CCM_CS1CDR, 16, 6);
0249     clk[IMX5_CLK_SSI_EXT2_PRED] = imx_clk_divider("ssi_ext2_pred", "ssi_ext2_sel", MXC_CCM_CS2CDR, 22, 3);
0250     clk[IMX5_CLK_SSI_EXT2_PODF] = imx_clk_divider("ssi_ext2_podf", "ssi_ext2_pred", MXC_CCM_CS2CDR, 16, 6);
0251     clk[IMX5_CLK_SSI1_ROOT_GATE]    = imx_clk_gate2("ssi1_root_gate", "ssi1_root_podf", MXC_CCM_CCGR3, 18);
0252     clk[IMX5_CLK_SSI2_ROOT_GATE]    = imx_clk_gate2("ssi2_root_gate", "ssi2_root_podf", MXC_CCM_CCGR3, 22);
0253     clk[IMX5_CLK_SSI3_ROOT_GATE]    = imx_clk_gate2("ssi3_root_gate", "ssi3_root_sel", MXC_CCM_CCGR3, 26);
0254     clk[IMX5_CLK_SSI_EXT1_GATE] = imx_clk_gate2("ssi_ext1_gate", "ssi_ext1_com_sel", MXC_CCM_CCGR3, 28);
0255     clk[IMX5_CLK_SSI_EXT2_GATE] = imx_clk_gate2("ssi_ext2_gate", "ssi_ext2_com_sel", MXC_CCM_CCGR3, 30);
0256     clk[IMX5_CLK_EPIT1_IPG_GATE]    = imx_clk_gate2("epit1_ipg_gate", "ipg", MXC_CCM_CCGR2, 2);
0257     clk[IMX5_CLK_EPIT1_HF_GATE] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4);
0258     clk[IMX5_CLK_EPIT2_IPG_GATE]    = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6);
0259     clk[IMX5_CLK_EPIT2_HF_GATE] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8);
0260     clk[IMX5_CLK_OWIRE_GATE]    = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22);
0261     clk[IMX5_CLK_SRTC_GATE]     = imx_clk_gate2("srtc_gate", "per_root", MXC_CCM_CCGR4, 28);
0262     clk[IMX5_CLK_PATA_GATE]     = imx_clk_gate2("pata_gate", "ipg", MXC_CCM_CCGR4, 0);
0263     clk[IMX5_CLK_SPDIF0_SEL]    = imx_clk_mux("spdif0_sel", MXC_CCM_CSCMR2, 0, 2, spdif_sel, ARRAY_SIZE(spdif_sel));
0264     clk[IMX5_CLK_SPDIF0_PRED]   = imx_clk_divider("spdif0_pred", "spdif0_sel", MXC_CCM_CDCDR, 25, 3);
0265     clk[IMX5_CLK_SPDIF0_PODF]   = imx_clk_divider("spdif0_podf", "spdif0_pred", MXC_CCM_CDCDR, 19, 6);
0266     clk[IMX5_CLK_SPDIF0_COM_SEL]    = imx_clk_mux_flags("spdif0_com_sel", MXC_CCM_CSCMR2, 4, 1,
0267                         spdif0_com_sel, ARRAY_SIZE(spdif0_com_sel), CLK_SET_RATE_PARENT);
0268     clk[IMX5_CLK_SPDIF0_GATE]   = imx_clk_gate2("spdif0_gate", "spdif0_com_sel", MXC_CCM_CCGR5, 26);
0269     clk[IMX5_CLK_SPDIF_IPG_GATE]    = imx_clk_gate2("spdif_ipg_gate", "ipg", MXC_CCM_CCGR5, 30);
0270     clk[IMX5_CLK_SAHARA_IPG_GATE]   = imx_clk_gate2("sahara_ipg_gate", "ipg", MXC_CCM_CCGR4, 14);
0271     clk[IMX5_CLK_SATA_REF]      = imx_clk_fixed_factor("sata_ref", "usb_phy1_gate", 1, 1);
0272 
0273     clk_register_clkdev(clk[IMX5_CLK_CPU_PODF], NULL, "cpu0");
0274     clk_register_clkdev(clk[IMX5_CLK_GPC_DVFS], "gpc_dvfs", NULL);
0275 
0276     /* move usb phy clk to 24MHz */
0277     clk_set_parent(clk[IMX5_CLK_USB_PHY_SEL], clk[IMX5_CLK_OSC]);
0278 }
0279 
0280 static void __init mx50_clocks_init(struct device_node *np)
0281 {
0282     void __iomem *ccm_base;
0283     void __iomem *pll_base;
0284     unsigned long r;
0285 
0286     pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
0287     WARN_ON(!pll_base);
0288     clk[IMX5_CLK_PLL1_SW]       = imx_clk_pllv2("pll1_sw", "osc", pll_base);
0289 
0290     pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
0291     WARN_ON(!pll_base);
0292     clk[IMX5_CLK_PLL2_SW]       = imx_clk_pllv2("pll2_sw", "osc", pll_base);
0293 
0294     pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
0295     WARN_ON(!pll_base);
0296     clk[IMX5_CLK_PLL3_SW]       = imx_clk_pllv2("pll3_sw", "osc", pll_base);
0297 
0298     ccm_base = of_iomap(np, 0);
0299     WARN_ON(!ccm_base);
0300 
0301     mx5_clocks_common_init(ccm_base);
0302 
0303     /*
0304      * This clock is called periph_clk in the i.MX50 Reference Manual, but
0305      * it comes closest in scope to the main_bus_clk of i.MX51 and i.MX53
0306      */
0307     clk[IMX5_CLK_MAIN_BUS]          = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 2,
0308                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0309 
0310     clk[IMX5_CLK_LP_APM]        = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
0311                         lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
0312     clk[IMX5_CLK_ESDHC_A_SEL]   = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 21, 2,
0313                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0314     clk[IMX5_CLK_ESDHC_B_SEL]   = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
0315                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0316     clk[IMX5_CLK_ESDHC_C_SEL]   = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 20, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
0317     clk[IMX5_CLK_ESDHC_D_SEL]   = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
0318     clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
0319     clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
0320     clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
0321     clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
0322     clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
0323     clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
0324     clk[IMX5_CLK_I2C3_GATE]     = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
0325     clk[IMX5_CLK_UART4_IPG_GATE]    = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
0326     clk[IMX5_CLK_UART4_PER_GATE]    = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
0327     clk[IMX5_CLK_UART5_IPG_GATE]    = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
0328     clk[IMX5_CLK_UART5_PER_GATE]    = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
0329 
0330     clk[IMX5_CLK_CKO1_SEL]      = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
0331                         mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
0332     clk[IMX5_CLK_CKO1_PODF]     = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
0333     clk[IMX5_CLK_CKO1]      = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
0334 
0335     clk[IMX5_CLK_CKO2_SEL]      = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
0336                         mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
0337     clk[IMX5_CLK_CKO2_PODF]     = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
0338     clk[IMX5_CLK_CKO2]      = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
0339 
0340     imx_check_clocks(clk, ARRAY_SIZE(clk));
0341 
0342     clk_data.clks = clk;
0343     clk_data.clk_num = ARRAY_SIZE(clk);
0344     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0345 
0346     /* Set SDHC parents to be PLL2 */
0347     clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
0348     clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
0349 
0350     /* set SDHC root clock to 200MHZ*/
0351     clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
0352     clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
0353 
0354     clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
0355     imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);
0356     clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
0357 
0358     r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
0359     clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
0360 
0361     imx_register_uart_clocks(5);
0362 }
0363 CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);
0364 
0365 static void __init mx51_clocks_init(struct device_node *np)
0366 {
0367     void __iomem *ccm_base;
0368     void __iomem *pll_base;
0369     u32 val;
0370 
0371     pll_base = ioremap(MX51_DPLL1_BASE, SZ_16K);
0372     WARN_ON(!pll_base);
0373     clk[IMX5_CLK_PLL1_SW]       = imx_clk_pllv2("pll1_sw", "osc", pll_base);
0374 
0375     pll_base = ioremap(MX51_DPLL2_BASE, SZ_16K);
0376     WARN_ON(!pll_base);
0377     clk[IMX5_CLK_PLL2_SW]       = imx_clk_pllv2("pll2_sw", "osc", pll_base);
0378 
0379     pll_base = ioremap(MX51_DPLL3_BASE, SZ_16K);
0380     WARN_ON(!pll_base);
0381     clk[IMX5_CLK_PLL3_SW]       = imx_clk_pllv2("pll3_sw", "osc", pll_base);
0382 
0383     ccm_base = of_iomap(np, 0);
0384     WARN_ON(!ccm_base);
0385 
0386     mx5_clocks_common_init(ccm_base);
0387 
0388     clk[IMX5_CLK_PERIPH_APM]    = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
0389                         periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
0390     clk[IMX5_CLK_MAIN_BUS]      = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
0391                         main_bus_sel, ARRAY_SIZE(main_bus_sel));
0392     clk[IMX5_CLK_LP_APM]        = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 9, 1,
0393                         lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
0394     clk[IMX5_CLK_IPU_DI0_SEL]   = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
0395                         mx51_ipu_di0_sel, ARRAY_SIZE(mx51_ipu_di0_sel), CLK_SET_RATE_PARENT);
0396     clk[IMX5_CLK_IPU_DI1_SEL]   = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
0397                         mx51_ipu_di1_sel, ARRAY_SIZE(mx51_ipu_di1_sel), CLK_SET_RATE_PARENT);
0398     clk[IMX5_CLK_TVE_EXT_SEL]   = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
0399                         mx51_tve_ext_sel, ARRAY_SIZE(mx51_tve_ext_sel), CLK_SET_RATE_PARENT);
0400     clk[IMX5_CLK_TVE_SEL]       = imx_clk_mux("tve_sel", MXC_CCM_CSCMR1, 7, 1,
0401                         mx51_tve_sel, ARRAY_SIZE(mx51_tve_sel));
0402     clk[IMX5_CLK_TVE_GATE]      = imx_clk_gate2("tve_gate", "tve_sel", MXC_CCM_CCGR2, 30);
0403     clk[IMX5_CLK_TVE_PRED]      = imx_clk_divider("tve_pred", "pll3_sw", MXC_CCM_CDCDR, 28, 3);
0404     clk[IMX5_CLK_ESDHC_A_SEL]   = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
0405                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0406     clk[IMX5_CLK_ESDHC_B_SEL]   = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
0407                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0408     clk[IMX5_CLK_ESDHC_C_SEL]   = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
0409     clk[IMX5_CLK_ESDHC_D_SEL]   = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
0410     clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
0411     clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 6);
0412     clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 10);
0413     clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
0414     clk[IMX5_CLK_USB_PHY_GATE]  = imx_clk_gate2("usb_phy_gate", "usb_phy_sel", MXC_CCM_CCGR2, 0);
0415     clk[IMX5_CLK_HSI2C_GATE]    = imx_clk_gate2("hsi2c_gate", "ipg", MXC_CCM_CCGR1, 22);
0416     clk[IMX5_CLK_SCC2_IPG_GATE] = imx_clk_gate2("scc2_gate", "ipg", MXC_CCM_CCGR1, 30);
0417     clk[IMX5_CLK_MIPI_HSC1_GATE]    = imx_clk_gate2_flags("mipi_hsc1_gate", "ipg", MXC_CCM_CCGR4, 6, CLK_IS_CRITICAL);
0418     clk[IMX5_CLK_MIPI_HSC2_GATE]    = imx_clk_gate2_flags("mipi_hsc2_gate", "ipg", MXC_CCM_CCGR4, 8, CLK_IS_CRITICAL);
0419     clk[IMX5_CLK_MIPI_ESC_GATE] = imx_clk_gate2_flags("mipi_esc_gate", "ipg", MXC_CCM_CCGR4, 10, CLK_IS_CRITICAL);
0420     clk[IMX5_CLK_MIPI_HSP_GATE] = imx_clk_gate2_flags("mipi_hsp_gate", "ipg", MXC_CCM_CCGR4, 12, CLK_IS_CRITICAL);
0421     clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
0422                         mx51_spdif_xtal_sel, ARRAY_SIZE(mx51_spdif_xtal_sel));
0423     clk[IMX5_CLK_SPDIF1_SEL]    = imx_clk_mux("spdif1_sel", MXC_CCM_CSCMR2, 2, 2,
0424                         spdif_sel, ARRAY_SIZE(spdif_sel));
0425     clk[IMX5_CLK_SPDIF1_PRED]   = imx_clk_divider("spdif1_pred", "spdif1_sel", MXC_CCM_CDCDR, 16, 3);
0426     clk[IMX5_CLK_SPDIF1_PODF]   = imx_clk_divider("spdif1_podf", "spdif1_pred", MXC_CCM_CDCDR, 9, 6);
0427     clk[IMX5_CLK_SPDIF1_COM_SEL]    = imx_clk_mux("spdif1_com_sel", MXC_CCM_CSCMR2, 5, 1,
0428                         mx51_spdif1_com_sel, ARRAY_SIZE(mx51_spdif1_com_sel));
0429     clk[IMX5_CLK_SPDIF1_GATE]   = imx_clk_gate2("spdif1_gate", "spdif1_com_sel", MXC_CCM_CCGR5, 28);
0430 
0431     imx_check_clocks(clk, ARRAY_SIZE(clk));
0432 
0433     clk_data.clks = clk;
0434     clk_data.clk_num = ARRAY_SIZE(clk);
0435     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0436 
0437     /* set the usboh3 parent to pll2_sw */
0438     clk_set_parent(clk[IMX5_CLK_USBOH3_SEL], clk[IMX5_CLK_PLL2_SW]);
0439 
0440     /* Set SDHC parents to be PLL2 */
0441     clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
0442     clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
0443 
0444     /* set SDHC root clock to 166.25MHZ*/
0445     clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 166250000);
0446     clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 166250000);
0447 
0448     clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
0449     imx_print_silicon_rev("i.MX51", mx51_revision());
0450     clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
0451 
0452     /*
0453      * Reference Manual says: Functionality of CCDR[18] and CLPCR[23] is no
0454      * longer supported. Set to one for better power saving.
0455      *
0456      * The effect of not setting these bits is that MIPI clocks can't be
0457      * enabled without the IPU clock being enabled aswell.
0458      */
0459     val = readl(MXC_CCM_CCDR);
0460     val |= 1 << 18;
0461     writel(val, MXC_CCM_CCDR);
0462 
0463     val = readl(MXC_CCM_CLPCR);
0464     val |= 1 << 23;
0465     writel(val, MXC_CCM_CLPCR);
0466 
0467     imx_register_uart_clocks(3);
0468 }
0469 CLK_OF_DECLARE(imx51_ccm, "fsl,imx51-ccm", mx51_clocks_init);
0470 
0471 static void __init mx53_clocks_init(struct device_node *np)
0472 {
0473     void __iomem *ccm_base;
0474     void __iomem *pll_base;
0475     unsigned long r;
0476 
0477     pll_base = ioremap(MX53_DPLL1_BASE, SZ_16K);
0478     WARN_ON(!pll_base);
0479     clk[IMX5_CLK_PLL1_SW]       = imx_clk_pllv2("pll1_sw", "osc", pll_base);
0480 
0481     pll_base = ioremap(MX53_DPLL2_BASE, SZ_16K);
0482     WARN_ON(!pll_base);
0483     clk[IMX5_CLK_PLL2_SW]       = imx_clk_pllv2("pll2_sw", "osc", pll_base);
0484 
0485     pll_base = ioremap(MX53_DPLL3_BASE, SZ_16K);
0486     WARN_ON(!pll_base);
0487     clk[IMX5_CLK_PLL3_SW]       = imx_clk_pllv2("pll3_sw", "osc", pll_base);
0488 
0489     pll_base = ioremap(MX53_DPLL4_BASE, SZ_16K);
0490     WARN_ON(!pll_base);
0491     clk[IMX5_CLK_PLL4_SW]       = imx_clk_pllv2("pll4_sw", "osc", pll_base);
0492 
0493     ccm_base = of_iomap(np, 0);
0494     WARN_ON(!ccm_base);
0495 
0496     mx5_clocks_common_init(ccm_base);
0497 
0498     clk[IMX5_CLK_PERIPH_APM]    = imx_clk_mux("periph_apm", MXC_CCM_CBCMR, 12, 2,
0499                         periph_apm_sel, ARRAY_SIZE(periph_apm_sel));
0500     clk[IMX5_CLK_MAIN_BUS]      = imx_clk_mux("main_bus", MXC_CCM_CBCDR, 25, 1,
0501                         main_bus_sel, ARRAY_SIZE(main_bus_sel));
0502     clk[IMX5_CLK_LP_APM]        = imx_clk_mux("lp_apm", MXC_CCM_CCSR, 10, 1,
0503                         lp_apm_sel, ARRAY_SIZE(lp_apm_sel));
0504     clk[IMX5_CLK_LDB_DI1_DIV_3_5]   = imx_clk_fixed_factor("ldb_di1_div_3_5", "ldb_di1_sel", 2, 7);
0505     clk[IMX5_CLK_LDB_DI1_DIV]   = imx_clk_divider_flags("ldb_di1_div", "ldb_di1_div_3_5", MXC_CCM_CSCMR2, 11, 1, 0);
0506     clk[IMX5_CLK_LDB_DI1_SEL]   = imx_clk_mux_flags("ldb_di1_sel", MXC_CCM_CSCMR2, 9, 1,
0507                         mx53_ldb_di1_sel, ARRAY_SIZE(mx53_ldb_di1_sel), CLK_SET_RATE_PARENT);
0508     clk[IMX5_CLK_DI_PLL4_PODF]  = imx_clk_divider("di_pll4_podf", "pll4_sw", MXC_CCM_CDCDR, 16, 3);
0509     clk[IMX5_CLK_LDB_DI0_DIV_3_5]   = imx_clk_fixed_factor("ldb_di0_div_3_5", "ldb_di0_sel", 2, 7);
0510     clk[IMX5_CLK_LDB_DI0_DIV]   = imx_clk_divider_flags("ldb_di0_div", "ldb_di0_div_3_5", MXC_CCM_CSCMR2, 10, 1, 0);
0511     clk[IMX5_CLK_LDB_DI0_SEL]   = imx_clk_mux_flags("ldb_di0_sel", MXC_CCM_CSCMR2, 8, 1,
0512                         mx53_ldb_di0_sel, ARRAY_SIZE(mx53_ldb_di0_sel), CLK_SET_RATE_PARENT);
0513     clk[IMX5_CLK_LDB_DI0_GATE]  = imx_clk_gate2("ldb_di0_gate", "ldb_di0_div", MXC_CCM_CCGR6, 28);
0514     clk[IMX5_CLK_LDB_DI1_GATE]  = imx_clk_gate2("ldb_di1_gate", "ldb_di1_div", MXC_CCM_CCGR6, 30);
0515     clk[IMX5_CLK_IPU_DI0_SEL]   = imx_clk_mux_flags("ipu_di0_sel", MXC_CCM_CSCMR2, 26, 3,
0516                         mx53_ipu_di0_sel, ARRAY_SIZE(mx53_ipu_di0_sel), CLK_SET_RATE_PARENT);
0517     clk[IMX5_CLK_IPU_DI1_SEL]   = imx_clk_mux_flags("ipu_di1_sel", MXC_CCM_CSCMR2, 29, 3,
0518                         mx53_ipu_di1_sel, ARRAY_SIZE(mx53_ipu_di1_sel), CLK_SET_RATE_PARENT);
0519     clk[IMX5_CLK_TVE_EXT_SEL]   = imx_clk_mux_flags("tve_ext_sel", MXC_CCM_CSCMR1, 6, 1,
0520                         mx53_tve_ext_sel, ARRAY_SIZE(mx53_tve_ext_sel), CLK_SET_RATE_PARENT);
0521     clk[IMX5_CLK_TVE_GATE]      = imx_clk_gate2("tve_gate", "tve_pred", MXC_CCM_CCGR2, 30);
0522     clk[IMX5_CLK_TVE_PRED]      = imx_clk_divider("tve_pred", "tve_ext_sel", MXC_CCM_CDCDR, 28, 3);
0523     clk[IMX5_CLK_ESDHC_A_SEL]   = imx_clk_mux("esdhc_a_sel", MXC_CCM_CSCMR1, 20, 2,
0524                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0525     clk[IMX5_CLK_ESDHC_B_SEL]   = imx_clk_mux("esdhc_b_sel", MXC_CCM_CSCMR1, 16, 2,
0526                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0527     clk[IMX5_CLK_ESDHC_C_SEL]   = imx_clk_mux("esdhc_c_sel", MXC_CCM_CSCMR1, 19, 1, esdhc_c_sel, ARRAY_SIZE(esdhc_c_sel));
0528     clk[IMX5_CLK_ESDHC_D_SEL]   = imx_clk_mux("esdhc_d_sel", MXC_CCM_CSCMR1, 18, 1, esdhc_d_sel, ARRAY_SIZE(esdhc_d_sel));
0529     clk[IMX5_CLK_ESDHC1_PER_GATE]   = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);
0530     clk[IMX5_CLK_ESDHC2_PER_GATE]   = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);
0531     clk[IMX5_CLK_ESDHC3_PER_GATE]   = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);
0532     clk[IMX5_CLK_ESDHC4_PER_GATE]   = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
0533     clk[IMX5_CLK_USB_PHY1_GATE] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
0534     clk[IMX5_CLK_USB_PHY2_GATE] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
0535     clk[IMX5_CLK_CAN_SEL]       = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
0536                         mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
0537     clk[IMX5_CLK_CAN1_SERIAL_GATE]  = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
0538     clk[IMX5_CLK_CAN1_IPG_GATE] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
0539     clk[IMX5_CLK_OCRAM]     = imx_clk_gate2("ocram", "ahb", MXC_CCM_CCGR6, 2);
0540     clk[IMX5_CLK_CAN2_SERIAL_GATE]  = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
0541     clk[IMX5_CLK_CAN2_IPG_GATE] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
0542     clk[IMX5_CLK_I2C3_GATE]     = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
0543     clk[IMX5_CLK_SATA_GATE]     = imx_clk_gate2("sata_gate", "ipg", MXC_CCM_CCGR4, 2);
0544 
0545     clk[IMX5_CLK_FIRI_SEL]      = imx_clk_mux("firi_sel", MXC_CCM_CSCMR2, 12, 2,
0546                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0547     clk[IMX5_CLK_FIRI_PRED]     = imx_clk_divider("firi_pred", "firi_sel", MXC_CCM_CSCDR3, 6, 3);
0548     clk[IMX5_CLK_FIRI_PODF]     = imx_clk_divider("firi_podf", "firi_pred", MXC_CCM_CSCDR3, 0, 6);
0549     clk[IMX5_CLK_FIRI_SERIAL_GATE]  = imx_clk_gate2("firi_serial_gate", "firi_podf", MXC_CCM_CCGR1, 28);
0550     clk[IMX5_CLK_FIRI_IPG_GATE] = imx_clk_gate2("firi_ipg_gate", "ipg", MXC_CCM_CCGR1, 26);
0551 
0552     clk[IMX5_CLK_CSI0_MCLK1_SEL]    = imx_clk_mux("csi0_mclk1_sel", MXC_CCM_CSCMR2, 22, 2,
0553                         standard_pll_sel, ARRAY_SIZE(standard_pll_sel));
0554     clk[IMX5_CLK_CSI0_MCLK1_PRED]   = imx_clk_divider("csi0_mclk1_pred", "csi0_mclk1_sel", MXC_CCM_CSCDR4, 6, 3);
0555     clk[IMX5_CLK_CSI0_MCLK1_PODF]   = imx_clk_divider("csi0_mclk1_podf", "csi0_mclk1_pred", MXC_CCM_CSCDR4, 0, 6);
0556     clk[IMX5_CLK_CSI0_MCLK1_GATE]   = imx_clk_gate2("csi0_mclk1_serial_gate", "csi0_mclk1_podf", MXC_CCM_CCGR6, 4);
0557 
0558     clk[IMX5_CLK_IEEE1588_SEL]  = imx_clk_mux("ieee1588_sel", MXC_CCM_CSCMR2, 14, 2,
0559                         ieee1588_sels, ARRAY_SIZE(ieee1588_sels));
0560     clk[IMX5_CLK_IEEE1588_PRED] = imx_clk_divider("ieee1588_pred", "ieee1588_sel", MXC_CCM_CSCDR2, 6, 3);
0561     clk[IMX5_CLK_IEEE1588_PODF] = imx_clk_divider("ieee1588_podf", "ieee1588_pred", MXC_CCM_CSCDR2, 0, 6);
0562     clk[IMX5_CLK_IEEE1588_GATE] = imx_clk_gate2("ieee1588_serial_gate", "ieee1588_podf", MXC_CCM_CCGR7, 6);
0563     clk[IMX5_CLK_UART4_IPG_GATE]    = imx_clk_gate2("uart4_ipg_gate", "ipg", MXC_CCM_CCGR7, 8);
0564     clk[IMX5_CLK_UART4_PER_GATE]    = imx_clk_gate2("uart4_per_gate", "uart_root", MXC_CCM_CCGR7, 10);
0565     clk[IMX5_CLK_UART5_IPG_GATE]    = imx_clk_gate2("uart5_ipg_gate", "ipg", MXC_CCM_CCGR7, 12);
0566     clk[IMX5_CLK_UART5_PER_GATE]    = imx_clk_gate2("uart5_per_gate", "uart_root", MXC_CCM_CCGR7, 14);
0567 
0568     clk[IMX5_CLK_CKO1_SEL]      = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,
0569                         mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));
0570     clk[IMX5_CLK_CKO1_PODF]     = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);
0571     clk[IMX5_CLK_CKO1]      = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);
0572 
0573     clk[IMX5_CLK_CKO2_SEL]      = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,
0574                         mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));
0575     clk[IMX5_CLK_CKO2_PODF]     = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);
0576     clk[IMX5_CLK_CKO2]      = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);
0577     clk[IMX5_CLK_SPDIF_XTAL_SEL]    = imx_clk_mux("spdif_xtal_sel", MXC_CCM_CSCMR1, 2, 2,
0578                         mx53_spdif_xtal_sel, ARRAY_SIZE(mx53_spdif_xtal_sel));
0579     clk[IMX5_CLK_ARM]       = imx_clk_cpu("arm", "cpu_podf",
0580                         clk[IMX5_CLK_CPU_PODF],
0581                         clk[IMX5_CLK_CPU_PODF_SEL],
0582                         clk[IMX5_CLK_PLL1_SW],
0583                         clk[IMX5_CLK_STEP_SEL]);
0584 
0585     imx_check_clocks(clk, ARRAY_SIZE(clk));
0586 
0587     clk_data.clks = clk;
0588     clk_data.clk_num = ARRAY_SIZE(clk);
0589     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0590 
0591     /* Set SDHC parents to be PLL2 */
0592     clk_set_parent(clk[IMX5_CLK_ESDHC_A_SEL], clk[IMX5_CLK_PLL2_SW]);
0593     clk_set_parent(clk[IMX5_CLK_ESDHC_B_SEL], clk[IMX5_CLK_PLL2_SW]);
0594 
0595     /* set SDHC root clock to 200MHZ*/
0596     clk_set_rate(clk[IMX5_CLK_ESDHC_A_PODF], 200000000);
0597     clk_set_rate(clk[IMX5_CLK_ESDHC_B_PODF], 200000000);
0598 
0599     /* move can bus clk to 24MHz */
0600     clk_set_parent(clk[IMX5_CLK_CAN_SEL], clk[IMX5_CLK_LP_APM]);
0601 
0602     /* make sure step clock is running from 24MHz */
0603     clk_set_parent(clk[IMX5_CLK_STEP_SEL], clk[IMX5_CLK_LP_APM]);
0604 
0605     clk_prepare_enable(clk[IMX5_CLK_IIM_GATE]);
0606     imx_print_silicon_rev("i.MX53", mx53_revision());
0607     clk_disable_unprepare(clk[IMX5_CLK_IIM_GATE]);
0608 
0609     r = clk_round_rate(clk[IMX5_CLK_USBOH3_PER_GATE], 54000000);
0610     clk_set_rate(clk[IMX5_CLK_USBOH3_PER_GATE], r);
0611 
0612     imx_register_uart_clocks(5);
0613 }
0614 CLK_OF_DECLARE(imx53_ccm, "fsl,imx53-ccm", mx53_clocks_init);
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