0001
0002
0003
0004
0005
0006 #include <linux/module.h>
0007 #include <linux/clk.h>
0008 #include <linux/clkdev.h>
0009 #include <linux/io.h>
0010 #include <linux/err.h>
0011 #include <linux/of.h>
0012 #include <linux/of_address.h>
0013 #include <soc/imx/revision.h>
0014 #include <soc/imx/timer.h>
0015 #include <asm/irq.h>
0016
0017 #include "clk.h"
0018
0019 #define MX31_CCM_BASE_ADDR 0x53f80000
0020 #define MX31_GPT1_BASE_ADDR 0x53f90000
0021 #define MX31_INT_GPT (NR_IRQS_LEGACY + 29)
0022
0023 #define MXC_CCM_CCMR 0x00
0024 #define MXC_CCM_PDR0 0x04
0025 #define MXC_CCM_PDR1 0x08
0026 #define MXC_CCM_MPCTL 0x10
0027 #define MXC_CCM_UPCTL 0x14
0028 #define MXC_CCM_SRPCTL 0x18
0029 #define MXC_CCM_CGR0 0x20
0030 #define MXC_CCM_CGR1 0x24
0031 #define MXC_CCM_CGR2 0x28
0032 #define MXC_CCM_PMCR0 0x5c
0033
0034 static const char *mcu_main_sel[] = { "spll", "mpll", };
0035 static const char *per_sel[] = { "per_div", "ipg", };
0036 static const char *csi_sel[] = { "upll", "spll", };
0037 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
0038
0039 enum mx31_clks {
0040 dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
0041 per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
0042 fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
0043 iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
0044 uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
0045 mstick1_gate, mstick2_gate, csi_gate, rtc_gate, wdog_gate, pwm_gate,
0046 sim_gate, ect_gate, usb_gate, kpp_gate, ipu_gate, uart3_gate,
0047 uart4_gate, uart5_gate, owire_gate, ssi2_gate, cspi1_gate, cspi2_gate,
0048 gacc_gate, emi_gate, rtic_gate, firi_gate, clk_max
0049 };
0050
0051 static struct clk *clk[clk_max];
0052 static struct clk_onecell_data clk_data;
0053
0054 static void __init _mx31_clocks_init(void __iomem *base, unsigned long fref)
0055 {
0056 clk[dummy] = imx_clk_fixed("dummy", 0);
0057 clk[ckih] = imx_clk_fixed("ckih", fref);
0058 clk[ckil] = imx_clk_fixed("ckil", 32768);
0059 clk[mpll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "mpll", "ckih", base + MXC_CCM_MPCTL);
0060 clk[spll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "spll", "ckih", base + MXC_CCM_SRPCTL);
0061 clk[upll] = imx_clk_pllv1(IMX_PLLV1_IMX31, "upll", "ckih", base + MXC_CCM_UPCTL);
0062 clk[mcu_main] = imx_clk_mux("mcu_main", base + MXC_CCM_PMCR0, 31, 1, mcu_main_sel, ARRAY_SIZE(mcu_main_sel));
0063 clk[hsp] = imx_clk_divider("hsp", "mcu_main", base + MXC_CCM_PDR0, 11, 3);
0064 clk[ahb] = imx_clk_divider("ahb", "mcu_main", base + MXC_CCM_PDR0, 3, 3);
0065 clk[nfc] = imx_clk_divider("nfc", "ahb", base + MXC_CCM_PDR0, 8, 3);
0066 clk[ipg] = imx_clk_divider("ipg", "ahb", base + MXC_CCM_PDR0, 6, 2);
0067 clk[per_div] = imx_clk_divider("per_div", "upll", base + MXC_CCM_PDR0, 16, 5);
0068 clk[per] = imx_clk_mux("per", base + MXC_CCM_CCMR, 24, 1, per_sel, ARRAY_SIZE(per_sel));
0069 clk[csi] = imx_clk_mux("csi_sel", base + MXC_CCM_CCMR, 25, 1, csi_sel, ARRAY_SIZE(csi_sel));
0070 clk[fir] = imx_clk_mux("fir_sel", base + MXC_CCM_CCMR, 11, 2, fir_sel, ARRAY_SIZE(fir_sel));
0071 clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MXC_CCM_PDR0, 23, 9);
0072 clk[usb_div_pre] = imx_clk_divider("usb_div_pre", "upll", base + MXC_CCM_PDR1, 30, 2);
0073 clk[usb_div_post] = imx_clk_divider("usb_div_post", "usb_div_pre", base + MXC_CCM_PDR1, 27, 3);
0074 clk[fir_div_pre] = imx_clk_divider("fir_div_pre", "fir_sel", base + MXC_CCM_PDR1, 24, 3);
0075 clk[fir_div_post] = imx_clk_divider("fir_div_post", "fir_div_pre", base + MXC_CCM_PDR1, 23, 6);
0076 clk[sdhc1_gate] = imx_clk_gate2("sdhc1_gate", "per", base + MXC_CCM_CGR0, 0);
0077 clk[sdhc2_gate] = imx_clk_gate2("sdhc2_gate", "per", base + MXC_CCM_CGR0, 2);
0078 clk[gpt_gate] = imx_clk_gate2("gpt_gate", "per", base + MXC_CCM_CGR0, 4);
0079 clk[epit1_gate] = imx_clk_gate2("epit1_gate", "per", base + MXC_CCM_CGR0, 6);
0080 clk[epit2_gate] = imx_clk_gate2("epit2_gate", "per", base + MXC_CCM_CGR0, 8);
0081 clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MXC_CCM_CGR0, 10);
0082 clk[ata_gate] = imx_clk_gate2("ata_gate", "ipg", base + MXC_CCM_CGR0, 12);
0083 clk[sdma_gate] = imx_clk_gate2("sdma_gate", "ahb", base + MXC_CCM_CGR0, 14);
0084 clk[cspi3_gate] = imx_clk_gate2("cspi3_gate", "ipg", base + MXC_CCM_CGR0, 16);
0085 clk[rng_gate] = imx_clk_gate2("rng_gate", "ipg", base + MXC_CCM_CGR0, 18);
0086 clk[uart1_gate] = imx_clk_gate2("uart1_gate", "per", base + MXC_CCM_CGR0, 20);
0087 clk[uart2_gate] = imx_clk_gate2("uart2_gate", "per", base + MXC_CCM_CGR0, 22);
0088 clk[ssi1_gate] = imx_clk_gate2("ssi1_gate", "spll", base + MXC_CCM_CGR0, 24);
0089 clk[i2c1_gate] = imx_clk_gate2("i2c1_gate", "per", base + MXC_CCM_CGR0, 26);
0090 clk[i2c2_gate] = imx_clk_gate2("i2c2_gate", "per", base + MXC_CCM_CGR0, 28);
0091 clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per", base + MXC_CCM_CGR0, 30);
0092 clk[hantro_gate] = imx_clk_gate2("hantro_gate", "per", base + MXC_CCM_CGR1, 0);
0093 clk[mstick1_gate] = imx_clk_gate2("mstick1_gate", "per", base + MXC_CCM_CGR1, 2);
0094 clk[mstick2_gate] = imx_clk_gate2("mstick2_gate", "per", base + MXC_CCM_CGR1, 4);
0095 clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MXC_CCM_CGR1, 6);
0096 clk[rtc_gate] = imx_clk_gate2("rtc_gate", "ipg", base + MXC_CCM_CGR1, 8);
0097 clk[wdog_gate] = imx_clk_gate2("wdog_gate", "ipg", base + MXC_CCM_CGR1, 10);
0098 clk[pwm_gate] = imx_clk_gate2("pwm_gate", "per", base + MXC_CCM_CGR1, 12);
0099 clk[sim_gate] = imx_clk_gate2("sim_gate", "per", base + MXC_CCM_CGR1, 14);
0100 clk[ect_gate] = imx_clk_gate2("ect_gate", "per", base + MXC_CCM_CGR1, 16);
0101 clk[usb_gate] = imx_clk_gate2("usb_gate", "ahb", base + MXC_CCM_CGR1, 18);
0102 clk[kpp_gate] = imx_clk_gate2("kpp_gate", "ipg", base + MXC_CCM_CGR1, 20);
0103 clk[ipu_gate] = imx_clk_gate2("ipu_gate", "hsp", base + MXC_CCM_CGR1, 22);
0104 clk[uart3_gate] = imx_clk_gate2("uart3_gate", "per", base + MXC_CCM_CGR1, 24);
0105 clk[uart4_gate] = imx_clk_gate2("uart4_gate", "per", base + MXC_CCM_CGR1, 26);
0106 clk[uart5_gate] = imx_clk_gate2("uart5_gate", "per", base + MXC_CCM_CGR1, 28);
0107 clk[owire_gate] = imx_clk_gate2("owire_gate", "per", base + MXC_CCM_CGR1, 30);
0108 clk[ssi2_gate] = imx_clk_gate2("ssi2_gate", "spll", base + MXC_CCM_CGR2, 0);
0109 clk[cspi1_gate] = imx_clk_gate2("cspi1_gate", "ipg", base + MXC_CCM_CGR2, 2);
0110 clk[cspi2_gate] = imx_clk_gate2("cspi2_gate", "ipg", base + MXC_CCM_CGR2, 4);
0111 clk[gacc_gate] = imx_clk_gate2("gacc_gate", "per", base + MXC_CCM_CGR2, 6);
0112 clk[emi_gate] = imx_clk_gate2("emi_gate", "ahb", base + MXC_CCM_CGR2, 8);
0113 clk[rtic_gate] = imx_clk_gate2("rtic_gate", "ahb", base + MXC_CCM_CGR2, 10);
0114 clk[firi_gate] = imx_clk_gate2("firi_gate", "upll", base+MXC_CCM_CGR2, 12);
0115
0116 imx_check_clocks(clk, ARRAY_SIZE(clk));
0117
0118 clk_set_parent(clk[csi], clk[upll]);
0119 clk_prepare_enable(clk[emi_gate]);
0120 clk_prepare_enable(clk[iim_gate]);
0121 mx31_revision();
0122 clk_disable_unprepare(clk[iim_gate]);
0123 }
0124
0125 static void __init mx31_clocks_init_dt(struct device_node *np)
0126 {
0127 struct device_node *osc_np;
0128 u32 fref = 26000000;
0129 void __iomem *ccm;
0130
0131 for_each_compatible_node(osc_np, NULL, "fixed-clock") {
0132 if (!of_device_is_compatible(osc_np, "fsl,imx-osc26m"))
0133 continue;
0134
0135 if (!of_property_read_u32(osc_np, "clock-frequency", &fref)) {
0136 of_node_put(osc_np);
0137 break;
0138 }
0139 }
0140
0141 ccm = of_iomap(np, 0);
0142 if (!ccm)
0143 panic("%s: failed to map registers\n", __func__);
0144
0145 _mx31_clocks_init(ccm, fref);
0146
0147 clk_data.clks = clk;
0148 clk_data.clk_num = ARRAY_SIZE(clk);
0149 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0150 }
0151
0152 CLK_OF_DECLARE(imx31_ccm, "fsl,imx31-ccm", mx31_clocks_init_dt);
