clk/imx/clk-imx1.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *  Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
0004  */
0005
0006 #include <linux/clkdev.h>
0007 #include <linux/clk-provider.h>
0008 #include <linux/err.h>
0009 #include <linux/init.h>
0010 #include <linux/of.h>
0011 #include <linux/of_address.h>
0012 #include <dt-bindings/clock/imx1-clock.h>
0013 #include <soc/imx/timer.h>
0014 #include <asm/irq.h>
0015
0016 #include "clk.h"
0017
0018 #define MX1_CCM_BASE_ADDR   0x0021b000
0019 #define MX1_TIM1_BASE_ADDR  0x00220000
0020 #define MX1_TIM1_INT        (NR_IRQS_LEGACY + 59)
0021
0022 static const char *prem_sel_clks[] = { "clk32_premult", "clk16m", };
0023 static const char *clko_sel_clks[] = { "per1", "hclk", "clk48m", "clk16m",
0024                        "prem", "fclk", };
0025
0026 static struct clk *clk[IMX1_CLK_MAX];
0027 static struct clk_onecell_data clk_data;
0028
0029 static void __iomem *ccm __initdata;
0030 #define CCM_CSCR    (ccm + 0x0000)
0031 #define CCM_MPCTL0  (ccm + 0x0004)
0032 #define CCM_SPCTL0  (ccm + 0x000c)
0033 #define CCM_PCDR    (ccm + 0x0020)
0034 #define SCM_GCCR    (ccm + 0x0810)
0035
0036 static void __init mx1_clocks_init_dt(struct device_node *np)
0037 {
0038     ccm = of_iomap(np, 0);
0039     BUG_ON(!ccm);
0040
0041     clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
0042     clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", 32768);
0043     clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
0044     clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
0045     clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
0046     clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
0047     clk[IMX1_CLK_MPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "mpll", "clk32_premult", CCM_MPCTL0);
0048     clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
0049     clk[IMX1_CLK_SPLL] = imx_clk_pllv1(IMX_PLLV1_IMX1, "spll", "prem", CCM_SPCTL0);
0050     clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
0051     clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
0052     clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
0053     clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
0054     clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
0055     clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
0056     clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
0057     clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
0058     clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
0059     clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
0060     clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
0061     clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
0062     clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
0063     clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
0064     clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
0065     clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);
0066
0067     imx_check_clocks(clk, ARRAY_SIZE(clk));
0068
0069     clk_data.clks = clk;
0070     clk_data.clk_num = ARRAY_SIZE(clk);
0071     of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
0072 }
0073 CLK_OF_DECLARE(imx1_ccm, "fsl,imx1-ccm", mx1_clocks_init_dt);