clk/imx/clk-frac-pll.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2018 NXP.
0004  *
0005  * This driver supports the fractional plls found in the imx8m SOCs
0006  *
0007  * Documentation for this fractional pll can be found at:
0008  *   https://www.nxp.com/docs/en/reference-manual/IMX8MDQLQRM.pdf#page=834
0009  */
0010
0011 #include <linux/clk-provider.h>
0012 #include <linux/err.h>
0013 #include <linux/export.h>
0014 #include <linux/io.h>
0015 #include <linux/iopoll.h>
0016 #include <linux/slab.h>
0017 #include <linux/bitfield.h>
0018
0019 #include "clk.h"
0020
0021 #define PLL_CFG0        0x0
0022 #define PLL_CFG1        0x4
0023
0024 #define PLL_LOCK_STATUS     BIT(31)
0025 #define PLL_PD_MASK     BIT(19)
0026 #define PLL_BYPASS_MASK     BIT(14)
0027 #define PLL_NEWDIV_VAL      BIT(12)
0028 #define PLL_NEWDIV_ACK      BIT(11)
0029 #define PLL_FRAC_DIV_MASK   GENMASK(30, 7)
0030 #define PLL_INT_DIV_MASK    GENMASK(6, 0)
0031 #define PLL_OUTPUT_DIV_MASK GENMASK(4, 0)
0032 #define PLL_FRAC_DENOM      0x1000000
0033
0034 #define PLL_FRAC_LOCK_TIMEOUT   10000
0035 #define PLL_FRAC_ACK_TIMEOUT    500000
0036
0037 struct clk_frac_pll {
0038     struct clk_hw   hw;
0039     void __iomem    *base;
0040 };
0041
0042 #define to_clk_frac_pll(_hw) container_of(_hw, struct clk_frac_pll, hw)
0043
0044 static int clk_wait_lock(struct clk_frac_pll *pll)
0045 {
0046     u32 val;
0047
0048     return readl_poll_timeout(pll->base, val, val & PLL_LOCK_STATUS, 0,
0049                     PLL_FRAC_LOCK_TIMEOUT);
0050 }
0051
0052 static int clk_wait_ack(struct clk_frac_pll *pll)
0053 {
0054     u32 val;
0055
0056     /* return directly if the pll is in powerdown or in bypass */
0057     if (readl_relaxed(pll->base) & (PLL_PD_MASK | PLL_BYPASS_MASK))
0058         return 0;
0059
0060     /* Wait for the pll's divfi and divff to be reloaded */
0061     return readl_poll_timeout(pll->base, val, val & PLL_NEWDIV_ACK, 0,
0062                     PLL_FRAC_ACK_TIMEOUT);
0063 }
0064
0065 static int clk_pll_prepare(struct clk_hw *hw)
0066 {
0067     struct clk_frac_pll *pll = to_clk_frac_pll(hw);
0068     u32 val;
0069
0070     val = readl_relaxed(pll->base + PLL_CFG0);
0071     val &= ~PLL_PD_MASK;
0072     writel_relaxed(val, pll->base + PLL_CFG0);
0073
0074     return clk_wait_lock(pll);
0075 }
0076
0077 static void clk_pll_unprepare(struct clk_hw *hw)
0078 {
0079     struct clk_frac_pll *pll = to_clk_frac_pll(hw);
0080     u32 val;
0081
0082     val = readl_relaxed(pll->base + PLL_CFG0);
0083     val |= PLL_PD_MASK;
0084     writel_relaxed(val, pll->base + PLL_CFG0);
0085 }
0086
0087 static int clk_pll_is_prepared(struct clk_hw *hw)
0088 {
0089     struct clk_frac_pll *pll = to_clk_frac_pll(hw);
0090     u32 val;
0091
0092     val = readl_relaxed(pll->base + PLL_CFG0);
0093     return (val & PLL_PD_MASK) ? 0 : 1;
0094 }
0095
0096 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
0097                      unsigned long parent_rate)
0098 {
0099     struct clk_frac_pll *pll = to_clk_frac_pll(hw);
0100     u32 val, divff, divfi, divq;
0101     u64 temp64 = parent_rate;
0102     u64 rate;
0103
0104     val = readl_relaxed(pll->base + PLL_CFG0);
0105     divq = (FIELD_GET(PLL_OUTPUT_DIV_MASK, val) + 1) * 2;
0106     val = readl_relaxed(pll->base + PLL_CFG1);
0107     divff = FIELD_GET(PLL_FRAC_DIV_MASK, val);
0108     divfi = FIELD_GET(PLL_INT_DIV_MASK, val);
0109
0110     temp64 *= 8;
0111     temp64 *= divff;
0112     do_div(temp64, PLL_FRAC_DENOM);
0113     do_div(temp64, divq);
0114
0115     rate = parent_rate * 8 * (divfi + 1);
0116     do_div(rate, divq);
0117     rate += temp64;
0118
0119     return rate;
0120 }
0121
0122 static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0123                    unsigned long *prate)
0124 {
0125     u64 parent_rate = *prate;
0126     u32 divff, divfi;
0127     u64 temp64;
0128
0129     parent_rate *= 8;
0130     rate *= 2;
0131     temp64 = rate;
0132     do_div(temp64, parent_rate);
0133     divfi = temp64;
0134     temp64 = rate - divfi * parent_rate;
0135     temp64 *= PLL_FRAC_DENOM;
0136     do_div(temp64, parent_rate);
0137     divff = temp64;
0138
0139     temp64 = parent_rate;
0140     temp64 *= divff;
0141     do_div(temp64, PLL_FRAC_DENOM);
0142
0143     rate = parent_rate * divfi + temp64;
0144
0145     return rate / 2;
0146 }
0147
0148 /*
0149  * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
0150  * (means the PLL output will be divided by 2). So the PLL output can use
0151  * the below formula:
0152  * pllout = parent_rate * 8 / 2 * DIVF_VAL;
0153  * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
0154  */
0155 static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0156                 unsigned long parent_rate)
0157 {
0158     struct clk_frac_pll *pll = to_clk_frac_pll(hw);
0159     u32 val, divfi, divff;
0160     u64 temp64;
0161     int ret;
0162
0163     parent_rate *= 8;
0164     rate *= 2;
0165     divfi = rate / parent_rate;
0166     temp64 = parent_rate * divfi;
0167     temp64 = rate - temp64;
0168     temp64 *= PLL_FRAC_DENOM;
0169     do_div(temp64, parent_rate);
0170     divff = temp64;
0171
0172     val = readl_relaxed(pll->base + PLL_CFG1);
0173     val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
0174     val |= (divff << 7) | (divfi - 1);
0175     writel_relaxed(val, pll->base + PLL_CFG1);
0176
0177     val = readl_relaxed(pll->base + PLL_CFG0);
0178     val &= ~0x1f;
0179     writel_relaxed(val, pll->base + PLL_CFG0);
0180
0181     /* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
0182     val = readl_relaxed(pll->base + PLL_CFG0);
0183     val |= PLL_NEWDIV_VAL;
0184     writel_relaxed(val, pll->base + PLL_CFG0);
0185
0186     ret = clk_wait_ack(pll);
0187
0188     /* clear the NEV_DIV_VAL */
0189     val = readl_relaxed(pll->base + PLL_CFG0);
0190     val &= ~PLL_NEWDIV_VAL;
0191     writel_relaxed(val, pll->base + PLL_CFG0);
0192
0193     return ret;
0194 }
0195
0196 static const struct clk_ops clk_frac_pll_ops = {
0197     .prepare    = clk_pll_prepare,
0198     .unprepare  = clk_pll_unprepare,
0199     .is_prepared    = clk_pll_is_prepared,
0200     .recalc_rate    = clk_pll_recalc_rate,
0201     .round_rate = clk_pll_round_rate,
0202     .set_rate   = clk_pll_set_rate,
0203 };
0204
0205 struct clk_hw *imx_clk_hw_frac_pll(const char *name,
0206                    const char *parent_name,
0207                    void __iomem *base)
0208 {
0209     struct clk_init_data init;
0210     struct clk_frac_pll *pll;
0211     struct clk_hw *hw;
0212     int ret;
0213
0214     pll = kzalloc(sizeof(*pll), GFP_KERNEL);
0215     if (!pll)
0216         return ERR_PTR(-ENOMEM);
0217
0218     init.name = name;
0219     init.ops = &clk_frac_pll_ops;
0220     init.flags = 0;
0221     init.parent_names = &parent_name;
0222     init.num_parents = 1;
0223
0224     pll->base = base;
0225     pll->hw.init = &init;
0226
0227     hw = &pll->hw;
0228
0229     ret = clk_hw_register(NULL, hw);
0230     if (ret) {
0231         kfree(pll);
0232         return ERR_PTR(ret);
0233     }
0234
0235     return hw;
0236 }
0237 EXPORT_SYMBOL_GPL(imx_clk_hw_frac_pll);