clk/imx/clk-composite-8m.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright 2018 NXP
0004  */
0005
0006 #include <linux/clk-provider.h>
0007 #include <linux/errno.h>
0008 #include <linux/export.h>
0009 #include <linux/io.h>
0010 #include <linux/slab.h>
0011
0012 #include "clk.h"
0013
0014 #define PCG_PREDIV_SHIFT    16
0015 #define PCG_PREDIV_WIDTH    3
0016 #define PCG_PREDIV_MAX      8
0017
0018 #define PCG_DIV_SHIFT       0
0019 #define PCG_CORE_DIV_WIDTH  3
0020 #define PCG_DIV_WIDTH       6
0021 #define PCG_DIV_MAX     64
0022
0023 #define PCG_PCS_SHIFT       24
0024 #define PCG_PCS_MASK        0x7
0025
0026 #define PCG_CGC_SHIFT       28
0027
0028 static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
0029                         unsigned long parent_rate)
0030 {
0031     struct clk_divider *divider = to_clk_divider(hw);
0032     unsigned long prediv_rate;
0033     unsigned int prediv_value;
0034     unsigned int div_value;
0035
0036     prediv_value = readl(divider->reg) >> divider->shift;
0037     prediv_value &= clk_div_mask(divider->width);
0038
0039     prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
0040                         NULL, divider->flags,
0041                         divider->width);
0042
0043     div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
0044     div_value &= clk_div_mask(PCG_DIV_WIDTH);
0045
0046     return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
0047                    divider->flags, PCG_DIV_WIDTH);
0048 }
0049
0050 static int imx8m_clk_composite_compute_dividers(unsigned long rate,
0051                         unsigned long parent_rate,
0052                         int *prediv, int *postdiv)
0053 {
0054     int div1, div2;
0055     int error = INT_MAX;
0056     int ret = -EINVAL;
0057
0058     *prediv = 1;
0059     *postdiv = 1;
0060
0061     for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
0062         for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) {
0063             int new_error = ((parent_rate / div1) / div2) - rate;
0064
0065             if (abs(new_error) < abs(error)) {
0066                 *prediv = div1;
0067                 *postdiv = div2;
0068                 error = new_error;
0069                 ret = 0;
0070             }
0071         }
0072     }
0073     return ret;
0074 }
0075
0076 static long imx8m_clk_composite_divider_round_rate(struct clk_hw *hw,
0077                         unsigned long rate,
0078                         unsigned long *prate)
0079 {
0080     int prediv_value;
0081     int div_value;
0082
0083     imx8m_clk_composite_compute_dividers(rate, *prate,
0084                         &prediv_value, &div_value);
0085     rate = DIV_ROUND_UP(*prate, prediv_value);
0086
0087     return DIV_ROUND_UP(rate, div_value);
0088
0089 }
0090
0091 static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
0092                     unsigned long rate,
0093                     unsigned long parent_rate)
0094 {
0095     struct clk_divider *divider = to_clk_divider(hw);
0096     unsigned long flags;
0097     int prediv_value;
0098     int div_value;
0099     int ret;
0100     u32 val;
0101
0102     ret = imx8m_clk_composite_compute_dividers(rate, parent_rate,
0103                         &prediv_value, &div_value);
0104     if (ret)
0105         return -EINVAL;
0106
0107     spin_lock_irqsave(divider->lock, flags);
0108
0109     val = readl(divider->reg);
0110     val &= ~((clk_div_mask(divider->width) << divider->shift) |
0111             (clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
0112
0113     val |= (u32)(prediv_value  - 1) << divider->shift;
0114     val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
0115     writel(val, divider->reg);
0116
0117     spin_unlock_irqrestore(divider->lock, flags);
0118
0119     return ret;
0120 }
0121
0122 static const struct clk_ops imx8m_clk_composite_divider_ops = {
0123     .recalc_rate = imx8m_clk_composite_divider_recalc_rate,
0124     .round_rate = imx8m_clk_composite_divider_round_rate,
0125     .set_rate = imx8m_clk_composite_divider_set_rate,
0126 };
0127
0128 static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw)
0129 {
0130     return clk_mux_ops.get_parent(hw);
0131 }
0132
0133 static int imx8m_clk_composite_mux_set_parent(struct clk_hw *hw, u8 index)
0134 {
0135     struct clk_mux *mux = to_clk_mux(hw);
0136     u32 val = clk_mux_index_to_val(mux->table, mux->flags, index);
0137     unsigned long flags = 0;
0138     u32 reg;
0139
0140     if (mux->lock)
0141         spin_lock_irqsave(mux->lock, flags);
0142
0143     reg = readl(mux->reg);
0144     reg &= ~(mux->mask << mux->shift);
0145     val = val << mux->shift;
0146     reg |= val;
0147     /*
0148      * write twice to make sure non-target interface
0149      * SEL_A/B point the same clk input.
0150      */
0151     writel(reg, mux->reg);
0152     writel(reg, mux->reg);
0153
0154     if (mux->lock)
0155         spin_unlock_irqrestore(mux->lock, flags);
0156
0157     return 0;
0158 }
0159
0160 static int
0161 imx8m_clk_composite_mux_determine_rate(struct clk_hw *hw,
0162                        struct clk_rate_request *req)
0163 {
0164     return clk_mux_ops.determine_rate(hw, req);
0165 }
0166
0167
0168 static const struct clk_ops imx8m_clk_composite_mux_ops = {
0169     .get_parent = imx8m_clk_composite_mux_get_parent,
0170     .set_parent = imx8m_clk_composite_mux_set_parent,
0171     .determine_rate = imx8m_clk_composite_mux_determine_rate,
0172 };
0173
0174 struct clk_hw *__imx8m_clk_hw_composite(const char *name,
0175                     const char * const *parent_names,
0176                     int num_parents, void __iomem *reg,
0177                     u32 composite_flags,
0178                     unsigned long flags)
0179 {
0180     struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
0181     struct clk_hw *div_hw, *gate_hw = NULL;
0182     struct clk_divider *div = NULL;
0183     struct clk_gate *gate = NULL;
0184     struct clk_mux *mux = NULL;
0185     const struct clk_ops *divider_ops;
0186     const struct clk_ops *mux_ops;
0187
0188     mux = kzalloc(sizeof(*mux), GFP_KERNEL);
0189     if (!mux)
0190         goto fail;
0191
0192     mux_hw = &mux->hw;
0193     mux->reg = reg;
0194     mux->shift = PCG_PCS_SHIFT;
0195     mux->mask = PCG_PCS_MASK;
0196     mux->lock = &imx_ccm_lock;
0197
0198     div = kzalloc(sizeof(*div), GFP_KERNEL);
0199     if (!div)
0200         goto fail;
0201
0202     div_hw = &div->hw;
0203     div->reg = reg;
0204     if (composite_flags & IMX_COMPOSITE_CORE) {
0205         div->shift = PCG_DIV_SHIFT;
0206         div->width = PCG_CORE_DIV_WIDTH;
0207         divider_ops = &clk_divider_ops;
0208         mux_ops = &imx8m_clk_composite_mux_ops;
0209     } else if (composite_flags & IMX_COMPOSITE_BUS) {
0210         div->shift = PCG_PREDIV_SHIFT;
0211         div->width = PCG_PREDIV_WIDTH;
0212         divider_ops = &imx8m_clk_composite_divider_ops;
0213         mux_ops = &imx8m_clk_composite_mux_ops;
0214     } else {
0215         div->shift = PCG_PREDIV_SHIFT;
0216         div->width = PCG_PREDIV_WIDTH;
0217         divider_ops = &imx8m_clk_composite_divider_ops;
0218         mux_ops = &clk_mux_ops;
0219         if (!(composite_flags & IMX_COMPOSITE_FW_MANAGED))
0220             flags |= CLK_SET_PARENT_GATE;
0221     }
0222
0223     div->lock = &imx_ccm_lock;
0224     div->flags = CLK_DIVIDER_ROUND_CLOSEST;
0225
0226     /* skip registering the gate ops if M4 is enabled */
0227     if (!mcore_booted) {
0228         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
0229         if (!gate)
0230             goto fail;
0231
0232         gate_hw = &gate->hw;
0233         gate->reg = reg;
0234         gate->bit_idx = PCG_CGC_SHIFT;
0235         gate->lock = &imx_ccm_lock;
0236     }
0237
0238     hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
0239             mux_hw, mux_ops, div_hw,
0240             divider_ops, gate_hw, &clk_gate_ops, flags);
0241     if (IS_ERR(hw))
0242         goto fail;
0243
0244     return hw;
0245
0246 fail:
0247     kfree(gate);
0248     kfree(div);
0249     kfree(mux);
0250     return ERR_CAST(hw);
0251 }
0252 EXPORT_SYMBOL_GPL(__imx8m_clk_hw_composite);