clk/imgtec/clk-boston.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2016-2017 Imagination Technologies
0004  * Author: Paul Burton <paul.burton@mips.com>
0005  */
0006
0007 #define pr_fmt(fmt) "clk-boston: " fmt
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/kernel.h>
0011 #include <linux/of.h>
0012 #include <linux/regmap.h>
0013 #include <linux/slab.h>
0014 #include <linux/mfd/syscon.h>
0015
0016 #include <dt-bindings/clock/boston-clock.h>
0017
0018 #define BOSTON_PLAT_MMCMDIV     0x30
0019 # define BOSTON_PLAT_MMCMDIV_CLK0DIV    (0xff << 0)
0020 # define BOSTON_PLAT_MMCMDIV_INPUT  (0xff << 8)
0021 # define BOSTON_PLAT_MMCMDIV_MUL    (0xff << 16)
0022 # define BOSTON_PLAT_MMCMDIV_CLK1DIV    (0xff << 24)
0023
0024 #define BOSTON_CLK_COUNT 3
0025
0026 static u32 ext_field(u32 val, u32 mask)
0027 {
0028     return (val & mask) >> (ffs(mask) - 1);
0029 }
0030
0031 static void __init clk_boston_setup(struct device_node *np)
0032 {
0033     unsigned long in_freq, cpu_freq, sys_freq;
0034     uint mmcmdiv, mul, cpu_div, sys_div;
0035     struct clk_hw_onecell_data *onecell;
0036     struct regmap *regmap;
0037     struct clk_hw *hw;
0038     int err;
0039
0040     regmap = syscon_node_to_regmap(np->parent);
0041     if (IS_ERR(regmap)) {
0042         pr_err("failed to find regmap\n");
0043         return;
0044     }
0045
0046     err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
0047     if (err) {
0048         pr_err("failed to read mmcm_div register: %d\n", err);
0049         return;
0050     }
0051
0052     in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
0053     mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
0054
0055     sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
0056     sys_freq = mult_frac(in_freq, mul, sys_div);
0057
0058     cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
0059     cpu_freq = mult_frac(in_freq, mul, cpu_div);
0060
0061     onecell = kzalloc(struct_size(onecell, hws, BOSTON_CLK_COUNT),
0062               GFP_KERNEL);
0063     if (!onecell)
0064         return;
0065
0066     onecell->num = BOSTON_CLK_COUNT;
0067
0068     hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
0069     if (IS_ERR(hw)) {
0070         pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
0071         goto fail_input;
0072     }
0073     onecell->hws[BOSTON_CLK_INPUT] = hw;
0074
0075     hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
0076     if (IS_ERR(hw)) {
0077         pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
0078         goto fail_sys;
0079     }
0080     onecell->hws[BOSTON_CLK_SYS] = hw;
0081
0082     hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
0083     if (IS_ERR(hw)) {
0084         pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
0085         goto fail_cpu;
0086     }
0087     onecell->hws[BOSTON_CLK_CPU] = hw;
0088
0089     err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
0090     if (err) {
0091         pr_err("failed to add DT provider: %d\n", err);
0092         goto fail_clk_add;
0093     }
0094
0095     return;
0096
0097 fail_clk_add:
0098     clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_CPU]);
0099 fail_cpu:
0100     clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_SYS]);
0101 fail_sys:
0102     clk_hw_unregister_fixed_rate(onecell->hws[BOSTON_CLK_INPUT]);
0103 fail_input:
0104     kfree(onecell);
0105 }
0106
0107 /*
0108  * Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
0109  * CPU frequency for use with the GIC or cop0 counters/timers.
0110  */
0111 CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);