clk/hisilicon/reset.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Hisilicon Reset Controller Driver
0004  *
0005  * Copyright (c) 2015-2016 HiSilicon Technologies Co., Ltd.
0006  */
0007
0008 #include <linux/io.h>
0009 #include <linux/of_address.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/reset-controller.h>
0012 #include <linux/slab.h>
0013 #include <linux/spinlock.h>
0014 #include "reset.h"
0015
0016 #define HISI_RESET_BIT_MASK 0x1f
0017 #define HISI_RESET_OFFSET_SHIFT 8
0018 #define HISI_RESET_OFFSET_MASK  0xffff00
0019
0020 struct hisi_reset_controller {
0021     spinlock_t  lock;
0022     void __iomem    *membase;
0023     struct reset_controller_dev rcdev;
0024 };
0025
0026
0027 #define to_hisi_reset_controller(rcdev)  \
0028     container_of(rcdev, struct hisi_reset_controller, rcdev)
0029
0030 static int hisi_reset_of_xlate(struct reset_controller_dev *rcdev,
0031             const struct of_phandle_args *reset_spec)
0032 {
0033     u32 offset;
0034     u8 bit;
0035
0036     offset = (reset_spec->args[0] << HISI_RESET_OFFSET_SHIFT)
0037         & HISI_RESET_OFFSET_MASK;
0038     bit = reset_spec->args[1] & HISI_RESET_BIT_MASK;
0039
0040     return (offset | bit);
0041 }
0042
0043 static int hisi_reset_assert(struct reset_controller_dev *rcdev,
0044                   unsigned long id)
0045 {
0046     struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
0047     unsigned long flags;
0048     u32 offset, reg;
0049     u8 bit;
0050
0051     offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
0052     bit = id & HISI_RESET_BIT_MASK;
0053
0054     spin_lock_irqsave(&rstc->lock, flags);
0055
0056     reg = readl(rstc->membase + offset);
0057     writel(reg | BIT(bit), rstc->membase + offset);
0058
0059     spin_unlock_irqrestore(&rstc->lock, flags);
0060
0061     return 0;
0062 }
0063
0064 static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
0065                 unsigned long id)
0066 {
0067     struct hisi_reset_controller *rstc = to_hisi_reset_controller(rcdev);
0068     unsigned long flags;
0069     u32 offset, reg;
0070     u8 bit;
0071
0072     offset = (id & HISI_RESET_OFFSET_MASK) >> HISI_RESET_OFFSET_SHIFT;
0073     bit = id & HISI_RESET_BIT_MASK;
0074
0075     spin_lock_irqsave(&rstc->lock, flags);
0076
0077     reg = readl(rstc->membase + offset);
0078     writel(reg & ~BIT(bit), rstc->membase + offset);
0079
0080     spin_unlock_irqrestore(&rstc->lock, flags);
0081
0082     return 0;
0083 }
0084
0085 static const struct reset_control_ops hisi_reset_ops = {
0086     .assert     = hisi_reset_assert,
0087     .deassert   = hisi_reset_deassert,
0088 };
0089
0090 struct hisi_reset_controller *hisi_reset_init(struct platform_device *pdev)
0091 {
0092     struct hisi_reset_controller *rstc;
0093
0094     rstc = devm_kmalloc(&pdev->dev, sizeof(*rstc), GFP_KERNEL);
0095     if (!rstc)
0096         return NULL;
0097
0098     rstc->membase = devm_platform_ioremap_resource(pdev, 0);
0099     if (IS_ERR(rstc->membase))
0100         return NULL;
0101
0102     spin_lock_init(&rstc->lock);
0103     rstc->rcdev.owner = THIS_MODULE;
0104     rstc->rcdev.ops = &hisi_reset_ops;
0105     rstc->rcdev.of_node = pdev->dev.of_node;
0106     rstc->rcdev.of_reset_n_cells = 2;
0107     rstc->rcdev.of_xlate = hisi_reset_of_xlate;
0108     reset_controller_register(&rstc->rcdev);
0109
0110     return rstc;
0111 }
0112 EXPORT_SYMBOL_GPL(hisi_reset_init);
0113
0114 void hisi_reset_exit(struct hisi_reset_controller *rstc)
0115 {
0116     reset_controller_unregister(&rstc->rcdev);
0117 }
0118 EXPORT_SYMBOL_GPL(hisi_reset_exit);