clk/hisilicon/crg-hi3798cv200.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Hi3798CV200 Clock and Reset Generator Driver
0004  *
0005  * Copyright (c) 2016 HiSilicon Technologies Co., Ltd.
0006  */
0007
0008 #include <dt-bindings/clock/histb-clock.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/module.h>
0011 #include <linux/of_device.h>
0012 #include <linux/platform_device.h>
0013 #include "clk.h"
0014 #include "crg.h"
0015 #include "reset.h"
0016
0017 /* hi3798CV200 core CRG */
0018 #define HI3798CV200_INNER_CLK_OFFSET        64
0019 #define HI3798CV200_FIXED_24M           65
0020 #define HI3798CV200_FIXED_25M           66
0021 #define HI3798CV200_FIXED_50M           67
0022 #define HI3798CV200_FIXED_75M           68
0023 #define HI3798CV200_FIXED_100M          69
0024 #define HI3798CV200_FIXED_150M          70
0025 #define HI3798CV200_FIXED_200M          71
0026 #define HI3798CV200_FIXED_250M          72
0027 #define HI3798CV200_FIXED_300M          73
0028 #define HI3798CV200_FIXED_400M          74
0029 #define HI3798CV200_MMC_MUX         75
0030 #define HI3798CV200_ETH_PUB_CLK         76
0031 #define HI3798CV200_ETH_BUS_CLK         77
0032 #define HI3798CV200_ETH_BUS0_CLK        78
0033 #define HI3798CV200_ETH_BUS1_CLK        79
0034 #define HI3798CV200_COMBPHY1_MUX        80
0035 #define HI3798CV200_FIXED_12M           81
0036 #define HI3798CV200_FIXED_48M           82
0037 #define HI3798CV200_FIXED_60M           83
0038 #define HI3798CV200_FIXED_166P5M        84
0039 #define HI3798CV200_SDIO0_MUX           85
0040 #define HI3798CV200_COMBPHY0_MUX        86
0041
0042 #define HI3798CV200_CRG_NR_CLKS         128
0043
0044 static const struct hisi_fixed_rate_clock hi3798cv200_fixed_rate_clks[] = {
0045     { HISTB_OSC_CLK, "clk_osc", NULL, 0, 24000000, },
0046     { HISTB_APB_CLK, "clk_apb", NULL, 0, 100000000, },
0047     { HISTB_AHB_CLK, "clk_ahb", NULL, 0, 200000000, },
0048     { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
0049     { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
0050     { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
0051     { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
0052     { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
0053     { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
0054     { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
0055     { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
0056     { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
0057     { HI3798CV200_FIXED_166P5M, "166p5m", NULL, 0, 165000000, },
0058     { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
0059     { HI3798CV200_FIXED_250M, "250m", NULL, 0, 250000000, },
0060 };
0061
0062 static const char *const mmc_mux_p[] = {
0063         "100m", "50m", "25m", "200m", "150m" };
0064 static u32 mmc_mux_table[] = {0, 1, 2, 3, 6};
0065
0066 static const char *const comphy_mux_p[] = {
0067         "100m", "25m"};
0068 static u32 comphy_mux_table[] = {2, 3};
0069
0070 static const char *const sdio_mux_p[] = {
0071         "100m", "50m", "150m", "166p5m" };
0072 static u32 sdio_mux_table[] = {0, 1, 2, 3};
0073
0074 static struct hisi_mux_clock hi3798cv200_mux_clks[] = {
0075     { HI3798CV200_MMC_MUX, "mmc_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
0076         CLK_SET_RATE_PARENT, 0xa0, 8, 3, 0, mmc_mux_table, },
0077     { HI3798CV200_COMBPHY0_MUX, "combphy0_mux",
0078         comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
0079         CLK_SET_RATE_PARENT, 0x188, 2, 2, 0, comphy_mux_table, },
0080     { HI3798CV200_COMBPHY1_MUX, "combphy1_mux",
0081         comphy_mux_p, ARRAY_SIZE(comphy_mux_p),
0082         CLK_SET_RATE_PARENT, 0x188, 10, 2, 0, comphy_mux_table, },
0083     { HI3798CV200_SDIO0_MUX, "sdio0_mux", sdio_mux_p,
0084         ARRAY_SIZE(sdio_mux_p), CLK_SET_RATE_PARENT,
0085         0x9c, 8, 2, 0, sdio_mux_table, },
0086 };
0087
0088 static u32 mmc_phase_regvals[] = {0, 1, 2, 3, 4, 5, 6, 7};
0089 static u32 mmc_phase_degrees[] = {0, 45, 90, 135, 180, 225, 270, 315};
0090
0091 static struct hisi_phase_clock hi3798cv200_phase_clks[] = {
0092     { HISTB_MMC_SAMPLE_CLK, "mmc_sample", "clk_mmc_ciu",
0093         CLK_SET_RATE_PARENT, 0xa0, 12, 3, mmc_phase_degrees,
0094         mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
0095     { HISTB_MMC_DRV_CLK, "mmc_drive", "clk_mmc_ciu",
0096         CLK_SET_RATE_PARENT, 0xa0, 16, 3, mmc_phase_degrees,
0097         mmc_phase_regvals, ARRAY_SIZE(mmc_phase_regvals) },
0098 };
0099
0100 static const struct hisi_gate_clock hi3798cv200_gate_clks[] = {
0101     /* UART */
0102     { HISTB_UART2_CLK, "clk_uart2", "75m",
0103         CLK_SET_RATE_PARENT, 0x68, 4, 0, },
0104     /* I2C */
0105     { HISTB_I2C0_CLK, "clk_i2c0", "clk_apb",
0106         CLK_SET_RATE_PARENT, 0x6C, 4, 0, },
0107     { HISTB_I2C1_CLK, "clk_i2c1", "clk_apb",
0108         CLK_SET_RATE_PARENT, 0x6C, 8, 0, },
0109     { HISTB_I2C2_CLK, "clk_i2c2", "clk_apb",
0110         CLK_SET_RATE_PARENT, 0x6C, 12, 0, },
0111     { HISTB_I2C3_CLK, "clk_i2c3", "clk_apb",
0112         CLK_SET_RATE_PARENT, 0x6C, 16, 0, },
0113     { HISTB_I2C4_CLK, "clk_i2c4", "clk_apb",
0114         CLK_SET_RATE_PARENT, 0x6C, 20, 0, },
0115     /* SPI */
0116     { HISTB_SPI0_CLK, "clk_spi0", "clk_apb",
0117         CLK_SET_RATE_PARENT, 0x70, 0, 0, },
0118     /* SDIO */
0119     { HISTB_SDIO0_BIU_CLK, "clk_sdio0_biu", "200m",
0120             CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
0121     { HISTB_SDIO0_CIU_CLK, "clk_sdio0_ciu", "sdio0_mux",
0122         CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
0123     /* EMMC */
0124     { HISTB_MMC_BIU_CLK, "clk_mmc_biu", "200m",
0125         CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
0126     { HISTB_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
0127         CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
0128     /* PCIE*/
0129     { HISTB_PCIE_BUS_CLK, "clk_pcie_bus", "200m",
0130         CLK_SET_RATE_PARENT, 0x18c, 0, 0, },
0131     { HISTB_PCIE_SYS_CLK, "clk_pcie_sys", "100m",
0132         CLK_SET_RATE_PARENT, 0x18c, 1, 0, },
0133     { HISTB_PCIE_PIPE_CLK, "clk_pcie_pipe", "250m",
0134         CLK_SET_RATE_PARENT, 0x18c, 2, 0, },
0135     { HISTB_PCIE_AUX_CLK, "clk_pcie_aux", "24m",
0136         CLK_SET_RATE_PARENT, 0x18c, 3, 0, },
0137     /* Ethernet */
0138     { HI3798CV200_ETH_PUB_CLK, "clk_pub", NULL,
0139         CLK_SET_RATE_PARENT, 0xcc, 5, 0, },
0140     { HI3798CV200_ETH_BUS_CLK, "clk_bus", "clk_pub",
0141         CLK_SET_RATE_PARENT, 0xcc, 0, 0, },
0142     { HI3798CV200_ETH_BUS0_CLK, "clk_bus_m0", "clk_bus",
0143         CLK_SET_RATE_PARENT, 0xcc, 1, 0, },
0144     { HI3798CV200_ETH_BUS1_CLK, "clk_bus_m1", "clk_bus",
0145         CLK_SET_RATE_PARENT, 0xcc, 2, 0, },
0146     { HISTB_ETH0_MAC_CLK, "clk_mac0", "clk_bus_m0",
0147         CLK_SET_RATE_PARENT, 0xcc, 3, 0, },
0148     { HISTB_ETH0_MACIF_CLK, "clk_macif0", "clk_bus_m0",
0149         CLK_SET_RATE_PARENT, 0xcc, 24, 0, },
0150     { HISTB_ETH1_MAC_CLK, "clk_mac1", "clk_bus_m1",
0151         CLK_SET_RATE_PARENT, 0xcc, 4, 0, },
0152     { HISTB_ETH1_MACIF_CLK, "clk_macif1", "clk_bus_m1",
0153         CLK_SET_RATE_PARENT, 0xcc, 25, 0, },
0154     /* COMBPHY0 */
0155     { HISTB_COMBPHY0_CLK, "clk_combphy0", "combphy0_mux",
0156         CLK_SET_RATE_PARENT, 0x188, 0, 0, },
0157     /* COMBPHY1 */
0158     { HISTB_COMBPHY1_CLK, "clk_combphy1", "combphy1_mux",
0159         CLK_SET_RATE_PARENT, 0x188, 8, 0, },
0160     /* USB2 */
0161     { HISTB_USB2_BUS_CLK, "clk_u2_bus", "clk_ahb",
0162         CLK_SET_RATE_PARENT, 0xb8, 0, 0, },
0163     { HISTB_USB2_PHY_CLK, "clk_u2_phy", "60m",
0164         CLK_SET_RATE_PARENT, 0xb8, 4, 0, },
0165     { HISTB_USB2_12M_CLK, "clk_u2_12m", "12m",
0166         CLK_SET_RATE_PARENT, 0xb8, 2, 0 },
0167     { HISTB_USB2_48M_CLK, "clk_u2_48m", "48m",
0168         CLK_SET_RATE_PARENT, 0xb8, 1, 0 },
0169     { HISTB_USB2_UTMI_CLK, "clk_u2_utmi", "60m",
0170         CLK_SET_RATE_PARENT, 0xb8, 5, 0 },
0171     { HISTB_USB2_OTG_UTMI_CLK, "clk_u2_otg_utmi", "60m",
0172         CLK_SET_RATE_PARENT, 0xb8, 3, 0 },
0173     { HISTB_USB2_PHY1_REF_CLK, "clk_u2_phy1_ref", "24m",
0174         CLK_SET_RATE_PARENT, 0xbc, 0, 0 },
0175     { HISTB_USB2_PHY2_REF_CLK, "clk_u2_phy2_ref", "24m",
0176         CLK_SET_RATE_PARENT, 0xbc, 2, 0 },
0177     /* USB3 */
0178     { HISTB_USB3_BUS_CLK, "clk_u3_bus", NULL,
0179         CLK_SET_RATE_PARENT, 0xb0, 0, 0 },
0180     { HISTB_USB3_UTMI_CLK, "clk_u3_utmi", NULL,
0181         CLK_SET_RATE_PARENT, 0xb0, 4, 0 },
0182     { HISTB_USB3_PIPE_CLK, "clk_u3_pipe", NULL,
0183         CLK_SET_RATE_PARENT, 0xb0, 3, 0 },
0184     { HISTB_USB3_SUSPEND_CLK, "clk_u3_suspend", NULL,
0185         CLK_SET_RATE_PARENT, 0xb0, 2, 0 },
0186     { HISTB_USB3_BUS_CLK1, "clk_u3_bus1", NULL,
0187         CLK_SET_RATE_PARENT, 0xb0, 16, 0 },
0188     { HISTB_USB3_UTMI_CLK1, "clk_u3_utmi1", NULL,
0189         CLK_SET_RATE_PARENT, 0xb0, 20, 0 },
0190     { HISTB_USB3_PIPE_CLK1, "clk_u3_pipe1", NULL,
0191         CLK_SET_RATE_PARENT, 0xb0, 19, 0 },
0192     { HISTB_USB3_SUSPEND_CLK1, "clk_u3_suspend1", NULL,
0193         CLK_SET_RATE_PARENT, 0xb0, 18, 0 },
0194 };
0195
0196 static struct hisi_clock_data *hi3798cv200_clk_register(
0197                 struct platform_device *pdev)
0198 {
0199     struct hisi_clock_data *clk_data;
0200     int ret;
0201
0202     clk_data = hisi_clk_alloc(pdev, HI3798CV200_CRG_NR_CLKS);
0203     if (!clk_data)
0204         return ERR_PTR(-ENOMEM);
0205
0206     /* hisi_phase_clock is resource managed */
0207     ret = hisi_clk_register_phase(&pdev->dev,
0208                 hi3798cv200_phase_clks,
0209                 ARRAY_SIZE(hi3798cv200_phase_clks),
0210                 clk_data);
0211     if (ret)
0212         return ERR_PTR(ret);
0213
0214     ret = hisi_clk_register_fixed_rate(hi3798cv200_fixed_rate_clks,
0215                      ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
0216                      clk_data);
0217     if (ret)
0218         return ERR_PTR(ret);
0219
0220     ret = hisi_clk_register_mux(hi3798cv200_mux_clks,
0221                 ARRAY_SIZE(hi3798cv200_mux_clks),
0222                 clk_data);
0223     if (ret)
0224         goto unregister_fixed_rate;
0225
0226     ret = hisi_clk_register_gate(hi3798cv200_gate_clks,
0227                 ARRAY_SIZE(hi3798cv200_gate_clks),
0228                 clk_data);
0229     if (ret)
0230         goto unregister_mux;
0231
0232     ret = of_clk_add_provider(pdev->dev.of_node,
0233             of_clk_src_onecell_get, &clk_data->clk_data);
0234     if (ret)
0235         goto unregister_gate;
0236
0237     return clk_data;
0238
0239 unregister_gate:
0240     hisi_clk_unregister_gate(hi3798cv200_gate_clks,
0241                 ARRAY_SIZE(hi3798cv200_gate_clks),
0242                 clk_data);
0243 unregister_mux:
0244     hisi_clk_unregister_mux(hi3798cv200_mux_clks,
0245                 ARRAY_SIZE(hi3798cv200_mux_clks),
0246                 clk_data);
0247 unregister_fixed_rate:
0248     hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
0249                 ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
0250                 clk_data);
0251     return ERR_PTR(ret);
0252 }
0253
0254 static void hi3798cv200_clk_unregister(struct platform_device *pdev)
0255 {
0256     struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
0257
0258     of_clk_del_provider(pdev->dev.of_node);
0259
0260     hisi_clk_unregister_gate(hi3798cv200_gate_clks,
0261                 ARRAY_SIZE(hi3798cv200_gate_clks),
0262                 crg->clk_data);
0263     hisi_clk_unregister_mux(hi3798cv200_mux_clks,
0264                 ARRAY_SIZE(hi3798cv200_mux_clks),
0265                 crg->clk_data);
0266     hisi_clk_unregister_fixed_rate(hi3798cv200_fixed_rate_clks,
0267                 ARRAY_SIZE(hi3798cv200_fixed_rate_clks),
0268                 crg->clk_data);
0269 }
0270
0271 static const struct hisi_crg_funcs hi3798cv200_crg_funcs = {
0272     .register_clks = hi3798cv200_clk_register,
0273     .unregister_clks = hi3798cv200_clk_unregister,
0274 };
0275
0276 /* hi3798CV200 sysctrl CRG */
0277
0278 #define HI3798CV200_SYSCTRL_NR_CLKS 16
0279
0280 static const struct hisi_gate_clock hi3798cv200_sysctrl_gate_clks[] = {
0281     { HISTB_IR_CLK, "clk_ir", "24m",
0282         CLK_SET_RATE_PARENT, 0x48, 4, 0, },
0283     { HISTB_TIMER01_CLK, "clk_timer01", "24m",
0284         CLK_SET_RATE_PARENT, 0x48, 6, 0, },
0285     { HISTB_UART0_CLK, "clk_uart0", "75m",
0286         CLK_SET_RATE_PARENT, 0x48, 10, 0, },
0287 };
0288
0289 static struct hisi_clock_data *hi3798cv200_sysctrl_clk_register(
0290                     struct platform_device *pdev)
0291 {
0292     struct hisi_clock_data *clk_data;
0293     int ret;
0294
0295     clk_data = hisi_clk_alloc(pdev, HI3798CV200_SYSCTRL_NR_CLKS);
0296     if (!clk_data)
0297         return ERR_PTR(-ENOMEM);
0298
0299     ret = hisi_clk_register_gate(hi3798cv200_sysctrl_gate_clks,
0300                 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
0301                 clk_data);
0302     if (ret)
0303         return ERR_PTR(ret);
0304
0305     ret = of_clk_add_provider(pdev->dev.of_node,
0306             of_clk_src_onecell_get, &clk_data->clk_data);
0307     if (ret)
0308         goto unregister_gate;
0309
0310     return clk_data;
0311
0312 unregister_gate:
0313     hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
0314                 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
0315                 clk_data);
0316     return ERR_PTR(ret);
0317 }
0318
0319 static void hi3798cv200_sysctrl_clk_unregister(struct platform_device *pdev)
0320 {
0321     struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
0322
0323     of_clk_del_provider(pdev->dev.of_node);
0324
0325     hisi_clk_unregister_gate(hi3798cv200_sysctrl_gate_clks,
0326                 ARRAY_SIZE(hi3798cv200_sysctrl_gate_clks),
0327                 crg->clk_data);
0328 }
0329
0330 static const struct hisi_crg_funcs hi3798cv200_sysctrl_funcs = {
0331     .register_clks = hi3798cv200_sysctrl_clk_register,
0332     .unregister_clks = hi3798cv200_sysctrl_clk_unregister,
0333 };
0334
0335 static const struct of_device_id hi3798cv200_crg_match_table[] = {
0336     { .compatible = "hisilicon,hi3798cv200-crg",
0337         .data = &hi3798cv200_crg_funcs },
0338     { .compatible = "hisilicon,hi3798cv200-sysctrl",
0339         .data = &hi3798cv200_sysctrl_funcs },
0340     { }
0341 };
0342 MODULE_DEVICE_TABLE(of, hi3798cv200_crg_match_table);
0343
0344 static int hi3798cv200_crg_probe(struct platform_device *pdev)
0345 {
0346     struct hisi_crg_dev *crg;
0347
0348     crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
0349     if (!crg)
0350         return -ENOMEM;
0351
0352     crg->funcs = of_device_get_match_data(&pdev->dev);
0353     if (!crg->funcs)
0354         return -ENOENT;
0355
0356     crg->rstc = hisi_reset_init(pdev);
0357     if (!crg->rstc)
0358         return -ENOMEM;
0359
0360     crg->clk_data = crg->funcs->register_clks(pdev);
0361     if (IS_ERR(crg->clk_data)) {
0362         hisi_reset_exit(crg->rstc);
0363         return PTR_ERR(crg->clk_data);
0364     }
0365
0366     platform_set_drvdata(pdev, crg);
0367     return 0;
0368 }
0369
0370 static int hi3798cv200_crg_remove(struct platform_device *pdev)
0371 {
0372     struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
0373
0374     hisi_reset_exit(crg->rstc);
0375     crg->funcs->unregister_clks(pdev);
0376     return 0;
0377 }
0378
0379 static struct platform_driver hi3798cv200_crg_driver = {
0380     .probe          = hi3798cv200_crg_probe,
0381     .remove     = hi3798cv200_crg_remove,
0382     .driver         = {
0383         .name   = "hi3798cv200-crg",
0384         .of_match_table = hi3798cv200_crg_match_table,
0385     },
0386 };
0387
0388 static int __init hi3798cv200_crg_init(void)
0389 {
0390     return platform_driver_register(&hi3798cv200_crg_driver);
0391 }
0392 core_initcall(hi3798cv200_crg_init);
0393
0394 static void __exit hi3798cv200_crg_exit(void)
0395 {
0396     platform_driver_unregister(&hi3798cv200_crg_driver);
0397 }
0398 module_exit(hi3798cv200_crg_exit);
0399
0400 MODULE_LICENSE("GPL v2");
0401 MODULE_DESCRIPTION("HiSilicon Hi3798CV200 CRG Driver");