clk/hisilicon/clk.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Hisilicon Hi3620 clock gate driver
0004  *
0005  * Copyright (c) 2012-2013 Hisilicon Limited.
0006  * Copyright (c) 2012-2013 Linaro Limited.
0007  *
0008  * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
0009  *     Xin Li <li.xin@linaro.org>
0010  */
0011
0012 #ifndef __HISI_CLK_H
0013 #define __HISI_CLK_H
0014
0015 #include <linux/clk-provider.h>
0016 #include <linux/io.h>
0017 #include <linux/spinlock.h>
0018
0019 struct platform_device;
0020
0021 struct hisi_clock_data {
0022     struct clk_onecell_data clk_data;
0023     void __iomem        *base;
0024 };
0025
0026 struct hisi_fixed_rate_clock {
0027     unsigned int        id;
0028     char            *name;
0029     const char      *parent_name;
0030     unsigned long       flags;
0031     unsigned long       fixed_rate;
0032 };
0033
0034 struct hisi_fixed_factor_clock {
0035     unsigned int        id;
0036     char            *name;
0037     const char      *parent_name;
0038     unsigned long       mult;
0039     unsigned long       div;
0040     unsigned long       flags;
0041 };
0042
0043 struct hisi_mux_clock {
0044     unsigned int        id;
0045     const char      *name;
0046     const char      *const *parent_names;
0047     u8          num_parents;
0048     unsigned long       flags;
0049     unsigned long       offset;
0050     u8          shift;
0051     u8          width;
0052     u8          mux_flags;
0053     const u32       *table;
0054     const char      *alias;
0055 };
0056
0057 struct hisi_phase_clock {
0058     unsigned int        id;
0059     const char      *name;
0060     const char      *parent_names;
0061     unsigned long       flags;
0062     unsigned long       offset;
0063     u8          shift;
0064     u8          width;
0065     u32         *phase_degrees;
0066     u32         *phase_regvals;
0067     u8          phase_num;
0068 };
0069
0070 struct hisi_divider_clock {
0071     unsigned int        id;
0072     const char      *name;
0073     const char      *parent_name;
0074     unsigned long       flags;
0075     unsigned long       offset;
0076     u8          shift;
0077     u8          width;
0078     u8          div_flags;
0079     struct clk_div_table    *table;
0080     const char      *alias;
0081 };
0082
0083 struct hi6220_divider_clock {
0084     unsigned int        id;
0085     const char      *name;
0086     const char      *parent_name;
0087     unsigned long       flags;
0088     unsigned long       offset;
0089     u8          shift;
0090     u8          width;
0091     u32         mask_bit;
0092     const char      *alias;
0093 };
0094
0095 struct hisi_gate_clock {
0096     unsigned int        id;
0097     const char      *name;
0098     const char      *parent_name;
0099     unsigned long       flags;
0100     unsigned long       offset;
0101     u8          bit_idx;
0102     u8          gate_flags;
0103     const char      *alias;
0104 };
0105
0106 struct clk *hisi_register_clkgate_sep(struct device *, const char *,
0107                 const char *, unsigned long,
0108                 void __iomem *, u8,
0109                 u8, spinlock_t *);
0110 struct clk *hi6220_register_clkdiv(struct device *dev, const char *name,
0111     const char *parent_name, unsigned long flags, void __iomem *reg,
0112     u8 shift, u8 width, u32 mask_bit, spinlock_t *lock);
0113
0114 struct hisi_clock_data *hisi_clk_alloc(struct platform_device *, int);
0115 struct hisi_clock_data *hisi_clk_init(struct device_node *, int);
0116 int hisi_clk_register_fixed_rate(const struct hisi_fixed_rate_clock *,
0117                 int, struct hisi_clock_data *);
0118 int hisi_clk_register_fixed_factor(const struct hisi_fixed_factor_clock *,
0119                 int, struct hisi_clock_data *);
0120 int hisi_clk_register_mux(const struct hisi_mux_clock *, int,
0121                 struct hisi_clock_data *);
0122 struct clk *clk_register_hisi_phase(struct device *dev,
0123                 const struct hisi_phase_clock *clks,
0124                 void __iomem *base, spinlock_t *lock);
0125 int hisi_clk_register_phase(struct device *dev,
0126                 const struct hisi_phase_clock *clks,
0127                 int nums, struct hisi_clock_data *data);
0128 int hisi_clk_register_divider(const struct hisi_divider_clock *,
0129                 int, struct hisi_clock_data *);
0130 int hisi_clk_register_gate(const struct hisi_gate_clock *,
0131                 int, struct hisi_clock_data *);
0132 void hisi_clk_register_gate_sep(const struct hisi_gate_clock *,
0133                 int, struct hisi_clock_data *);
0134 void hi6220_clk_register_divider(const struct hi6220_divider_clock *,
0135                 int, struct hisi_clock_data *);
0136
0137 #define hisi_clk_unregister(type) \
0138 static inline \
0139 void hisi_clk_unregister_##type(const struct hisi_##type##_clock *clks, \
0140                 int nums, struct hisi_clock_data *data) \
0141 { \
0142     struct clk **clocks = data->clk_data.clks; \
0143     int i; \
0144     for (i = 0; i < nums; i++) { \
0145         int id = clks[i].id; \
0146         if (clocks[id])  \
0147             clk_unregister_##type(clocks[id]); \
0148     } \
0149 }
0150
0151 hisi_clk_unregister(fixed_rate)
0152 hisi_clk_unregister(fixed_factor)
0153 hisi_clk_unregister(mux)
0154 hisi_clk_unregister(divider)
0155 hisi_clk_unregister(gate)
0156
0157 #endif  /* __HISI_CLK_H */