clk/hisilicon/clk-hix5hd2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 Linaro Ltd.
0004  * Copyright (c) 2014 Hisilicon Limited.
0005  */
0006
0007 #include <linux/of_address.h>
0008 #include <dt-bindings/clock/hix5hd2-clock.h>
0009 #include <linux/slab.h>
0010 #include <linux/delay.h>
0011 #include "clk.h"
0012
0013 static struct hisi_fixed_rate_clock hix5hd2_fixed_rate_clks[] __initdata = {
0014     { HIX5HD2_FIXED_1200M, "1200m", NULL, 0, 1200000000, },
0015     { HIX5HD2_FIXED_400M, "400m", NULL, 0, 400000000, },
0016     { HIX5HD2_FIXED_48M, "48m", NULL, 0, 48000000, },
0017     { HIX5HD2_FIXED_24M, "24m", NULL, 0, 24000000, },
0018     { HIX5HD2_FIXED_600M, "600m", NULL, 0, 600000000, },
0019     { HIX5HD2_FIXED_300M, "300m", NULL, 0, 300000000, },
0020     { HIX5HD2_FIXED_75M, "75m", NULL, 0, 75000000, },
0021     { HIX5HD2_FIXED_200M, "200m", NULL, 0, 200000000, },
0022     { HIX5HD2_FIXED_100M, "100m", NULL, 0, 100000000, },
0023     { HIX5HD2_FIXED_40M, "40m", NULL, 0, 40000000, },
0024     { HIX5HD2_FIXED_150M, "150m", NULL, 0, 150000000, },
0025     { HIX5HD2_FIXED_1728M, "1728m", NULL, 0, 1728000000, },
0026     { HIX5HD2_FIXED_28P8M, "28p8m", NULL, 0, 28000000, },
0027     { HIX5HD2_FIXED_432M, "432m", NULL, 0, 432000000, },
0028     { HIX5HD2_FIXED_345P6M, "345p6m", NULL, 0, 345000000, },
0029     { HIX5HD2_FIXED_288M, "288m", NULL, 0, 288000000, },
0030     { HIX5HD2_FIXED_60M,    "60m", NULL, 0, 60000000, },
0031     { HIX5HD2_FIXED_750M, "750m", NULL, 0, 750000000, },
0032     { HIX5HD2_FIXED_500M, "500m", NULL, 0, 500000000, },
0033     { HIX5HD2_FIXED_54M,    "54m", NULL, 0, 54000000, },
0034     { HIX5HD2_FIXED_27M, "27m", NULL, 0, 27000000, },
0035     { HIX5HD2_FIXED_1500M, "1500m", NULL, 0, 1500000000, },
0036     { HIX5HD2_FIXED_375M, "375m", NULL, 0, 375000000, },
0037     { HIX5HD2_FIXED_187M, "187m", NULL, 0, 187000000, },
0038     { HIX5HD2_FIXED_250M, "250m", NULL, 0, 250000000, },
0039     { HIX5HD2_FIXED_125M, "125m", NULL, 0, 125000000, },
0040     { HIX5HD2_FIXED_2P02M, "2m", NULL, 0, 2000000, },
0041     { HIX5HD2_FIXED_50M, "50m", NULL, 0, 50000000, },
0042     { HIX5HD2_FIXED_25M, "25m", NULL, 0, 25000000, },
0043     { HIX5HD2_FIXED_83M, "83m", NULL, 0, 83333333, },
0044 };
0045
0046 static const char *const sfc_mux_p[] __initconst = {
0047         "24m", "150m", "200m", "100m", "75m", };
0048 static u32 sfc_mux_table[] = {0, 4, 5, 6, 7};
0049
0050 static const char *const sdio_mux_p[] __initconst = {
0051         "75m", "100m", "50m", "15m", };
0052 static u32 sdio_mux_table[] = {0, 1, 2, 3};
0053
0054 static const char *const fephy_mux_p[] __initconst = { "25m", "125m"};
0055 static u32 fephy_mux_table[] = {0, 1};
0056
0057
0058 static struct hisi_mux_clock hix5hd2_mux_clks[] __initdata = {
0059     { HIX5HD2_SFC_MUX, "sfc_mux", sfc_mux_p, ARRAY_SIZE(sfc_mux_p),
0060         CLK_SET_RATE_PARENT, 0x5c, 8, 3, 0, sfc_mux_table, },
0061     { HIX5HD2_MMC_MUX, "mmc_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
0062         CLK_SET_RATE_PARENT, 0xa0, 8, 2, 0, sdio_mux_table, },
0063     { HIX5HD2_SD_MUX, "sd_mux", sdio_mux_p, ARRAY_SIZE(sdio_mux_p),
0064         CLK_SET_RATE_PARENT, 0x9c, 8, 2, 0, sdio_mux_table, },
0065     { HIX5HD2_FEPHY_MUX, "fephy_mux",
0066         fephy_mux_p, ARRAY_SIZE(fephy_mux_p),
0067         CLK_SET_RATE_PARENT, 0x120, 8, 2, 0, fephy_mux_table, },
0068 };
0069
0070 static struct hisi_gate_clock hix5hd2_gate_clks[] __initdata = {
0071     /* sfc */
0072     { HIX5HD2_SFC_CLK, "clk_sfc", "sfc_mux",
0073         CLK_SET_RATE_PARENT, 0x5c, 0, 0, },
0074     { HIX5HD2_SFC_RST, "rst_sfc", "clk_sfc",
0075         CLK_SET_RATE_PARENT, 0x5c, 4, CLK_GATE_SET_TO_DISABLE, },
0076     /* sdio0 */
0077     { HIX5HD2_SD_BIU_CLK, "clk_sd_biu", "200m",
0078         CLK_SET_RATE_PARENT, 0x9c, 0, 0, },
0079     { HIX5HD2_SD_CIU_CLK, "clk_sd_ciu", "sd_mux",
0080         CLK_SET_RATE_PARENT, 0x9c, 1, 0, },
0081     { HIX5HD2_SD_CIU_RST, "rst_sd_ciu", "clk_sd_ciu",
0082         CLK_SET_RATE_PARENT, 0x9c, 4, CLK_GATE_SET_TO_DISABLE, },
0083     /* sdio1 */
0084     { HIX5HD2_MMC_BIU_CLK, "clk_mmc_biu", "200m",
0085         CLK_SET_RATE_PARENT, 0xa0, 0, 0, },
0086     { HIX5HD2_MMC_CIU_CLK, "clk_mmc_ciu", "mmc_mux",
0087         CLK_SET_RATE_PARENT, 0xa0, 1, 0, },
0088     { HIX5HD2_MMC_CIU_RST, "rst_mmc_ciu", "clk_mmc_ciu",
0089         CLK_SET_RATE_PARENT, 0xa0, 4, CLK_GATE_SET_TO_DISABLE, },
0090     /* gsf */
0091     { HIX5HD2_FWD_BUS_CLK, "clk_fwd_bus", NULL, 0, 0xcc, 0, 0, },
0092     { HIX5HD2_FWD_SYS_CLK, "clk_fwd_sys", "clk_fwd_bus", 0, 0xcc, 5, 0, },
0093     { HIX5HD2_MAC0_PHY_CLK, "clk_fephy", "clk_fwd_sys",
0094          CLK_SET_RATE_PARENT, 0x120, 0, 0, },
0095     /* wdg0 */
0096     { HIX5HD2_WDG0_CLK, "clk_wdg0", "24m",
0097         CLK_SET_RATE_PARENT, 0x178, 0, 0, },
0098     { HIX5HD2_WDG0_RST, "rst_wdg0", "clk_wdg0",
0099         CLK_SET_RATE_PARENT, 0x178, 4, CLK_GATE_SET_TO_DISABLE, },
0100     /* I2C */
0101     {HIX5HD2_I2C0_CLK, "clk_i2c0", "100m",
0102          CLK_SET_RATE_PARENT, 0x06c, 4, 0, },
0103     {HIX5HD2_I2C0_RST, "rst_i2c0", "clk_i2c0",
0104          CLK_SET_RATE_PARENT, 0x06c, 5, CLK_GATE_SET_TO_DISABLE, },
0105     {HIX5HD2_I2C1_CLK, "clk_i2c1", "100m",
0106          CLK_SET_RATE_PARENT, 0x06c, 8, 0, },
0107     {HIX5HD2_I2C1_RST, "rst_i2c1", "clk_i2c1",
0108          CLK_SET_RATE_PARENT, 0x06c, 9, CLK_GATE_SET_TO_DISABLE, },
0109     {HIX5HD2_I2C2_CLK, "clk_i2c2", "100m",
0110          CLK_SET_RATE_PARENT, 0x06c, 12, 0, },
0111     {HIX5HD2_I2C2_RST, "rst_i2c2", "clk_i2c2",
0112          CLK_SET_RATE_PARENT, 0x06c, 13, CLK_GATE_SET_TO_DISABLE, },
0113     {HIX5HD2_I2C3_CLK, "clk_i2c3", "100m",
0114          CLK_SET_RATE_PARENT, 0x06c, 16, 0, },
0115     {HIX5HD2_I2C3_RST, "rst_i2c3", "clk_i2c3",
0116          CLK_SET_RATE_PARENT, 0x06c, 17, CLK_GATE_SET_TO_DISABLE, },
0117     {HIX5HD2_I2C4_CLK, "clk_i2c4", "100m",
0118          CLK_SET_RATE_PARENT, 0x06c, 20, 0, },
0119     {HIX5HD2_I2C4_RST, "rst_i2c4", "clk_i2c4",
0120          CLK_SET_RATE_PARENT, 0x06c, 21, CLK_GATE_SET_TO_DISABLE, },
0121     {HIX5HD2_I2C5_CLK, "clk_i2c5", "100m",
0122          CLK_SET_RATE_PARENT, 0x06c, 0, 0, },
0123     {HIX5HD2_I2C5_RST, "rst_i2c5", "clk_i2c5",
0124          CLK_SET_RATE_PARENT, 0x06c, 1, CLK_GATE_SET_TO_DISABLE, },
0125 };
0126
0127 enum hix5hd2_clk_type {
0128     TYPE_COMPLEX,
0129     TYPE_ETHER,
0130 };
0131
0132 struct hix5hd2_complex_clock {
0133     const char  *name;
0134     const char  *parent_name;
0135     u32     id;
0136     u32     ctrl_reg;
0137     u32     ctrl_clk_mask;
0138     u32     ctrl_rst_mask;
0139     u32     phy_reg;
0140     u32     phy_clk_mask;
0141     u32     phy_rst_mask;
0142     enum hix5hd2_clk_type type;
0143 };
0144
0145 struct hix5hd2_clk_complex {
0146     struct clk_hw   hw;
0147     u32     id;
0148     void __iomem    *ctrl_reg;
0149     u32     ctrl_clk_mask;
0150     u32     ctrl_rst_mask;
0151     void __iomem    *phy_reg;
0152     u32     phy_clk_mask;
0153     u32     phy_rst_mask;
0154 };
0155
0156 static struct hix5hd2_complex_clock hix5hd2_complex_clks[] __initdata = {
0157     {"clk_mac0", "clk_fephy", HIX5HD2_MAC0_CLK,
0158         0xcc, 0xa, 0x500, 0x120, 0, 0x10, TYPE_ETHER},
0159     {"clk_mac1", "clk_fwd_sys", HIX5HD2_MAC1_CLK,
0160         0xcc, 0x14, 0xa00, 0x168, 0x2, 0, TYPE_ETHER},
0161     {"clk_sata", NULL, HIX5HD2_SATA_CLK,
0162         0xa8, 0x1f, 0x300, 0xac, 0x1, 0x0, TYPE_COMPLEX},
0163     {"clk_usb", NULL, HIX5HD2_USB_CLK,
0164         0xb8, 0xff, 0x3f000, 0xbc, 0x7, 0x3f00, TYPE_COMPLEX},
0165 };
0166
0167 #define to_complex_clk(_hw) container_of(_hw, struct hix5hd2_clk_complex, hw)
0168
0169 static int clk_ether_prepare(struct clk_hw *hw)
0170 {
0171     struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
0172     u32 val;
0173
0174     val = readl_relaxed(clk->ctrl_reg);
0175     val |= clk->ctrl_clk_mask | clk->ctrl_rst_mask;
0176     writel_relaxed(val, clk->ctrl_reg);
0177     val &= ~(clk->ctrl_rst_mask);
0178     writel_relaxed(val, clk->ctrl_reg);
0179
0180     val = readl_relaxed(clk->phy_reg);
0181     val |= clk->phy_clk_mask;
0182     val &= ~(clk->phy_rst_mask);
0183     writel_relaxed(val, clk->phy_reg);
0184     mdelay(10);
0185
0186     val &= ~(clk->phy_clk_mask);
0187     val |= clk->phy_rst_mask;
0188     writel_relaxed(val, clk->phy_reg);
0189     mdelay(10);
0190
0191     val |= clk->phy_clk_mask;
0192     val &= ~(clk->phy_rst_mask);
0193     writel_relaxed(val, clk->phy_reg);
0194     mdelay(30);
0195     return 0;
0196 }
0197
0198 static void clk_ether_unprepare(struct clk_hw *hw)
0199 {
0200     struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
0201     u32 val;
0202
0203     val = readl_relaxed(clk->ctrl_reg);
0204     val &= ~(clk->ctrl_clk_mask);
0205     writel_relaxed(val, clk->ctrl_reg);
0206 }
0207
0208 static const struct clk_ops clk_ether_ops = {
0209     .prepare = clk_ether_prepare,
0210     .unprepare = clk_ether_unprepare,
0211 };
0212
0213 static int clk_complex_enable(struct clk_hw *hw)
0214 {
0215     struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
0216     u32 val;
0217
0218     val = readl_relaxed(clk->ctrl_reg);
0219     val |= clk->ctrl_clk_mask;
0220     val &= ~(clk->ctrl_rst_mask);
0221     writel_relaxed(val, clk->ctrl_reg);
0222
0223     val = readl_relaxed(clk->phy_reg);
0224     val |= clk->phy_clk_mask;
0225     val &= ~(clk->phy_rst_mask);
0226     writel_relaxed(val, clk->phy_reg);
0227
0228     return 0;
0229 }
0230
0231 static void clk_complex_disable(struct clk_hw *hw)
0232 {
0233     struct hix5hd2_clk_complex *clk = to_complex_clk(hw);
0234     u32 val;
0235
0236     val = readl_relaxed(clk->ctrl_reg);
0237     val |= clk->ctrl_rst_mask;
0238     val &= ~(clk->ctrl_clk_mask);
0239     writel_relaxed(val, clk->ctrl_reg);
0240
0241     val = readl_relaxed(clk->phy_reg);
0242     val |= clk->phy_rst_mask;
0243     val &= ~(clk->phy_clk_mask);
0244     writel_relaxed(val, clk->phy_reg);
0245 }
0246
0247 static const struct clk_ops clk_complex_ops = {
0248     .enable = clk_complex_enable,
0249     .disable = clk_complex_disable,
0250 };
0251
0252 static void __init
0253 hix5hd2_clk_register_complex(struct hix5hd2_complex_clock *clks, int nums,
0254                  struct hisi_clock_data *data)
0255 {
0256     void __iomem *base = data->base;
0257     int i;
0258
0259     for (i = 0; i < nums; i++) {
0260         struct hix5hd2_clk_complex *p_clk;
0261         struct clk *clk;
0262         struct clk_init_data init;
0263
0264         p_clk = kzalloc(sizeof(*p_clk), GFP_KERNEL);
0265         if (!p_clk)
0266             return;
0267
0268         init.name = clks[i].name;
0269         if (clks[i].type == TYPE_ETHER)
0270             init.ops = &clk_ether_ops;
0271         else
0272             init.ops = &clk_complex_ops;
0273
0274         init.flags = 0;
0275         init.parent_names =
0276             (clks[i].parent_name ? &clks[i].parent_name : NULL);
0277         init.num_parents = (clks[i].parent_name ? 1 : 0);
0278
0279         p_clk->ctrl_reg = base + clks[i].ctrl_reg;
0280         p_clk->ctrl_clk_mask = clks[i].ctrl_clk_mask;
0281         p_clk->ctrl_rst_mask = clks[i].ctrl_rst_mask;
0282         p_clk->phy_reg = base + clks[i].phy_reg;
0283         p_clk->phy_clk_mask = clks[i].phy_clk_mask;
0284         p_clk->phy_rst_mask = clks[i].phy_rst_mask;
0285         p_clk->hw.init = &init;
0286
0287         clk = clk_register(NULL, &p_clk->hw);
0288         if (IS_ERR(clk)) {
0289             kfree(p_clk);
0290             pr_err("%s: failed to register clock %s\n",
0291                    __func__, clks[i].name);
0292             continue;
0293         }
0294
0295         data->clk_data.clks[clks[i].id] = clk;
0296     }
0297 }
0298
0299 static void __init hix5hd2_clk_init(struct device_node *np)
0300 {
0301     struct hisi_clock_data *clk_data;
0302
0303     clk_data = hisi_clk_init(np, HIX5HD2_NR_CLKS);
0304     if (!clk_data)
0305         return;
0306
0307     hisi_clk_register_fixed_rate(hix5hd2_fixed_rate_clks,
0308                      ARRAY_SIZE(hix5hd2_fixed_rate_clks),
0309                      clk_data);
0310     hisi_clk_register_mux(hix5hd2_mux_clks, ARRAY_SIZE(hix5hd2_mux_clks),
0311                     clk_data);
0312     hisi_clk_register_gate(hix5hd2_gate_clks,
0313             ARRAY_SIZE(hix5hd2_gate_clks), clk_data);
0314     hix5hd2_clk_register_complex(hix5hd2_complex_clks,
0315                      ARRAY_SIZE(hix5hd2_complex_clks),
0316                      clk_data);
0317 }
0318
0319 CLK_OF_DECLARE(hix5hd2_clk, "hisilicon,hix5hd2-clock", hix5hd2_clk_init);