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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Hisilicon Hi6220 clock driver
0004  *
0005  * Copyright (c) 2015 Hisilicon Limited.
0006  *
0007  * Author: Bintian Wang <bintian.wang@huawei.com>
0008  */
0009 
0010 #include <linux/kernel.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/clkdev.h>
0013 #include <linux/io.h>
0014 #include <linux/of.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_device.h>
0017 #include <linux/slab.h>
0018 
0019 #include <dt-bindings/clock/hi6220-clock.h>
0020 
0021 #include "clk.h"
0022 
0023 
0024 /* clocks in AO (always on) controller */
0025 static struct hisi_fixed_rate_clock hi6220_fixed_rate_clks[] __initdata = {
0026     { HI6220_REF32K,    "ref32k",   NULL, 0, 32764,     },
0027     { HI6220_CLK_TCXO,  "clk_tcxo", NULL, 0, 19200000,  },
0028     { HI6220_MMC1_PAD,  "mmc1_pad", NULL, 0, 100000000, },
0029     { HI6220_MMC2_PAD,  "mmc2_pad", NULL, 0, 100000000, },
0030     { HI6220_MMC0_PAD,  "mmc0_pad", NULL, 0, 200000000, },
0031     { HI6220_PLL_BBP,   "bbppll0",  NULL, 0, 245760000, },
0032     { HI6220_PLL_GPU,   "gpupll",   NULL, 0, 1000000000,},
0033     { HI6220_PLL1_DDR,  "ddrpll1",  NULL, 0, 1066000000,},
0034     { HI6220_PLL_SYS,   "syspll",   NULL, 0, 1190400000,},
0035     { HI6220_PLL_SYS_MEDIA, "media_syspll", NULL, 0, 1190400000,},
0036     { HI6220_DDR_SRC,   "ddr_sel_src",  NULL, 0, 1200000000,},
0037     { HI6220_PLL_MEDIA, "media_pll",    NULL, 0, 1440000000,},
0038     { HI6220_PLL_DDR,   "ddrpll0",      NULL, 0, 1600000000,},
0039 };
0040 
0041 static struct hisi_fixed_factor_clock hi6220_fixed_factor_clks[] __initdata = {
0042     { HI6220_300M,         "clk_300m",    "syspll",          1, 4, 0, },
0043     { HI6220_150M,         "clk_150m",    "clk_300m",        1, 2, 0, },
0044     { HI6220_PICOPHY_SRC,  "picophy_src", "clk_150m",        1, 4, 0, },
0045     { HI6220_MMC0_SRC_SEL, "mmc0srcsel",  "mmc0_sel",        1, 8, 0, },
0046     { HI6220_MMC1_SRC_SEL, "mmc1srcsel",  "mmc1_sel",        1, 8, 0, },
0047     { HI6220_MMC2_SRC_SEL, "mmc2srcsel",  "mmc2_sel",        1, 8, 0, },
0048     { HI6220_VPU_CODEC,    "vpucodec",    "codec_jpeg_aclk", 1, 2, 0, },
0049     { HI6220_MMC0_SMP,     "mmc0_sample", "mmc0_sel",        1, 8, 0, },
0050     { HI6220_MMC1_SMP,     "mmc1_sample", "mmc1_sel",        1, 8, 0, },
0051     { HI6220_MMC2_SMP,     "mmc2_sample", "mmc2_sel",        1, 8, 0, },
0052 };
0053 
0054 static struct hisi_gate_clock hi6220_separated_gate_clks_ao[] __initdata = {
0055     { HI6220_WDT0_PCLK,   "wdt0_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 12, 0, },
0056     { HI6220_WDT1_PCLK,   "wdt1_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 13, 0, },
0057     { HI6220_WDT2_PCLK,   "wdt2_pclk",   "ref32k",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 14, 0, },
0058     { HI6220_TIMER0_PCLK, "timer0_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 15, 0, },
0059     { HI6220_TIMER1_PCLK, "timer1_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 16, 0, },
0060     { HI6220_TIMER2_PCLK, "timer2_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 17, 0, },
0061     { HI6220_TIMER3_PCLK, "timer3_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 18, 0, },
0062     { HI6220_TIMER4_PCLK, "timer4_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 19, 0, },
0063     { HI6220_TIMER5_PCLK, "timer5_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 20, 0, },
0064     { HI6220_TIMER6_PCLK, "timer6_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 21, 0, },
0065     { HI6220_TIMER7_PCLK, "timer7_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 22, 0, },
0066     { HI6220_TIMER8_PCLK, "timer8_pclk", "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 23, 0, },
0067     { HI6220_UART0_PCLK,  "uart0_pclk",  "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 24, 0, },
0068     { HI6220_RTC0_PCLK,   "rtc0_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 25, 0, },
0069     { HI6220_RTC1_PCLK,   "rtc1_pclk",   "clk_tcxo", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x630, 26, 0, },
0070 };
0071 
0072 static void __init hi6220_clk_ao_init(struct device_node *np)
0073 {
0074     struct hisi_clock_data *clk_data_ao;
0075 
0076     clk_data_ao = hisi_clk_init(np, HI6220_AO_NR_CLKS);
0077     if (!clk_data_ao)
0078         return;
0079 
0080     hisi_clk_register_fixed_rate(hi6220_fixed_rate_clks,
0081                 ARRAY_SIZE(hi6220_fixed_rate_clks), clk_data_ao);
0082 
0083     hisi_clk_register_fixed_factor(hi6220_fixed_factor_clks,
0084                 ARRAY_SIZE(hi6220_fixed_factor_clks), clk_data_ao);
0085 
0086     hisi_clk_register_gate_sep(hi6220_separated_gate_clks_ao,
0087                 ARRAY_SIZE(hi6220_separated_gate_clks_ao), clk_data_ao);
0088 }
0089 /* Allow reset driver to probe as well */
0090 CLK_OF_DECLARE_DRIVER(hi6220_clk_ao, "hisilicon,hi6220-aoctrl", hi6220_clk_ao_init);
0091 
0092 
0093 /* clocks in sysctrl */
0094 static const char *mmc0_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
0095 static const char *mmc0_mux1_p[] __initdata = { "mmc0_mux0", "pll_media_gate", };
0096 static const char *mmc0_src_p[] __initdata = { "mmc0srcsel", "mmc0_div", };
0097 static const char *mmc1_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
0098 static const char *mmc1_mux1_p[] __initdata = { "mmc1_mux0", "pll_media_gate", };
0099 static const char *mmc1_src_p[]  __initdata = { "mmc1srcsel", "mmc1_div", };
0100 static const char *mmc2_mux0_p[] __initdata = { "pll_ddr_gate", "syspll", };
0101 static const char *mmc2_mux1_p[] __initdata = { "mmc2_mux0", "pll_media_gate", };
0102 static const char *mmc2_src_p[]  __initdata = { "mmc2srcsel", "mmc2_div", };
0103 static const char *mmc0_sample_in[] __initdata = { "mmc0_sample", "mmc0_pad", };
0104 static const char *mmc1_sample_in[] __initdata = { "mmc1_sample", "mmc1_pad", };
0105 static const char *mmc2_sample_in[] __initdata = { "mmc2_sample", "mmc2_pad", };
0106 static const char *uart1_src[] __initdata = { "clk_tcxo", "clk_150m", };
0107 static const char *uart2_src[] __initdata = { "clk_tcxo", "clk_150m", };
0108 static const char *uart3_src[] __initdata = { "clk_tcxo", "clk_150m", };
0109 static const char *uart4_src[] __initdata = { "clk_tcxo", "clk_150m", };
0110 static const char *hifi_src[] __initdata = { "syspll", "pll_media_gate", };
0111 
0112 static struct hisi_gate_clock hi6220_separated_gate_clks_sys[] __initdata = {
0113     { HI6220_MMC0_CLK,      "mmc0_clk",      "mmc0_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0,  0, },
0114     { HI6220_MMC0_CIUCLK,   "mmc0_ciuclk",   "mmc0_smp_in",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 0,  0, },
0115     { HI6220_MMC1_CLK,      "mmc1_clk",      "mmc1_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1,  0, },
0116     { HI6220_MMC1_CIUCLK,   "mmc1_ciuclk",   "mmc1_smp_in",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 1,  0, },
0117     { HI6220_MMC2_CLK,      "mmc2_clk",      "mmc2_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2,  0, },
0118     { HI6220_MMC2_CIUCLK,   "mmc2_ciuclk",   "mmc2_smp_in",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 2,  0, },
0119     { HI6220_USBOTG_HCLK,   "usbotg_hclk",   "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 4,  0, },
0120     { HI6220_CLK_PICOPHY,   "clk_picophy",   "cs_dapb",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x200, 5,  0, },
0121     { HI6220_HIFI,          "hifi_clk",      "hifi_div",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 0,  0, },
0122     { HI6220_DACODEC_PCLK,  "dacodec_pclk",  "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x210, 5,  0, },
0123     { HI6220_EDMAC_ACLK,    "edmac_aclk",    "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x220, 2,  0, },
0124     { HI6220_CS_ATB,        "cs_atb",        "cs_atb_div",     CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 0,  0, },
0125     { HI6220_I2C0_CLK,      "i2c0_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 1,  0, },
0126     { HI6220_I2C1_CLK,      "i2c1_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 2,  0, },
0127     { HI6220_I2C2_CLK,      "i2c2_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 3,  0, },
0128     { HI6220_I2C3_CLK,      "i2c3_clk",      "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 4,  0, },
0129     { HI6220_UART1_PCLK,    "uart1_pclk",    "uart1_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 5,  0, },
0130     { HI6220_UART2_PCLK,    "uart2_pclk",    "uart2_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 6,  0, },
0131     { HI6220_UART3_PCLK,    "uart3_pclk",    "uart3_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 7,  0, },
0132     { HI6220_UART4_PCLK,    "uart4_pclk",    "uart4_src",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 8,  0, },
0133     { HI6220_SPI_CLK,       "spi_clk",       "clk_150m",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 9,  0, },
0134     { HI6220_TSENSOR_CLK,   "tsensor_clk",   "clk_bus",        CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x230, 12, 0, },
0135     { HI6220_DAPB_CLK,      "dapb_clk",      "cs_dapb",        CLK_SET_RATE_PARENT|CLK_IS_CRITICAL,   0x230, 18, 0, },
0136     { HI6220_MMU_CLK,       "mmu_clk",       "ddrc_axi1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x240, 11, 0, },
0137     { HI6220_HIFI_SEL,      "hifi_sel",      "hifi_src",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 0,  0, },
0138     { HI6220_MMC0_SYSPLL,   "mmc0_syspll",   "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 1,  0, },
0139     { HI6220_MMC1_SYSPLL,   "mmc1_syspll",   "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 2,  0, },
0140     { HI6220_MMC2_SYSPLL,   "mmc2_syspll",   "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 3,  0, },
0141     { HI6220_MMC0_SEL,      "mmc0_sel",      "mmc0_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 6,  0, },
0142     { HI6220_MMC1_SEL,      "mmc1_sel",      "mmc1_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 7,  0, },
0143     { HI6220_BBPPLL_SEL,    "bbppll_sel",    "pll0_bbp_gate",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9,  0, },
0144     { HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
0145     { HI6220_MMC2_SEL,      "mmc2_sel",      "mmc2_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
0146     { HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll",         CLK_SET_RATE_PARENT|CLK_IS_CRITICAL,   0x270, 12, 0, },
0147 };
0148 
0149 static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {
0150     { HI6220_MMC0_SRC,    "mmc0_src",    mmc0_src_p,     ARRAY_SIZE(mmc0_src_p),     CLK_SET_RATE_PARENT, 0x4,   0,  1, 0, },
0151     { HI6220_MMC0_SMP_IN, "mmc0_smp_in", mmc0_sample_in, ARRAY_SIZE(mmc0_sample_in), CLK_SET_RATE_PARENT, 0x4,   0,  1, 0, },
0152     { HI6220_MMC1_SRC,    "mmc1_src",    mmc1_src_p,     ARRAY_SIZE(mmc1_src_p),     CLK_SET_RATE_PARENT, 0x4,   2,  1, 0, },
0153     { HI6220_MMC1_SMP_IN, "mmc1_smp_in", mmc1_sample_in, ARRAY_SIZE(mmc1_sample_in), CLK_SET_RATE_PARENT, 0x4,   2,  1, 0, },
0154     { HI6220_MMC2_SRC,    "mmc2_src",    mmc2_src_p,     ARRAY_SIZE(mmc2_src_p),     CLK_SET_RATE_PARENT, 0x4,   4,  1, 0, },
0155     { HI6220_MMC2_SMP_IN, "mmc2_smp_in", mmc2_sample_in, ARRAY_SIZE(mmc2_sample_in), CLK_SET_RATE_PARENT, 0x4,   4,  1, 0, },
0156     { HI6220_HIFI_SRC,    "hifi_src",    hifi_src,       ARRAY_SIZE(hifi_src),       CLK_SET_RATE_PARENT, 0x400, 0,  1, CLK_MUX_HIWORD_MASK,},
0157     { HI6220_UART1_SRC,   "uart1_src",   uart1_src,      ARRAY_SIZE(uart1_src),      CLK_SET_RATE_PARENT, 0x400, 1,  1, CLK_MUX_HIWORD_MASK,},
0158     { HI6220_UART2_SRC,   "uart2_src",   uart2_src,      ARRAY_SIZE(uart2_src),      CLK_SET_RATE_PARENT, 0x400, 2,  1, CLK_MUX_HIWORD_MASK,},
0159     { HI6220_UART3_SRC,   "uart3_src",   uart3_src,      ARRAY_SIZE(uart3_src),      CLK_SET_RATE_PARENT, 0x400, 3,  1, CLK_MUX_HIWORD_MASK,},
0160     { HI6220_UART4_SRC,   "uart4_src",   uart4_src,      ARRAY_SIZE(uart4_src),      CLK_SET_RATE_PARENT, 0x400, 4,  1, CLK_MUX_HIWORD_MASK,},
0161     { HI6220_MMC0_MUX0,   "mmc0_mux0",   mmc0_mux0_p,    ARRAY_SIZE(mmc0_mux0_p),    CLK_SET_RATE_PARENT, 0x400, 5,  1, CLK_MUX_HIWORD_MASK,},
0162     { HI6220_MMC1_MUX0,   "mmc1_mux0",   mmc1_mux0_p,    ARRAY_SIZE(mmc1_mux0_p),    CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
0163     { HI6220_MMC2_MUX0,   "mmc2_mux0",   mmc2_mux0_p,    ARRAY_SIZE(mmc2_mux0_p),    CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
0164     { HI6220_MMC0_MUX1,   "mmc0_mux1",   mmc0_mux1_p,    ARRAY_SIZE(mmc0_mux1_p),    CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
0165     { HI6220_MMC1_MUX1,   "mmc1_mux1",   mmc1_mux1_p,    ARRAY_SIZE(mmc1_mux1_p),    CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,},
0166     { HI6220_MMC2_MUX1,   "mmc2_mux1",   mmc2_mux1_p,    ARRAY_SIZE(mmc2_mux1_p),    CLK_SET_RATE_PARENT, 0x400, 15, 1, CLK_MUX_HIWORD_MASK,},
0167 };
0168 
0169 static struct hi6220_divider_clock hi6220_div_clks_sys[] __initdata = {
0170     { HI6220_CLK_BUS,     "clk_bus",     "clk_300m",      CLK_SET_RATE_PARENT, 0x490, 0,  4, 7, },
0171     { HI6220_MMC0_DIV,    "mmc0_div",    "mmc0_syspll",   CLK_SET_RATE_PARENT, 0x494, 0,  6, 7, },
0172     { HI6220_MMC1_DIV,    "mmc1_div",    "mmc1_syspll",   CLK_SET_RATE_PARENT, 0x498, 0,  6, 7, },
0173     { HI6220_MMC2_DIV,    "mmc2_div",    "mmc2_syspll",   CLK_SET_RATE_PARENT, 0x49c, 0,  6, 7, },
0174     { HI6220_HIFI_DIV,    "hifi_div",    "hifi_sel",      CLK_SET_RATE_PARENT, 0x4a0, 0,  4, 7, },
0175     { HI6220_BBPPLL0_DIV, "bbppll0_div", "bbppll_sel",    CLK_SET_RATE_PARENT, 0x4a0, 8,  6, 15,},
0176     { HI6220_CS_DAPB,     "cs_dapb",     "picophy_src",   CLK_SET_RATE_PARENT, 0x4a0, 24, 2, 31,},
0177     { HI6220_CS_ATB_DIV,  "cs_atb_div",  "cs_atb_syspll", CLK_SET_RATE_PARENT, 0x4a4, 0,  4, 7, },
0178 };
0179 
0180 static void __init hi6220_clk_sys_init(struct device_node *np)
0181 {
0182     struct hisi_clock_data *clk_data;
0183 
0184     clk_data = hisi_clk_init(np, HI6220_SYS_NR_CLKS);
0185     if (!clk_data)
0186         return;
0187 
0188     hisi_clk_register_gate_sep(hi6220_separated_gate_clks_sys,
0189             ARRAY_SIZE(hi6220_separated_gate_clks_sys), clk_data);
0190 
0191     hisi_clk_register_mux(hi6220_mux_clks_sys,
0192             ARRAY_SIZE(hi6220_mux_clks_sys), clk_data);
0193 
0194     hi6220_clk_register_divider(hi6220_div_clks_sys,
0195             ARRAY_SIZE(hi6220_div_clks_sys), clk_data);
0196 }
0197 CLK_OF_DECLARE_DRIVER(hi6220_clk_sys, "hisilicon,hi6220-sysctrl", hi6220_clk_sys_init);
0198 
0199 
0200 /* clocks in media controller */
0201 static const char *clk_1000_1200_src[] __initdata = { "pll_gpu_gate", "media_syspll_src", };
0202 static const char *clk_1440_1200_src[] __initdata = { "media_syspll_src", "media_pll_src", };
0203 static const char *clk_1000_1440_src[] __initdata = { "pll_gpu_gate", "media_pll_src", };
0204 
0205 static struct hisi_gate_clock hi6220_separated_gate_clks_media[] __initdata = {
0206     { HI6220_DSI_PCLK,       "dsi_pclk",         "vpucodec",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 0,  0, },
0207     { HI6220_G3D_PCLK,       "g3d_pclk",         "vpucodec",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 1,  0, },
0208     { HI6220_ACLK_CODEC_VPU, "aclk_codec_vpu",   "ade_core_src",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 3,  0, },
0209     { HI6220_ISP_SCLK,       "isp_sclk",         "isp_sclk_src",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 5,  0, },
0210     { HI6220_ADE_CORE,   "ade_core",         "ade_core_src",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 6,  0, },
0211     { HI6220_MED_MMU,        "media_mmu",        "mmu_clk",       CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 8,  0, },
0212     { HI6220_CFG_CSI4PHY,    "cfg_csi4phy",      "clk_tcxo",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 9,  0, },
0213     { HI6220_CFG_CSI2PHY,    "cfg_csi2phy",      "clk_tcxo",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 10, 0, },
0214     { HI6220_ISP_SCLK_GATE,  "isp_sclk_gate",    "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 11, 0, },
0215     { HI6220_ISP_SCLK_GATE1, "isp_sclk_gate1",   "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 12, 0, },
0216     { HI6220_ADE_CORE_GATE,  "ade_core_gate",    "media_pll_src", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 14, 0, },
0217     { HI6220_CODEC_VPU_GATE, "codec_vpu_gate",   "clk_1000_1440", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 15, 0, },
0218     { HI6220_MED_SYSPLL,     "media_syspll_src", "media_syspll",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x520, 17, 0, },
0219 };
0220 
0221 static struct hisi_mux_clock hi6220_mux_clks_media[] __initdata = {
0222     { HI6220_1440_1200, "clk_1440_1200", clk_1440_1200_src, ARRAY_SIZE(clk_1440_1200_src), CLK_SET_RATE_PARENT, 0x51c, 0, 1, 0, },
0223     { HI6220_1000_1200, "clk_1000_1200", clk_1000_1200_src, ARRAY_SIZE(clk_1000_1200_src), CLK_SET_RATE_PARENT, 0x51c, 1, 1, 0, },
0224     { HI6220_1000_1440, "clk_1000_1440", clk_1000_1440_src, ARRAY_SIZE(clk_1000_1440_src), CLK_SET_RATE_PARENT, 0x51c, 6, 1, 0, },
0225 };
0226 
0227 static struct hi6220_divider_clock hi6220_div_clks_media[] __initdata = {
0228     { HI6220_CODEC_JPEG,    "codec_jpeg_aclk", "media_pll_src",  CLK_SET_RATE_PARENT, 0xcbc, 0,  4, 23, },
0229     { HI6220_ISP_SCLK_SRC,  "isp_sclk_src",    "isp_sclk_gate",  CLK_SET_RATE_PARENT, 0xcbc, 8,  4, 15, },
0230     { HI6220_ISP_SCLK1,     "isp_sclk1",       "isp_sclk_gate1", CLK_SET_RATE_PARENT, 0xcbc, 24, 4, 31, },
0231     { HI6220_ADE_CORE_SRC,  "ade_core_src",    "ade_core_gate",  CLK_SET_RATE_PARENT, 0xcc0, 16, 3, 23, },
0232     { HI6220_ADE_PIX_SRC,   "ade_pix_src",     "clk_1440_1200",  CLK_SET_RATE_PARENT, 0xcc0, 24, 6, 31, },
0233     { HI6220_G3D_CLK,       "g3d_clk",         "clk_1000_1200",  CLK_SET_RATE_PARENT, 0xcc4, 8,  4, 15, },
0234     { HI6220_CODEC_VPU_SRC, "codec_vpu_src",   "codec_vpu_gate", CLK_SET_RATE_PARENT, 0xcc4, 24, 6, 31, },
0235 };
0236 
0237 static void __init hi6220_clk_media_init(struct device_node *np)
0238 {
0239     struct hisi_clock_data *clk_data;
0240 
0241     clk_data = hisi_clk_init(np, HI6220_MEDIA_NR_CLKS);
0242     if (!clk_data)
0243         return;
0244 
0245     hisi_clk_register_gate_sep(hi6220_separated_gate_clks_media,
0246                 ARRAY_SIZE(hi6220_separated_gate_clks_media), clk_data);
0247 
0248     hisi_clk_register_mux(hi6220_mux_clks_media,
0249                 ARRAY_SIZE(hi6220_mux_clks_media), clk_data);
0250 
0251     hi6220_clk_register_divider(hi6220_div_clks_media,
0252                 ARRAY_SIZE(hi6220_div_clks_media), clk_data);
0253 }
0254 CLK_OF_DECLARE_DRIVER(hi6220_clk_media, "hisilicon,hi6220-mediactrl", hi6220_clk_media_init);
0255 
0256 
0257 /* clocks in pmctrl */
0258 static struct hisi_gate_clock hi6220_gate_clks_power[] __initdata = {
0259     { HI6220_PLL_GPU_GATE,   "pll_gpu_gate",   "gpupll",    CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x8,  0,  0, },
0260     { HI6220_PLL1_DDR_GATE,  "pll1_ddr_gate",  "ddrpll1",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x10, 0,  0, },
0261     { HI6220_PLL_DDR_GATE,   "pll_ddr_gate",   "ddrpll0",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x18, 0,  0, },
0262     { HI6220_PLL_MEDIA_GATE, "pll_media_gate", "media_pll", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x38, 0,  0, },
0263     { HI6220_PLL0_BBP_GATE,  "pll0_bbp_gate",  "bbppll0",   CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x48, 0,  0, },
0264 };
0265 
0266 static struct hi6220_divider_clock hi6220_div_clks_power[] __initdata = {
0267     { HI6220_DDRC_SRC,  "ddrc_src",  "ddr_sel_src", CLK_SET_RATE_PARENT, 0x5a8, 0, 4, 0, },
0268     { HI6220_DDRC_AXI1, "ddrc_axi1", "ddrc_src",    CLK_SET_RATE_PARENT, 0x5a8, 8, 2, 0, },
0269 };
0270 
0271 static void __init hi6220_clk_power_init(struct device_node *np)
0272 {
0273     struct hisi_clock_data *clk_data;
0274 
0275     clk_data = hisi_clk_init(np, HI6220_POWER_NR_CLKS);
0276     if (!clk_data)
0277         return;
0278 
0279     hisi_clk_register_gate(hi6220_gate_clks_power,
0280                 ARRAY_SIZE(hi6220_gate_clks_power), clk_data);
0281 
0282     hi6220_clk_register_divider(hi6220_div_clks_power,
0283                 ARRAY_SIZE(hi6220_div_clks_power), clk_data);
0284 }
0285 CLK_OF_DECLARE(hi6220_clk_power, "hisilicon,hi6220-pmctrl", hi6220_clk_power_init);
0286 
0287 /* clocks in acpu */
0288 static const struct hisi_gate_clock hi6220_acpu_sc_gate_sep_clks[] = {
0289     { HI6220_ACPU_SFT_AT_S, "sft_at_s", "cs_atb",
0290       CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0xc, 11, 0, },
0291 };
0292 
0293 static void __init hi6220_clk_acpu_init(struct device_node *np)
0294 {
0295     struct hisi_clock_data *clk_data;
0296     int nr = ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks);
0297 
0298     clk_data = hisi_clk_init(np, nr);
0299     if (!clk_data)
0300         return;
0301 
0302     hisi_clk_register_gate_sep(hi6220_acpu_sc_gate_sep_clks,
0303                    ARRAY_SIZE(hi6220_acpu_sc_gate_sep_clks),
0304                    clk_data);
0305 }
0306 
0307 CLK_OF_DECLARE(hi6220_clk_acpu, "hisilicon,hi6220-acpu-sctrl", hi6220_clk_acpu_init);
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