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0010 #include <dt-bindings/clock/hi3670-clock.h>
0011 #include <linux/clk-provider.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include "clk.h"
0015
0016 static const struct hisi_fixed_rate_clock hi3670_fixed_rate_clks[] = {
0017 { HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
0018 { HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
0019 { HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
0020 { HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
0021 { HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
0022 { HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
0023 { HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
0024 { HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
0025 { HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
0026 { HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
0027 { HI3670_CLK_PPLL_PCIE, "clk_ppll_pcie", NULL, 0, 100000000, },
0028 { HI3670_CLK_PCIEPLL_REV, "clk_pciepll_rev", NULL, 0, 100000000, },
0029 { HI3670_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
0030 { HI3670_PCLK, "pclk", NULL, 0, 20000000, },
0031 { HI3670_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
0032 { HI3670_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
0033 { HI3670_OSC32K, "osc32k", NULL, 0, 32764, },
0034 { HI3670_OSC19M, "osc19m", NULL, 0, 19200000, },
0035 { HI3670_CLK_480M, "clk_480m", NULL, 0, 480000000, },
0036 { HI3670_CLK_INVALID, "clk_invalid", NULL, 0, 10000000, },
0037 };
0038
0039
0040 static const struct hisi_fixed_factor_clock hi3670_crg_fixed_factor_clks[] = {
0041 { HI3670_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus",
0042 1, 7, 0, },
0043 { HI3670_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys",
0044 1, 6, 0, },
0045 { HI3670_CLK_SD_SYS, "clk_sd_sys", "clk_sd_sys_gt",
0046 1, 6, 0, },
0047 { HI3670_CLK_SDIO_SYS, "clk_sdio_sys", "clk_sdio_sys_gt",
0048 1, 6, 0, },
0049 { HI3670_CLK_DIV_A53HPM, "clk_div_a53hpm", "clk_a53hpm_andgt",
0050 1, 4, 0, },
0051 { HI3670_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt",
0052 1, 5, 0, },
0053 { HI3670_PCLK_GATE_UART0, "pclk_gate_uart0", "clk_mux_uartl",
0054 1, 1, 0, },
0055 { HI3670_CLK_FACTOR_UART0, "clk_factor_uart0", "clk_mux_uart0",
0056 1, 1, 0, },
0057 { HI3670_CLK_FACTOR_USB3PHY_PLL, "clk_factor_usb3phy_pll", "clk_ppll0",
0058 1, 60, 0, },
0059 { HI3670_CLK_GATE_ABB_USB, "clk_gate_abb_usb", "clk_gate_usb_tcxo_en",
0060 1, 1, 0, },
0061 { HI3670_CLK_GATE_UFSPHY_REF, "clk_gate_ufsphy_ref", "clkin_sys",
0062 1, 1, 0, },
0063 { HI3670_ICS_VOLT_HIGH, "ics_volt_high", "peri_volt_hold",
0064 1, 1, 0, },
0065 { HI3670_ICS_VOLT_MIDDLE, "ics_volt_middle", "peri_volt_middle",
0066 1, 1, 0, },
0067 { HI3670_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold",
0068 1, 1, 0, },
0069 { HI3670_VDEC_VOLT_HOLD, "vdec_volt_hold", "peri_volt_hold",
0070 1, 1, 0, },
0071 { HI3670_EDC_VOLT_HOLD, "edc_volt_hold", "peri_volt_hold",
0072 1, 1, 0, },
0073 { HI3670_CLK_ISP_SNCLK_FAC, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
0074 1, 10, 0, },
0075 { HI3670_CLK_FACTOR_RXDPHY, "clk_factor_rxdphy", "clk_andgt_rxdphy",
0076 1, 6, 0, },
0077 };
0078
0079 static const struct hisi_gate_clock hi3670_crgctrl_gate_sep_clks[] = {
0080 { HI3670_PPLL1_EN_ACPU, "ppll1_en_acpu", "clk_ppll1",
0081 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
0082 { HI3670_PPLL2_EN_ACPU, "ppll2_en_acpu", "clk_ppll2",
0083 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
0084 { HI3670_PPLL3_EN_ACPU, "ppll3_en_acpu", "clk_ppll3",
0085 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
0086 { HI3670_PPLL1_GT_CPU, "ppll1_gt_cpu", "clk_ppll1",
0087 CLK_SET_RATE_PARENT, 0x460, 16, 0, },
0088 { HI3670_PPLL2_GT_CPU, "ppll2_gt_cpu", "clk_ppll2",
0089 CLK_SET_RATE_PARENT, 0x460, 18, 0, },
0090 { HI3670_PPLL3_GT_CPU, "ppll3_gt_cpu", "clk_ppll3",
0091 CLK_SET_RATE_PARENT, 0x460, 20, 0, },
0092 { HI3670_CLK_GATE_PPLL2_MEDIA, "clk_gate_ppll2_media", "clk_ppll2",
0093 CLK_SET_RATE_PARENT, 0x410, 27, 0, },
0094 { HI3670_CLK_GATE_PPLL3_MEDIA, "clk_gate_ppll3_media", "clk_ppll3",
0095 CLK_SET_RATE_PARENT, 0x410, 28, 0, },
0096 { HI3670_CLK_GATE_PPLL4_MEDIA, "clk_gate_ppll4_media", "clk_ppll4",
0097 CLK_SET_RATE_PARENT, 0x410, 26, 0, },
0098 { HI3670_CLK_GATE_PPLL6_MEDIA, "clk_gate_ppll6_media", "clk_ppll6",
0099 CLK_SET_RATE_PARENT, 0x410, 30, 0, },
0100 { HI3670_CLK_GATE_PPLL7_MEDIA, "clk_gate_ppll7_media", "clk_ppll7",
0101 CLK_SET_RATE_PARENT, 0x410, 29, 0, },
0102 { HI3670_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
0103 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
0104 { HI3670_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
0105 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
0106 { HI3670_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
0107 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
0108 { HI3670_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
0109 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
0110 { HI3670_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
0111 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
0112 { HI3670_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
0113 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
0114 { HI3670_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
0115 CLK_SET_RATE_PARENT, 0x10, 6, 0, },
0116 { HI3670_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
0117 CLK_SET_RATE_PARENT, 0x10, 7, 0, },
0118 { HI3670_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
0119 CLK_SET_RATE_PARENT, 0x10, 8, 0, },
0120 { HI3670_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
0121 CLK_SET_RATE_PARENT, 0x10, 9, 0, },
0122 { HI3670_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
0123 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
0124 { HI3670_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
0125 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
0126 { HI3670_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
0127 CLK_SET_RATE_PARENT, 0x10, 12, 0, },
0128 { HI3670_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
0129 CLK_SET_RATE_PARENT, 0x10, 13, 0, },
0130 { HI3670_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
0131 CLK_SET_RATE_PARENT, 0x10, 14, 0, },
0132 { HI3670_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
0133 CLK_SET_RATE_PARENT, 0x10, 15, 0, },
0134 { HI3670_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
0135 CLK_SET_RATE_PARENT, 0x10, 16, 0, },
0136 { HI3670_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
0137 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
0138 { HI3670_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
0139 CLK_SET_RATE_PARENT, 0x10, 20, 0, },
0140 { HI3670_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
0141 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
0142 { HI3670_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
0143 CLK_SET_RATE_PARENT, 0x50, 28, 0, },
0144 { HI3670_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
0145 CLK_SET_RATE_PARENT, 0x50, 29, 0, },
0146 { HI3670_HCLK_GATE_USB3OTG, "hclk_gate_usb3otg", "clk_div_sysbus",
0147 CLK_SET_RATE_PARENT, 0x0, 25, 0, },
0148 { HI3670_ACLK_GATE_USB3DVFS, "aclk_gate_usb3dvfs", "autodiv_emmc0bus",
0149 CLK_SET_RATE_PARENT, 0x40, 1, 0, },
0150 { HI3670_HCLK_GATE_SDIO, "hclk_gate_sdio", "clk_div_sysbus",
0151 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
0152 { HI3670_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
0153 CLK_SET_RATE_PARENT, 0x420, 7, 0, },
0154 { HI3670_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "pclk_gate_mmc1_pcie",
0155 CLK_SET_RATE_PARENT, 0x420, 9, 0, },
0156 { HI3670_PCLK_GATE_MMC1_PCIE, "pclk_gate_mmc1_pcie", "pclk_div_mmc1_pcie",
0157 CLK_SET_RATE_PARENT, 0x30, 12, 0, },
0158 { HI3670_PCLK_GATE_MMC0_IOC, "pclk_gate_mmc0_ioc", "clk_div_mmc0bus",
0159 CLK_SET_RATE_PARENT, 0x40, 13, 0, },
0160 { HI3670_PCLK_GATE_MMC1_IOC, "pclk_gate_mmc1_ioc", "clk_div_mmc1bus",
0161 CLK_SET_RATE_PARENT, 0x420, 21, 0, },
0162 { HI3670_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
0163 CLK_SET_RATE_PARENT, 0x30, 1, 0, },
0164 { HI3670_CLK_GATE_VCODECBUS2DDR, "clk_gate_vcodecbus2ddr", "clk_div_vcodecbus",
0165 CLK_SET_RATE_PARENT, 0x0, 5, 0, },
0166 { HI3670_CLK_CCI400_BYPASS, "clk_cci400_bypass", "clk_ddrc_freq",
0167 CLK_SET_RATE_PARENT, 0x22C, 28, 0, },
0168 { HI3670_CLK_GATE_CCI400, "clk_gate_cci400", "clk_ddrc_freq",
0169 CLK_SET_RATE_PARENT, 0x50, 14, 0, },
0170 { HI3670_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
0171 CLK_SET_RATE_PARENT, 0x40, 17, 0, },
0172 { HI3670_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
0173 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
0174 { HI3670_CLK_GATE_SDIO, "clk_gate_sdio", "clk_mux_sdio_sys",
0175 CLK_SET_RATE_PARENT, 0x40, 19, 0, },
0176 { HI3670_CLK_GATE_A57HPM, "clk_gate_a57hpm", "clk_div_a53hpm",
0177 CLK_SET_RATE_PARENT, 0x050, 9, 0, },
0178 { HI3670_CLK_GATE_A53HPM, "clk_gate_a53hpm", "clk_div_a53hpm",
0179 CLK_SET_RATE_PARENT, 0x050, 13, 0, },
0180 { HI3670_CLK_GATE_PA_A53, "clk_gate_pa_a53", "clk_div_a53hpm",
0181 CLK_SET_RATE_PARENT, 0x480, 10, 0, },
0182 { HI3670_CLK_GATE_PA_A57, "clk_gate_pa_a57", "clk_div_a53hpm",
0183 CLK_SET_RATE_PARENT, 0x480, 9, 0, },
0184 { HI3670_CLK_GATE_PA_G3D, "clk_gate_pa_g3d", "clk_div_a53hpm",
0185 CLK_SET_RATE_PARENT, 0x480, 15, 0, },
0186 { HI3670_CLK_GATE_GPUHPM, "clk_gate_gpuhpm", "clk_div_a53hpm",
0187 CLK_SET_RATE_PARENT, 0x050, 15, 0, },
0188 { HI3670_CLK_GATE_PERIHPM, "clk_gate_perihpm", "clk_div_a53hpm",
0189 CLK_SET_RATE_PARENT, 0x050, 12, 0, },
0190 { HI3670_CLK_GATE_AOHPM, "clk_gate_aohpm", "clk_div_a53hpm",
0191 CLK_SET_RATE_PARENT, 0x050, 11, 0, },
0192 { HI3670_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
0193 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
0194 { HI3670_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
0195 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
0196 { HI3670_PCLK_GATE_UART1, "pclk_gate_uart1", "clk_mux_uarth",
0197 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
0198 { HI3670_PCLK_GATE_UART4, "pclk_gate_uart4", "clk_mux_uarth",
0199 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
0200 { HI3670_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uartl",
0201 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
0202 { HI3670_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uartl",
0203 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
0204 { HI3670_PCLK_GATE_UART2, "pclk_gate_uart2", "clk_mux_uartl",
0205 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
0206 { HI3670_PCLK_GATE_UART5, "pclk_gate_uart5", "clk_mux_uartl",
0207 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
0208 { HI3670_CLK_GATE_UART0, "clk_gate_uart0", "clk_mux_uart0",
0209 CLK_SET_RATE_PARENT, 0x20, 10, 0, },
0210 { HI3670_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
0211 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
0212 { HI3670_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
0213 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
0214 { HI3670_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
0215 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
0216 { HI3670_PCLK_GATE_I2C3, "pclk_gate_i2c3", "clk_mux_i2c",
0217 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
0218 { HI3670_PCLK_GATE_I2C4, "pclk_gate_i2c4", "clk_mux_i2c",
0219 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
0220 { HI3670_PCLK_GATE_I2C7, "pclk_gate_i2c7", "clk_mux_i2c",
0221 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
0222 { HI3670_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
0223 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
0224 { HI3670_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
0225 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
0226 { HI3670_PCLK_GATE_SPI1, "pclk_gate_spi1", "clk_mux_spi",
0227 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
0228 { HI3670_PCLK_GATE_SPI4, "pclk_gate_spi4", "clk_mux_spi",
0229 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
0230 { HI3670_CLK_GATE_USB3OTG_REF, "clk_gate_usb3otg_ref", "clkin_sys",
0231 CLK_SET_RATE_PARENT, 0x40, 0, 0, },
0232 { HI3670_CLK_GATE_USB2PHY_REF, "clk_gate_usb2phy_ref", "clkin_sys",
0233 CLK_SET_RATE_PARENT, 0x410, 19, 0, },
0234 { HI3670_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
0235 CLK_SET_RATE_PARENT, 0x420, 8, 0, },
0236 { HI3670_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_gate_mmc1_pcieaxi",
0237 CLK_SET_RATE_PARENT, 0x420, 5, 0, },
0238 { HI3670_CLK_GATE_MMC1_PCIEAXI, "clk_gate_mmc1_pcieaxi", "clk_div_pcieaxi",
0239 CLK_SET_RATE_PARENT, 0x050, 4, 0, },
0240 { HI3670_CLK_GATE_PCIEPHY_REF, "clk_gate_pciephy_ref", "clk_ppll_pcie",
0241 CLK_SET_RATE_PARENT, 0x470, 14, 0, },
0242 { HI3670_CLK_GATE_PCIE_DEBOUNCE, "clk_gate_pcie_debounce", "clk_ppll_pcie",
0243 CLK_SET_RATE_PARENT, 0x470, 12, 0, },
0244 { HI3670_CLK_GATE_PCIEIO, "clk_gate_pcieio", "clk_ppll_pcie",
0245 CLK_SET_RATE_PARENT, 0x470, 13, 0, },
0246 { HI3670_CLK_GATE_PCIE_HP, "clk_gate_pcie_hp", "clk_ppll_pcie",
0247 CLK_SET_RATE_PARENT, 0x470, 15, 0, },
0248 { HI3670_CLK_GATE_AO_ASP, "clk_gate_ao_asp", "clk_div_ao_asp",
0249 CLK_SET_RATE_PARENT, 0x0, 26, 0, },
0250 { HI3670_PCLK_GATE_PCTRL, "pclk_gate_pctrl", "clk_div_ptp",
0251 CLK_SET_RATE_PARENT, 0x20, 31, 0, },
0252 { HI3670_CLK_CSI_TRANS_GT, "clk_csi_trans_gt", "clk_div_csi_trans",
0253 CLK_SET_RATE_PARENT, 0x30, 24, 0, },
0254 { HI3670_CLK_DSI_TRANS_GT, "clk_dsi_trans_gt", "clk_div_dsi_trans",
0255 CLK_SET_RATE_PARENT, 0x30, 25, 0, },
0256 { HI3670_CLK_GATE_PWM, "clk_gate_pwm", "clk_div_ptp",
0257 CLK_SET_RATE_PARENT, 0x20, 0, 0, },
0258 { HI3670_ABB_AUDIO_EN0, "abb_audio_en0", "clk_gate_abb_192",
0259 CLK_SET_RATE_PARENT, 0x30, 8, 0, },
0260 { HI3670_ABB_AUDIO_EN1, "abb_audio_en1", "clk_gate_abb_192",
0261 CLK_SET_RATE_PARENT, 0x30, 9, 0, },
0262 { HI3670_ABB_AUDIO_GT_EN0, "abb_audio_gt_en0", "abb_audio_en0",
0263 CLK_SET_RATE_PARENT, 0x30, 19, 0, },
0264 { HI3670_ABB_AUDIO_GT_EN1, "abb_audio_gt_en1", "abb_audio_en1",
0265 CLK_SET_RATE_PARENT, 0x40, 20, 0, },
0266 { HI3670_CLK_GATE_DP_AUDIO_PLL_AO, "clk_gate_dp_audio_pll_ao", "clkdiv_dp_audio_pll_ao",
0267 CLK_SET_RATE_PARENT, 0x00, 13, 0, },
0268 { HI3670_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
0269 CLK_SET_RATE_PARENT, 0, 1, 0, },
0270 { HI3670_PERI_VOLT_MIDDLE, "peri_volt_middle", "clkin_sys",
0271 CLK_SET_RATE_PARENT, 0, 1, 0, },
0272 { HI3670_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0", "clk_isp_snclk_mux0",
0273 CLK_SET_RATE_PARENT, 0x50, 16, 0, },
0274 { HI3670_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1", "clk_isp_snclk_mux1",
0275 CLK_SET_RATE_PARENT, 0x50, 17, 0, },
0276 { HI3670_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2", "clk_isp_snclk_mux2",
0277 CLK_SET_RATE_PARENT, 0x50, 18, 0, },
0278 { HI3670_CLK_GATE_RXDPHY0_CFG, "clk_gate_rxdphy0_cfg", "clk_mux_rxdphy_cfg",
0279 CLK_SET_RATE_PARENT, 0x030, 20, 0, },
0280 { HI3670_CLK_GATE_RXDPHY1_CFG, "clk_gate_rxdphy1_cfg", "clk_mux_rxdphy_cfg",
0281 CLK_SET_RATE_PARENT, 0x030, 21, 0, },
0282 { HI3670_CLK_GATE_RXDPHY2_CFG, "clk_gate_rxdphy2_cfg", "clk_mux_rxdphy_cfg",
0283 CLK_SET_RATE_PARENT, 0x030, 22, 0, },
0284 { HI3670_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
0285 CLK_SET_RATE_PARENT, 0x030, 28, 0, },
0286 { HI3670_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
0287 CLK_SET_RATE_PARENT, 0x030, 29, 0, },
0288 { HI3670_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
0289 CLK_SET_RATE_PARENT, 0x030, 30, 0, },
0290 { HI3670_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
0291 CLK_SET_RATE_PARENT, 0x030, 31, 0, },
0292 { HI3670_CLK_GATE_MEDIA_TCXO, "clk_gate_media_tcxo", "clkin_sys",
0293 CLK_SET_RATE_PARENT, 0x40, 6, 0, },
0294 };
0295
0296 static const struct hisi_gate_clock hi3670_crgctrl_gate_clks[] = {
0297 { HI3670_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
0298 CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
0299 { HI3670_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
0300 CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
0301 { HI3670_PCLK_ANDGT_MMC1_PCIE, "pclk_andgt_mmc1_pcie", "clk_div_320m",
0302 CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, },
0303 { HI3670_CLK_GATE_VCODECBUS_GT, "clk_gate_vcodecbus_gt", "clk_mux_vcodecbus",
0304 CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, },
0305 { HI3670_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
0306 CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, },
0307 { HI3670_CLK_SD_SYS_GT, "clk_sd_sys_gt", "clkin_sys",
0308 CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, },
0309 { HI3670_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
0310 CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, },
0311 { HI3670_CLK_SDIO_SYS_GT, "clk_sdio_sys_gt", "clkin_sys",
0312 CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, },
0313 { HI3670_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
0314 CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, },
0315 { HI3670_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
0316 CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, },
0317 { HI3670_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
0318 CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, },
0319 { HI3670_CLK_ANDGT_UARTL, "clk_andgt_uartl", "clk_div_320m",
0320 CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, },
0321 { HI3670_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
0322 CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, },
0323 { HI3670_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
0324 CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, },
0325 { HI3670_CLK_ANDGT_PCIEAXI, "clk_andgt_pcieaxi", "clk_mux_pcieaxi",
0326 CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, },
0327 { HI3670_CLK_DIV_AO_ASP_GT, "clk_div_ao_asp_gt", "clk_mux_ao_asp",
0328 CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, },
0329 { HI3670_CLK_GATE_CSI_TRANS, "clk_gate_csi_trans", "clk_ppll2",
0330 CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, },
0331 { HI3670_CLK_GATE_DSI_TRANS, "clk_gate_dsi_trans", "clk_ppll2",
0332 CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, },
0333 { HI3670_CLK_ANDGT_PTP, "clk_andgt_ptp", "clk_div_320m",
0334 CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, },
0335 { HI3670_CLK_ANDGT_OUT0, "clk_andgt_out0", "clk_ppll0",
0336 CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, },
0337 { HI3670_CLK_ANDGT_OUT1, "clk_andgt_out1", "clk_ppll0",
0338 CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, },
0339 { HI3670_CLKGT_DP_AUDIO_PLL_AO, "clkgt_dp_audio_pll_ao", "clk_ppll6",
0340 CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, },
0341 { HI3670_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
0342 CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, },
0343 { HI3670_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
0344 CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, },
0345 { HI3670_CLK_ISP_SNCLK_ANGT, "clk_isp_snclk_angt", "clk_div_a53hpm",
0346 CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
0347 { HI3670_CLK_ANDGT_RXDPHY, "clk_andgt_rxdphy", "clk_div_a53hpm",
0348 CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, },
0349 { HI3670_CLK_ANDGT_ICS, "clk_andgt_ics", "clk_mux_ics",
0350 CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, },
0351 { HI3670_AUTODIV_DMABUS, "autodiv_dmabus", "autodiv_sysbus",
0352 CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, },
0353 };
0354
0355 static const char *const
0356 clk_mux_sysbus_p[] = { "clk_ppll1", "clk_ppll0", };
0357 static const char *const
0358 clk_mux_vcodecbus_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0",
0359 "clk_invalid", "clk_ppll2", "clk_invalid",
0360 "clk_invalid", "clk_invalid", "clk_ppll3",
0361 "clk_invalid", "clk_invalid", "clk_invalid",
0362 "clk_invalid", "clk_invalid", "clk_invalid",
0363 "clk_invalid", };
0364 static const char *const
0365 clk_mux_sd_sys_p[] = { "clk_sd_sys", "clk_div_sd", };
0366 static const char *const
0367 clk_mux_sd_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
0368 static const char *const
0369 clk_mux_sdio_sys_p[] = { "clk_sdio_sys", "clk_div_sdio", };
0370 static const char *const
0371 clk_mux_sdio_pll_p[] = { "clk_ppll0", "clk_ppll3", "clk_ppll2", "clk_ppll2", };
0372 static const char *const
0373 clk_mux_a53hpm_p[] = { "clk_ppll0", "clk_ppll2", };
0374 static const char *const
0375 clk_mux_320m_p[] = { "clk_ppll2", "clk_ppll0", };
0376 static const char *const
0377 clk_mux_uarth_p[] = { "clkin_sys", "clk_div_uarth", };
0378 static const char *const
0379 clk_mux_uartl_p[] = { "clkin_sys", "clk_div_uartl", };
0380 static const char *const
0381 clk_mux_uart0_p[] = { "clkin_sys", "clk_div_uart0", };
0382 static const char *const
0383 clk_mux_i2c_p[] = { "clkin_sys", "clk_div_i2c", };
0384 static const char *const
0385 clk_mux_spi_p[] = { "clkin_sys", "clk_div_spi", };
0386 static const char *const
0387 clk_mux_pcieaxi_p[] = { "clkin_sys", "clk_ppll0", };
0388 static const char *const
0389 clk_mux_ao_asp_p[] = { "clk_ppll2", "clk_ppll3", };
0390 static const char *const
0391 clk_mux_vdec_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
0392 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0393 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0394 "clk_invalid", "clk_invalid", "clk_invalid",
0395 "clk_invalid", };
0396 static const char *const
0397 clk_mux_venc_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
0398 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0399 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0400 "clk_invalid", "clk_invalid", "clk_invalid",
0401 "clk_invalid", };
0402 static const char *const
0403 clk_isp_snclk_mux0_p[] = { "clkin_sys", "clk_isp_snclk_div0", };
0404 static const char *const
0405 clk_isp_snclk_mux1_p[] = { "clkin_sys", "clk_isp_snclk_div1", };
0406 static const char *const
0407 clk_isp_snclk_mux2_p[] = { "clkin_sys", "clk_isp_snclk_div2", };
0408 static const char *const
0409 clk_mux_rxdphy_cfg_p[] = { "clk_factor_rxdphy", "clkin_sys", };
0410 static const char *const
0411 clk_mux_ics_p[] = { "clk_invalid", "clk_ppll4", "clk_ppll0", "clk_invalid",
0412 "clk_ppll2", "clk_invalid", "clk_invalid", "clk_invalid",
0413 "clk_ppll3", "clk_invalid", "clk_invalid", "clk_invalid",
0414 "clk_invalid", "clk_invalid", "clk_invalid",
0415 "clk_invalid", };
0416
0417 static const struct hisi_mux_clock hi3670_crgctrl_mux_clks[] = {
0418 { HI3670_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
0419 ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT,
0420 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },
0421 { HI3670_CLK_MUX_VCODECBUS, "clk_mux_vcodecbus", clk_mux_vcodecbus_p,
0422 ARRAY_SIZE(clk_mux_vcodecbus_p), CLK_SET_RATE_PARENT,
0423 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, },
0424 { HI3670_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
0425 ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT,
0426 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, },
0427 { HI3670_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_sd_pll_p,
0428 ARRAY_SIZE(clk_mux_sd_pll_p), CLK_SET_RATE_PARENT,
0429 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, },
0430 { HI3670_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
0431 ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT,
0432 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, },
0433 { HI3670_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_sdio_pll_p,
0434 ARRAY_SIZE(clk_mux_sdio_pll_p), CLK_SET_RATE_PARENT,
0435 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, },
0436 { HI3670_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_a53hpm_p,
0437 ARRAY_SIZE(clk_mux_a53hpm_p), CLK_SET_RATE_PARENT,
0438 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, },
0439 { HI3670_CLK_MUX_320M, "clk_mux_320m", clk_mux_320m_p,
0440 ARRAY_SIZE(clk_mux_320m_p), CLK_SET_RATE_PARENT,
0441 0x100, 0, 1, CLK_MUX_HIWORD_MASK, },
0442 { HI3670_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
0443 ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT,
0444 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },
0445 { HI3670_CLK_MUX_UARTL, "clk_mux_uartl", clk_mux_uartl_p,
0446 ARRAY_SIZE(clk_mux_uartl_p), CLK_SET_RATE_PARENT,
0447 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },
0448 { HI3670_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
0449 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT,
0450 0xAC, 2, 1, CLK_MUX_HIWORD_MASK, },
0451 { HI3670_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
0452 ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT,
0453 0xAC, 13, 1, CLK_MUX_HIWORD_MASK, },
0454 { HI3670_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
0455 ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT,
0456 0xAC, 8, 1, CLK_MUX_HIWORD_MASK, },
0457 { HI3670_CLK_MUX_PCIEAXI, "clk_mux_pcieaxi", clk_mux_pcieaxi_p,
0458 ARRAY_SIZE(clk_mux_pcieaxi_p), CLK_SET_RATE_PARENT,
0459 0xb4, 5, 1, CLK_MUX_HIWORD_MASK, },
0460 { HI3670_CLK_MUX_AO_ASP, "clk_mux_ao_asp", clk_mux_ao_asp_p,
0461 ARRAY_SIZE(clk_mux_ao_asp_p), CLK_SET_RATE_PARENT,
0462 0x100, 6, 1, CLK_MUX_HIWORD_MASK, },
0463 { HI3670_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_vdec_p,
0464 ARRAY_SIZE(clk_mux_vdec_p), CLK_SET_RATE_PARENT,
0465 0xC8, 8, 4, CLK_MUX_HIWORD_MASK, },
0466 { HI3670_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
0467 ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT,
0468 0xC8, 4, 4, CLK_MUX_HIWORD_MASK, },
0469 { HI3670_CLK_ISP_SNCLK_MUX0, "clk_isp_snclk_mux0", clk_isp_snclk_mux0_p,
0470 ARRAY_SIZE(clk_isp_snclk_mux0_p), CLK_SET_RATE_PARENT,
0471 0x108, 3, 1, CLK_MUX_HIWORD_MASK, },
0472 { HI3670_CLK_ISP_SNCLK_MUX1, "clk_isp_snclk_mux1", clk_isp_snclk_mux1_p,
0473 ARRAY_SIZE(clk_isp_snclk_mux1_p), CLK_SET_RATE_PARENT,
0474 0x10C, 13, 1, CLK_MUX_HIWORD_MASK, },
0475 { HI3670_CLK_ISP_SNCLK_MUX2, "clk_isp_snclk_mux2", clk_isp_snclk_mux2_p,
0476 ARRAY_SIZE(clk_isp_snclk_mux2_p), CLK_SET_RATE_PARENT,
0477 0x10C, 10, 1, CLK_MUX_HIWORD_MASK, },
0478 { HI3670_CLK_MUX_RXDPHY_CFG, "clk_mux_rxdphy_cfg", clk_mux_rxdphy_cfg_p,
0479 ARRAY_SIZE(clk_mux_rxdphy_cfg_p), CLK_SET_RATE_PARENT,
0480 0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, },
0481 { HI3670_CLK_MUX_ICS, "clk_mux_ics", clk_mux_ics_p,
0482 ARRAY_SIZE(clk_mux_ics_p), CLK_SET_RATE_PARENT,
0483 0xc8, 12, 4, CLK_MUX_HIWORD_MASK, },
0484 };
0485
0486 static const struct hisi_divider_clock hi3670_crgctrl_divider_clks[] = {
0487 { HI3670_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
0488 CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
0489 { HI3670_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
0490 CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
0491 { HI3670_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
0492 CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
0493 { HI3670_PCLK_DIV_MMC1_PCIE, "pclk_div_mmc1_pcie", "pclk_andgt_mmc1_pcie",
0494 CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
0495 { HI3670_CLK_DIV_VCODECBUS, "clk_div_vcodecbus", "clk_gate_vcodecbus_gt",
0496 CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0497 { HI3670_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
0498 CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
0499 { HI3670_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
0500 CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
0501 { HI3670_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
0502 CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
0503 { HI3670_CLK_DIV_UARTL, "clk_div_uartl", "clk_andgt_uartl",
0504 CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
0505 { HI3670_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
0506 CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
0507 { HI3670_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
0508 CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
0509 { HI3670_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
0510 CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
0511 { HI3670_CLK_DIV_PCIEAXI, "clk_div_pcieaxi", "clk_andgt_pcieaxi",
0512 CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
0513 { HI3670_CLK_DIV_AO_ASP, "clk_div_ao_asp", "clk_div_ao_asp_gt",
0514 CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
0515 { HI3670_CLK_DIV_CSI_TRANS, "clk_div_csi_trans", "clk_gate_csi_trans",
0516 CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
0517 { HI3670_CLK_DIV_DSI_TRANS, "clk_div_dsi_trans", "clk_gate_dsi_trans",
0518 CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, },
0519 { HI3670_CLK_DIV_PTP, "clk_div_ptp", "clk_andgt_ptp",
0520 CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
0521 { HI3670_CLK_DIV_CLKOUT0_PLL, "clk_div_clkout0_pll", "clk_andgt_out0",
0522 CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, },
0523 { HI3670_CLK_DIV_CLKOUT1_PLL, "clk_div_clkout1_pll", "clk_andgt_out1",
0524 CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
0525 { HI3670_CLKDIV_DP_AUDIO_PLL_AO, "clkdiv_dp_audio_pll_ao", "clkgt_dp_audio_pll_ao",
0526 CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
0527 { HI3670_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
0528 CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0529 { HI3670_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
0530 CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
0531 { HI3670_CLK_ISP_SNCLK_DIV0, "clk_isp_snclk_div0", "clk_isp_snclk_fac",
0532 CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
0533 { HI3670_CLK_ISP_SNCLK_DIV1, "clk_isp_snclk_div1", "clk_isp_snclk_fac",
0534 CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, },
0535 { HI3670_CLK_ISP_SNCLK_DIV2, "clk_isp_snclk_div2", "clk_isp_snclk_fac",
0536 CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, },
0537 { HI3670_CLK_DIV_ICS, "clk_div_ics", "clk_andgt_ics",
0538 CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, },
0539 };
0540
0541
0542 static const struct hisi_gate_clock hi3670_pmu_gate_clks[] = {
0543 { HI3670_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
0544 CLK_SET_RATE_PARENT, (0x037 << 2), 0, 0, },
0545 };
0546
0547
0548 static const struct hisi_gate_clock hi3670_pctrl_gate_clks[] = {
0549 { HI3670_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en", "clk_gate_abb_192",
0550 CLK_SET_RATE_PARENT, 0x10, 0, CLK_GATE_HIWORD_MASK, },
0551 { HI3670_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
0552 CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
0553 };
0554
0555
0556 static const struct hisi_gate_clock hi3670_sctrl_gate_sep_clks[] = {
0557 { HI3670_PPLL0_EN_ACPU, "ppll0_en_acpu", "clk_ppll0",
0558 CLK_SET_RATE_PARENT, 0x190, 26, 0, },
0559 { HI3670_PPLL0_GT_CPU, "ppll0_gt_cpu", "clk_ppll0",
0560 CLK_SET_RATE_PARENT, 0x190, 15, 0, },
0561 { HI3670_CLK_GATE_PPLL0_MEDIA, "clk_gate_ppll0_media", "clk_ppll0",
0562 CLK_SET_RATE_PARENT, 0x1b0, 6, 0, },
0563 { HI3670_PCLK_GPIO18, "pclk_gpio18", "clk_div_aobus",
0564 CLK_SET_RATE_PARENT, 0x1B0, 9, 0, },
0565 { HI3670_PCLK_GPIO19, "pclk_gpio19", "clk_div_aobus",
0566 CLK_SET_RATE_PARENT, 0x1B0, 8, 0, },
0567 { HI3670_CLK_GATE_SPI, "clk_gate_spi", "clk_div_ioperi",
0568 CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
0569 { HI3670_PCLK_GATE_SPI, "pclk_gate_spi", "clk_div_ioperi",
0570 CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
0571 { HI3670_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_ufs_subsys",
0572 CLK_SET_RATE_PARENT, 0x1B0, 14, 0, },
0573 { HI3670_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref", "clkin_sys",
0574 CLK_SET_RATE_PARENT, 0x1b0, 12, 0, },
0575 { HI3670_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
0576 CLK_SET_RATE_PARENT, 0x160, 11, 0, },
0577 { HI3670_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
0578 CLK_SET_RATE_PARENT, 0x160, 12, 0, },
0579 { HI3670_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
0580 CLK_SET_RATE_PARENT, 0x160, 13, 0, },
0581 { HI3670_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
0582 CLK_SET_RATE_PARENT, 0x160, 14, 0, },
0583 { HI3670_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
0584 CLK_SET_RATE_PARENT, 0x160, 21, 0, },
0585 { HI3670_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
0586 CLK_SET_RATE_PARENT, 0x160, 22, 0, },
0587 { HI3670_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
0588 CLK_SET_RATE_PARENT, 0x160, 25, 0, },
0589 { HI3670_CLK_GATE_OUT0, "clk_gate_out0", "clk_mux_clkout0",
0590 CLK_SET_RATE_PARENT, 0x160, 16, 0, },
0591 { HI3670_CLK_GATE_OUT1, "clk_gate_out1", "clk_mux_clkout1",
0592 CLK_SET_RATE_PARENT, 0x160, 17, 0, },
0593 { HI3670_PCLK_GATE_SYSCNT, "pclk_gate_syscnt", "clk_div_aobus",
0594 CLK_SET_RATE_PARENT, 0x160, 19, 0, },
0595 { HI3670_CLK_GATE_SYSCNT, "clk_gate_syscnt", "clkin_sys",
0596 CLK_SET_RATE_PARENT, 0x160, 20, 0, },
0597 { HI3670_CLK_GATE_ASP_SUBSYS_PERI, "clk_gate_asp_subsys_peri",
0598 "clk_mux_asp_subsys_peri",
0599 CLK_SET_RATE_PARENT, 0x170, 6, 0, },
0600 { HI3670_CLK_GATE_ASP_SUBSYS, "clk_gate_asp_subsys", "clk_mux_asp_pll",
0601 CLK_SET_RATE_PARENT, 0x170, 4, 0, },
0602 { HI3670_CLK_GATE_ASP_TCXO, "clk_gate_asp_tcxo", "clkin_sys",
0603 CLK_SET_RATE_PARENT, 0x160, 27, 0, },
0604 { HI3670_CLK_GATE_DP_AUDIO_PLL, "clk_gate_dp_audio_pll",
0605 "clk_gate_dp_audio_pll_ao",
0606 CLK_SET_RATE_PARENT, 0x1B0, 7, 0, },
0607 };
0608
0609 static const struct hisi_gate_clock hi3670_sctrl_gate_clks[] = {
0610 { HI3670_CLK_ANDGT_IOPERI, "clk_andgt_ioperi", "clk_ppll0",
0611 CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, },
0612 { HI3670_CLKANDGT_ASP_SUBSYS_PERI, "clkandgt_asp_subsys_peri",
0613 "clk_ppll0",
0614 CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, },
0615 { HI3670_CLK_ANGT_ASP_SUBSYS, "clk_angt_asp_subsys", "clk_ppll0",
0616 CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, },
0617 };
0618
0619 static const char *const
0620 clk_mux_ufs_subsys_p[] = { "clkin_sys", "clk_ppll0", };
0621 static const char *const
0622 clk_mux_clkout0_p[] = { "clkin_ref", "clk_div_clkout0_tcxo",
0623 "clk_div_clkout0_pll", "clk_div_clkout0_pll", };
0624 static const char *const
0625 clk_mux_clkout1_p[] = { "clkin_ref", "clk_div_clkout1_tcxo",
0626 "clk_div_clkout1_pll", "clk_div_clkout1_pll", };
0627 static const char *const
0628 clk_mux_asp_subsys_peri_p[] = { "clk_ppll0", "clk_fll_src", };
0629 static const char *const
0630 clk_mux_asp_pll_p[] = { "clk_ppll0", "clk_fll_src", "clk_gate_ao_asp",
0631 "clk_pciepll_rev", };
0632
0633 static const struct hisi_mux_clock hi3670_sctrl_mux_clks[] = {
0634 { HI3670_CLK_MUX_UFS_SUBSYS, "clk_mux_ufs_subsys", clk_mux_ufs_subsys_p,
0635 ARRAY_SIZE(clk_mux_ufs_subsys_p), CLK_SET_RATE_PARENT,
0636 0x274, 8, 1, CLK_MUX_HIWORD_MASK, },
0637 { HI3670_CLK_MUX_CLKOUT0, "clk_mux_clkout0", clk_mux_clkout0_p,
0638 ARRAY_SIZE(clk_mux_clkout0_p), CLK_SET_RATE_PARENT,
0639 0x254, 12, 2, CLK_MUX_HIWORD_MASK, },
0640 { HI3670_CLK_MUX_CLKOUT1, "clk_mux_clkout1", clk_mux_clkout1_p,
0641 ARRAY_SIZE(clk_mux_clkout1_p), CLK_SET_RATE_PARENT,
0642 0x254, 14, 2, CLK_MUX_HIWORD_MASK, },
0643 { HI3670_CLK_MUX_ASP_SUBSYS_PERI, "clk_mux_asp_subsys_peri",
0644 clk_mux_asp_subsys_peri_p, ARRAY_SIZE(clk_mux_asp_subsys_peri_p),
0645 CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, },
0646 { HI3670_CLK_MUX_ASP_PLL, "clk_mux_asp_pll", clk_mux_asp_pll_p,
0647 ARRAY_SIZE(clk_mux_asp_pll_p), CLK_SET_RATE_PARENT,
0648 0x268, 9, 2, CLK_MUX_HIWORD_MASK, },
0649 };
0650
0651 static const struct hisi_divider_clock hi3670_sctrl_divider_clks[] = {
0652 { HI3670_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
0653 CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0654 { HI3670_CLK_DIV_UFS_SUBSYS, "clk_div_ufs_subsys", "clk_mux_ufs_subsys",
0655 CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0656 { HI3670_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_andgt_ioperi",
0657 CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0658 { HI3670_CLK_DIV_CLKOUT0_TCXO, "clk_div_clkout0_tcxo", "clkin_sys",
0659 CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, },
0660 { HI3670_CLK_DIV_CLKOUT1_TCXO, "clk_div_clkout1_tcxo", "clkin_sys",
0661 CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, },
0662 { HI3670_CLK_ASP_SUBSYS_PERI_DIV, "clk_asp_subsys_peri_div", "clkandgt_asp_subsys_peri",
0663 CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
0664 { HI3670_CLK_DIV_ASP_SUBSYS, "clk_div_asp_subsys", "clk_angt_asp_subsys",
0665 CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
0666 };
0667
0668
0669 static const struct hisi_fixed_factor_clock hi3670_iomcu_fixed_factor_clks[] = {
0670 { HI3670_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_gate_iomcu", 1, 4, 0, },
0671 { HI3670_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_gate_iomcu", 1, 4, 0, },
0672 { HI3670_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_gate_iomcu", 1, 4, 0, },
0673 { HI3670_CLK_GATE_SPI0, "clk_gate_spi0", "clk_spi0_gate_iomcu", 1, 1, 0, },
0674 { HI3670_CLK_GATE_SPI2, "clk_gate_spi2", "clk_spi2_gate_iomcu", 1, 1, 0, },
0675 { HI3670_CLK_GATE_UART3, "clk_gate_uart3", "clk_uart3_gate_iomcu", 1, 16, 0, },
0676 };
0677
0678 static const struct hisi_gate_clock hi3670_iomcu_gate_sep_clks[] = {
0679 { HI3670_CLK_I2C0_GATE_IOMCU, "clk_i2c0_gate_iomcu", "clk_fll_src",
0680 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
0681 { HI3670_CLK_I2C1_GATE_IOMCU, "clk_i2c1_gate_iomcu", "clk_fll_src",
0682 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
0683 { HI3670_CLK_I2C2_GATE_IOMCU, "clk_i2c2_gate_iomcu", "clk_fll_src",
0684 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
0685 { HI3670_CLK_SPI0_GATE_IOMCU, "clk_spi0_gate_iomcu", "clk_fll_src",
0686 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
0687 { HI3670_CLK_SPI2_GATE_IOMCU, "clk_spi2_gate_iomcu", "clk_fll_src",
0688 CLK_SET_RATE_PARENT, 0x10, 30, 0, },
0689 { HI3670_CLK_UART3_GATE_IOMCU, "clk_uart3_gate_iomcu", "clk_gate_iomcu_peri0",
0690 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
0691 { HI3670_CLK_GATE_PERI0_IOMCU, "clk_gate_iomcu_peri0", "clk_ppll0",
0692 CLK_SET_RATE_PARENT, 0x90, 0, 0, },
0693 };
0694
0695
0696 static const struct hisi_gate_clock hi3670_media1_gate_sep_clks[] = {
0697 { HI3670_ACLK_GATE_NOC_DSS, "aclk_gate_noc_dss", "aclk_gate_disp_noc_subsys",
0698 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
0699 { HI3670_PCLK_GATE_NOC_DSS_CFG, "pclk_gate_noc_dss_cfg", "pclk_gate_disp_noc_subsys",
0700 CLK_SET_RATE_PARENT, 0x10, 22, 0, },
0701 { HI3670_PCLK_GATE_MMBUF_CFG, "pclk_gate_mmbuf_cfg", "pclk_gate_disp_noc_subsys",
0702 CLK_SET_RATE_PARENT, 0x20, 5, 0, },
0703 { HI3670_PCLK_GATE_DISP_NOC_SUBSYS, "pclk_gate_disp_noc_subsys", "clk_div_sysbus",
0704 CLK_SET_RATE_PARENT, 0x10, 18, 0, },
0705 { HI3670_ACLK_GATE_DISP_NOC_SUBSYS, "aclk_gate_disp_noc_subsys", "clk_gate_vivobusfreq",
0706 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
0707 { HI3670_PCLK_GATE_DSS, "pclk_gate_dss", "pclk_gate_disp_noc_subsys",
0708 CLK_SET_RATE_PARENT, 0x00, 14, 0, },
0709 { HI3670_ACLK_GATE_DSS, "aclk_gate_dss", "aclk_gate_disp_noc_subsys",
0710 CLK_SET_RATE_PARENT, 0x00, 19, 0, },
0711 { HI3670_CLK_GATE_VIVOBUSFREQ, "clk_gate_vivobusfreq", "clk_div_vivobus",
0712 CLK_SET_RATE_PARENT, 0x00, 18, 0, },
0713 { HI3670_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
0714 CLK_SET_RATE_PARENT, 0x00, 15, 0, },
0715 { HI3670_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
0716 CLK_SET_RATE_PARENT, 0x00, 16, 0, },
0717 { HI3670_CLK_GATE_LDI1FREQ, "clk_gate_ldi1freq", "clk_div_ldi1",
0718 CLK_SET_RATE_PARENT, 0x00, 17, 0, },
0719 { HI3670_CLK_GATE_BRG, "clk_gate_brg", "clk_media_common_div",
0720 CLK_SET_RATE_PARENT, 0x00, 29, 0, },
0721 { HI3670_ACLK_GATE_ASC, "aclk_gate_asc", "clk_gate_mmbuf",
0722 CLK_SET_RATE_PARENT, 0x20, 3, 0, },
0723 { HI3670_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "clk_gate_mmbuf",
0724 CLK_SET_RATE_PARENT, 0x20, 4, 0, },
0725 { HI3670_CLK_GATE_MMBUF, "clk_gate_mmbuf", "aclk_div_mmbuf",
0726 CLK_SET_RATE_PARENT, 0x20, 0, 0, },
0727 { HI3670_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
0728 CLK_SET_RATE_PARENT, 0x20, 1, 0, },
0729 { HI3670_CLK_GATE_ATDIV_VIVO, "clk_gate_atdiv_vivo", "clk_div_vivobus",
0730 CLK_SET_RATE_PARENT, 0x010, 1, 0, },
0731 };
0732
0733 static const struct hisi_gate_clock hi3670_media1_gate_clks[] = {
0734 { HI3670_CLK_GATE_VIVOBUS_ANDGT, "clk_gate_vivobus_andgt", "clk_mux_vivobus",
0735 CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, },
0736 { HI3670_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
0737 CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, },
0738 { HI3670_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
0739 CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, },
0740 { HI3670_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
0741 CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, },
0742 { HI3670_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_sw_mmbuf",
0743 CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, },
0744 { HI3670_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "aclk_div_mmbuf",
0745 CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, },
0746 };
0747
0748 static const char *const
0749 clk_mux_vivobus_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
0750 "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
0751 "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
0752 "clk_invalid", "clk_invalid", "clk_invalid",
0753 "clk_invalid", "clk_invalid", "clk_invalid",
0754 "clk_invalid", };
0755 static const char *const
0756 clk_mux_edc0_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
0757 "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
0758 "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
0759 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0760 "clk_invalid", "clk_invalid", "clk_invalid", };
0761 static const char *const
0762 clk_mux_ldi0_p[] = { "clk_invalid", "clk_gate_ppll7_media",
0763 "clk_gate_ppll0_media", "clk_invalid",
0764 "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
0765 "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
0766 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0767 "clk_invalid", "clk_invalid", };
0768 static const char *const
0769 clk_mux_ldi1_p[] = { "clk_invalid", "clk_gate_ppll7_media",
0770 "clk_gate_ppll0_media", "clk_invalid",
0771 "clk_gate_ppll2_media", "clk_invalid", "clk_invalid",
0772 "clk_invalid", "clk_gate_ppll3_media", "clk_invalid",
0773 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0774 "clk_invalid", "clk_invalid", };
0775 static const char *const
0776 clk_sw_mmbuf_p[] = { "clk_invalid", "clk_invalid", "clk_gate_ppll0_media",
0777 "clk_invalid", "clk_gate_ppll2_media", "clk_invalid",
0778 "clk_invalid", "clk_invalid", "clk_gate_ppll3_media",
0779 "clk_invalid", "clk_invalid", "clk_invalid", "clk_invalid",
0780 "clk_invalid", "clk_invalid", "clk_invalid", };
0781
0782 static const struct hisi_mux_clock hi3670_media1_mux_clks[] = {
0783 { HI3670_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_vivobus_p,
0784 ARRAY_SIZE(clk_mux_vivobus_p), CLK_SET_RATE_PARENT,
0785 0x74, 6, 4, CLK_MUX_HIWORD_MASK, },
0786 { HI3670_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
0787 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT,
0788 0x68, 6, 4, CLK_MUX_HIWORD_MASK, },
0789 { HI3670_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
0790 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT,
0791 0x60, 6, 4, CLK_MUX_HIWORD_MASK, },
0792 { HI3670_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi1_p,
0793 ARRAY_SIZE(clk_mux_ldi1_p), CLK_SET_RATE_PARENT,
0794 0x64, 6, 4, CLK_MUX_HIWORD_MASK, },
0795 { HI3670_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
0796 ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT,
0797 0x88, 0, 4, CLK_MUX_HIWORD_MASK, },
0798 };
0799
0800 static const struct hisi_divider_clock hi3670_media1_divider_clks[] = {
0801 { HI3670_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_gate_vivobus_andgt",
0802 CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0803 { HI3670_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
0804 CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0805 { HI3670_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
0806 CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0807 { HI3670_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
0808 CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0809 { HI3670_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
0810 CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
0811 { HI3670_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
0812 CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
0813 };
0814
0815
0816 static const struct hisi_gate_clock hi3670_media2_gate_sep_clks[] = {
0817 { HI3670_CLK_GATE_VDECFREQ, "clk_gate_vdecfreq", "clk_div_vdec",
0818 CLK_SET_RATE_PARENT, 0x00, 8, 0, },
0819 { HI3670_CLK_GATE_VENCFREQ, "clk_gate_vencfreq", "clk_div_venc",
0820 CLK_SET_RATE_PARENT, 0x00, 5, 0, },
0821 { HI3670_CLK_GATE_ICSFREQ, "clk_gate_icsfreq", "clk_div_ics",
0822 CLK_SET_RATE_PARENT, 0x00, 2, 0, },
0823 };
0824
0825 static void hi3670_clk_crgctrl_init(struct device_node *np)
0826 {
0827 struct hisi_clock_data *clk_data;
0828
0829 int nr = ARRAY_SIZE(hi3670_fixed_rate_clks) +
0830 ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks) +
0831 ARRAY_SIZE(hi3670_crgctrl_gate_clks) +
0832 ARRAY_SIZE(hi3670_crgctrl_mux_clks) +
0833 ARRAY_SIZE(hi3670_crg_fixed_factor_clks) +
0834 ARRAY_SIZE(hi3670_crgctrl_divider_clks);
0835
0836 clk_data = hisi_clk_init(np, nr);
0837 if (!clk_data)
0838 return;
0839
0840 hisi_clk_register_fixed_rate(hi3670_fixed_rate_clks,
0841 ARRAY_SIZE(hi3670_fixed_rate_clks),
0842 clk_data);
0843 hisi_clk_register_gate_sep(hi3670_crgctrl_gate_sep_clks,
0844 ARRAY_SIZE(hi3670_crgctrl_gate_sep_clks),
0845 clk_data);
0846 hisi_clk_register_gate(hi3670_crgctrl_gate_clks,
0847 ARRAY_SIZE(hi3670_crgctrl_gate_clks),
0848 clk_data);
0849 hisi_clk_register_mux(hi3670_crgctrl_mux_clks,
0850 ARRAY_SIZE(hi3670_crgctrl_mux_clks),
0851 clk_data);
0852 hisi_clk_register_fixed_factor(hi3670_crg_fixed_factor_clks,
0853 ARRAY_SIZE(hi3670_crg_fixed_factor_clks),
0854 clk_data);
0855 hisi_clk_register_divider(hi3670_crgctrl_divider_clks,
0856 ARRAY_SIZE(hi3670_crgctrl_divider_clks),
0857 clk_data);
0858 }
0859
0860 static void hi3670_clk_pctrl_init(struct device_node *np)
0861 {
0862 struct hisi_clock_data *clk_data;
0863 int nr = ARRAY_SIZE(hi3670_pctrl_gate_clks);
0864
0865 clk_data = hisi_clk_init(np, nr);
0866 if (!clk_data)
0867 return;
0868 hisi_clk_register_gate(hi3670_pctrl_gate_clks,
0869 ARRAY_SIZE(hi3670_pctrl_gate_clks), clk_data);
0870 }
0871
0872 static void hi3670_clk_pmuctrl_init(struct device_node *np)
0873 {
0874 struct hisi_clock_data *clk_data;
0875 int nr = ARRAY_SIZE(hi3670_pmu_gate_clks);
0876
0877 clk_data = hisi_clk_init(np, nr);
0878 if (!clk_data)
0879 return;
0880
0881 hisi_clk_register_gate(hi3670_pmu_gate_clks,
0882 ARRAY_SIZE(hi3670_pmu_gate_clks), clk_data);
0883 }
0884
0885 static void hi3670_clk_sctrl_init(struct device_node *np)
0886 {
0887 struct hisi_clock_data *clk_data;
0888 int nr = ARRAY_SIZE(hi3670_sctrl_gate_sep_clks) +
0889 ARRAY_SIZE(hi3670_sctrl_gate_clks) +
0890 ARRAY_SIZE(hi3670_sctrl_mux_clks) +
0891 ARRAY_SIZE(hi3670_sctrl_divider_clks);
0892
0893 clk_data = hisi_clk_init(np, nr);
0894 if (!clk_data)
0895 return;
0896
0897 hisi_clk_register_gate_sep(hi3670_sctrl_gate_sep_clks,
0898 ARRAY_SIZE(hi3670_sctrl_gate_sep_clks),
0899 clk_data);
0900 hisi_clk_register_gate(hi3670_sctrl_gate_clks,
0901 ARRAY_SIZE(hi3670_sctrl_gate_clks),
0902 clk_data);
0903 hisi_clk_register_mux(hi3670_sctrl_mux_clks,
0904 ARRAY_SIZE(hi3670_sctrl_mux_clks),
0905 clk_data);
0906 hisi_clk_register_divider(hi3670_sctrl_divider_clks,
0907 ARRAY_SIZE(hi3670_sctrl_divider_clks),
0908 clk_data);
0909 }
0910
0911 static void hi3670_clk_iomcu_init(struct device_node *np)
0912 {
0913 struct hisi_clock_data *clk_data;
0914 int nr = ARRAY_SIZE(hi3670_iomcu_gate_sep_clks) +
0915 ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks);
0916
0917 clk_data = hisi_clk_init(np, nr);
0918 if (!clk_data)
0919 return;
0920
0921 hisi_clk_register_gate(hi3670_iomcu_gate_sep_clks,
0922 ARRAY_SIZE(hi3670_iomcu_gate_sep_clks), clk_data);
0923
0924 hisi_clk_register_fixed_factor(hi3670_iomcu_fixed_factor_clks,
0925 ARRAY_SIZE(hi3670_iomcu_fixed_factor_clks),
0926 clk_data);
0927 }
0928
0929 static void hi3670_clk_media1_init(struct device_node *np)
0930 {
0931 struct hisi_clock_data *clk_data;
0932
0933 int nr = ARRAY_SIZE(hi3670_media1_gate_sep_clks) +
0934 ARRAY_SIZE(hi3670_media1_gate_clks) +
0935 ARRAY_SIZE(hi3670_media1_mux_clks) +
0936 ARRAY_SIZE(hi3670_media1_divider_clks);
0937
0938 clk_data = hisi_clk_init(np, nr);
0939 if (!clk_data)
0940 return;
0941
0942 hisi_clk_register_gate_sep(hi3670_media1_gate_sep_clks,
0943 ARRAY_SIZE(hi3670_media1_gate_sep_clks),
0944 clk_data);
0945 hisi_clk_register_gate(hi3670_media1_gate_clks,
0946 ARRAY_SIZE(hi3670_media1_gate_clks),
0947 clk_data);
0948 hisi_clk_register_mux(hi3670_media1_mux_clks,
0949 ARRAY_SIZE(hi3670_media1_mux_clks),
0950 clk_data);
0951 hisi_clk_register_divider(hi3670_media1_divider_clks,
0952 ARRAY_SIZE(hi3670_media1_divider_clks),
0953 clk_data);
0954 }
0955
0956 static void hi3670_clk_media2_init(struct device_node *np)
0957 {
0958 struct hisi_clock_data *clk_data;
0959
0960 int nr = ARRAY_SIZE(hi3670_media2_gate_sep_clks);
0961
0962 clk_data = hisi_clk_init(np, nr);
0963 if (!clk_data)
0964 return;
0965
0966 hisi_clk_register_gate_sep(hi3670_media2_gate_sep_clks,
0967 ARRAY_SIZE(hi3670_media2_gate_sep_clks),
0968 clk_data);
0969 }
0970
0971 static const struct of_device_id hi3670_clk_match_table[] = {
0972 { .compatible = "hisilicon,hi3670-crgctrl",
0973 .data = hi3670_clk_crgctrl_init },
0974 { .compatible = "hisilicon,hi3670-pctrl",
0975 .data = hi3670_clk_pctrl_init },
0976 { .compatible = "hisilicon,hi3670-pmuctrl",
0977 .data = hi3670_clk_pmuctrl_init },
0978 { .compatible = "hisilicon,hi3670-sctrl",
0979 .data = hi3670_clk_sctrl_init },
0980 { .compatible = "hisilicon,hi3670-iomcu",
0981 .data = hi3670_clk_iomcu_init },
0982 { .compatible = "hisilicon,hi3670-media1-crg",
0983 .data = hi3670_clk_media1_init },
0984 { .compatible = "hisilicon,hi3670-media2-crg",
0985 .data = hi3670_clk_media2_init },
0986 { }
0987 };
0988
0989 static int hi3670_clk_probe(struct platform_device *pdev)
0990 {
0991 struct device *dev = &pdev->dev;
0992 struct device_node *np = pdev->dev.of_node;
0993 void (*init_func)(struct device_node *np);
0994
0995 init_func = of_device_get_match_data(dev);
0996 if (!init_func)
0997 return -ENODEV;
0998
0999 init_func(np);
1000
1001 return 0;
1002 }
1003
1004 static struct platform_driver hi3670_clk_driver = {
1005 .probe = hi3670_clk_probe,
1006 .driver = {
1007 .name = "hi3670-clk",
1008 .of_match_table = hi3670_clk_match_table,
1009 },
1010 };
1011
1012 static int __init hi3670_clk_init(void)
1013 {
1014 return platform_driver_register(&hi3670_clk_driver);
1015 }
1016 core_initcall(hi3670_clk_init);
