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0007 #include <dt-bindings/clock/hi3660-clock.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/of_device.h>
0010 #include <linux/platform_device.h>
0011 #include "clk.h"
0012
0013 static const struct hisi_fixed_rate_clock hi3660_fixed_rate_clks[] = {
0014 { HI3660_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
0015 { HI3660_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
0016 { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, },
0017 { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, },
0018 { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
0019 { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000UL, },
0020 { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, },
0021 { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
0022 { HI3660_PCLK, "pclk", NULL, 0, 20000000, },
0023 { HI3660_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
0024 { HI3660_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
0025 { HI3660_OSC32K, "osc32k", NULL, 0, 32764, },
0026 { HI3660_OSC19M, "osc19m", NULL, 0, 19200000, },
0027 { HI3660_CLK_480M, "clk_480m", NULL, 0, 480000000, },
0028 { HI3660_CLK_INV, "clk_inv", NULL, 0, 10000000, },
0029 };
0030
0031
0032 static const struct hisi_fixed_factor_clock hi3660_crg_fixed_factor_clks[] = {
0033 { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
0034 { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
0035 { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
0036 { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
0037 { HI3660_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_iomcu", 1, 4, 0, },
0038 { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, },
0039 { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, },
0040 { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, },
0041 { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, },
0042 { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, },
0043 { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, },
0044 { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },
0045 { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 },
0046 { HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, },
0047 { HI3660_CLK_FAC_ISP_SNCLK, "clk_isp_snclk_fac", "clk_isp_snclk_angt",
0048 1, 10, 0, },
0049 };
0050
0051 static const struct hisi_gate_clock hi3660_crgctrl_gate_sep_clks[] = {
0052 { HI3660_PERI_VOLT_HOLD, "peri_volt_hold", "clkin_sys",
0053 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
0054 { HI3660_HCLK_GATE_SDIO0, "hclk_gate_sdio0", "clk_div_sysbus",
0055 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
0056 { HI3660_HCLK_GATE_SD, "hclk_gate_sd", "clk_div_sysbus",
0057 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
0058 { HI3660_CLK_GATE_AOMM, "clk_gate_aomm", "clk_div_aomm",
0059 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
0060 { HI3660_PCLK_GPIO0, "pclk_gpio0", "clk_div_cfgbus",
0061 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
0062 { HI3660_PCLK_GPIO1, "pclk_gpio1", "clk_div_cfgbus",
0063 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
0064 { HI3660_PCLK_GPIO2, "pclk_gpio2", "clk_div_cfgbus",
0065 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
0066 { HI3660_PCLK_GPIO3, "pclk_gpio3", "clk_div_cfgbus",
0067 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
0068 { HI3660_PCLK_GPIO4, "pclk_gpio4", "clk_div_cfgbus",
0069 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
0070 { HI3660_PCLK_GPIO5, "pclk_gpio5", "clk_div_cfgbus",
0071 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
0072 { HI3660_PCLK_GPIO6, "pclk_gpio6", "clk_div_cfgbus",
0073 CLK_SET_RATE_PARENT, 0x10, 6, 0, },
0074 { HI3660_PCLK_GPIO7, "pclk_gpio7", "clk_div_cfgbus",
0075 CLK_SET_RATE_PARENT, 0x10, 7, 0, },
0076 { HI3660_PCLK_GPIO8, "pclk_gpio8", "clk_div_cfgbus",
0077 CLK_SET_RATE_PARENT, 0x10, 8, 0, },
0078 { HI3660_PCLK_GPIO9, "pclk_gpio9", "clk_div_cfgbus",
0079 CLK_SET_RATE_PARENT, 0x10, 9, 0, },
0080 { HI3660_PCLK_GPIO10, "pclk_gpio10", "clk_div_cfgbus",
0081 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
0082 { HI3660_PCLK_GPIO11, "pclk_gpio11", "clk_div_cfgbus",
0083 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
0084 { HI3660_PCLK_GPIO12, "pclk_gpio12", "clk_div_cfgbus",
0085 CLK_SET_RATE_PARENT, 0x10, 12, 0, },
0086 { HI3660_PCLK_GPIO13, "pclk_gpio13", "clk_div_cfgbus",
0087 CLK_SET_RATE_PARENT, 0x10, 13, 0, },
0088 { HI3660_PCLK_GPIO14, "pclk_gpio14", "clk_div_cfgbus",
0089 CLK_SET_RATE_PARENT, 0x10, 14, 0, },
0090 { HI3660_PCLK_GPIO15, "pclk_gpio15", "clk_div_cfgbus",
0091 CLK_SET_RATE_PARENT, 0x10, 15, 0, },
0092 { HI3660_PCLK_GPIO16, "pclk_gpio16", "clk_div_cfgbus",
0093 CLK_SET_RATE_PARENT, 0x10, 16, 0, },
0094 { HI3660_PCLK_GPIO17, "pclk_gpio17", "clk_div_cfgbus",
0095 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
0096 { HI3660_PCLK_GPIO18, "pclk_gpio18", "clk_div_ioperi",
0097 CLK_SET_RATE_PARENT, 0x10, 18, 0, },
0098 { HI3660_PCLK_GPIO19, "pclk_gpio19", "clk_div_ioperi",
0099 CLK_SET_RATE_PARENT, 0x10, 19, 0, },
0100 { HI3660_PCLK_GPIO20, "pclk_gpio20", "clk_div_cfgbus",
0101 CLK_SET_RATE_PARENT, 0x10, 20, 0, },
0102 { HI3660_PCLK_GPIO21, "pclk_gpio21", "clk_div_cfgbus",
0103 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
0104 { HI3660_CLK_GATE_SPI3, "clk_gate_spi3", "clk_div_ioperi",
0105 CLK_SET_RATE_PARENT, 0x10, 30, 0, },
0106 { HI3660_CLK_GATE_I2C7, "clk_gate_i2c7", "clk_mux_i2c",
0107 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
0108 { HI3660_CLK_GATE_I2C3, "clk_gate_i2c3", "clk_mux_i2c",
0109 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
0110 { HI3660_CLK_GATE_SPI1, "clk_gate_spi1", "clk_mux_spi",
0111 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
0112 { HI3660_CLK_GATE_UART1, "clk_gate_uart1", "clk_mux_uarth",
0113 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
0114 { HI3660_CLK_GATE_UART2, "clk_gate_uart2", "clk_mux_uart1",
0115 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
0116 { HI3660_CLK_GATE_UART4, "clk_gate_uart4", "clk_mux_uarth",
0117 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
0118 { HI3660_CLK_GATE_UART5, "clk_gate_uart5", "clk_mux_uart1",
0119 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
0120 { HI3660_CLK_GATE_I2C4, "clk_gate_i2c4", "clk_mux_i2c",
0121 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
0122 { HI3660_CLK_GATE_DMAC, "clk_gate_dmac", "clk_div_sysbus",
0123 CLK_SET_RATE_PARENT, 0x30, 1, 0, },
0124 { HI3660_CLK_GATE_VENC, "clk_gate_venc", "clk_div_venc",
0125 CLK_SET_RATE_PARENT, 0x30, 10, 0, },
0126 { HI3660_CLK_GATE_VDEC, "clk_gate_vdec", "clk_div_vdec",
0127 CLK_SET_RATE_PARENT, 0x30, 11, 0, },
0128 { HI3660_PCLK_GATE_DSS, "pclk_gate_dss", "clk_div_cfgbus",
0129 CLK_SET_RATE_PARENT, 0x30, 12, 0, },
0130 { HI3660_ACLK_GATE_DSS, "aclk_gate_dss", "clk_gate_vivobus",
0131 CLK_SET_RATE_PARENT, 0x30, 13, 0, },
0132 { HI3660_CLK_GATE_LDI1, "clk_gate_ldi1", "clk_div_ldi1",
0133 CLK_SET_RATE_PARENT, 0x30, 14, 0, },
0134 { HI3660_CLK_GATE_LDI0, "clk_gate_ldi0", "clk_div_ldi0",
0135 CLK_SET_RATE_PARENT, 0x30, 15, 0, },
0136 { HI3660_CLK_GATE_VIVOBUS, "clk_gate_vivobus", "clk_div_vivobus",
0137 CLK_SET_RATE_PARENT, 0x30, 16, 0, },
0138 { HI3660_CLK_GATE_EDC0, "clk_gate_edc0", "clk_div_edc0",
0139 CLK_SET_RATE_PARENT, 0x30, 17, 0, },
0140 { HI3660_CLK_GATE_TXDPHY0_CFG, "clk_gate_txdphy0_cfg", "clkin_sys",
0141 CLK_SET_RATE_PARENT, 0x30, 28, 0, },
0142 { HI3660_CLK_GATE_TXDPHY0_REF, "clk_gate_txdphy0_ref", "clkin_sys",
0143 CLK_SET_RATE_PARENT, 0x30, 29, 0, },
0144 { HI3660_CLK_GATE_TXDPHY1_CFG, "clk_gate_txdphy1_cfg", "clkin_sys",
0145 CLK_SET_RATE_PARENT, 0x30, 30, 0, },
0146 { HI3660_CLK_GATE_TXDPHY1_REF, "clk_gate_txdphy1_ref", "clkin_sys",
0147 CLK_SET_RATE_PARENT, 0x30, 31, 0, },
0148 { HI3660_ACLK_GATE_USB3OTG, "aclk_gate_usb3otg", "clk_div_mmc0bus",
0149 CLK_SET_RATE_PARENT, 0x40, 1, 0, },
0150 { HI3660_CLK_GATE_SPI4, "clk_gate_spi4", "clk_mux_spi",
0151 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
0152 { HI3660_CLK_GATE_SD, "clk_gate_sd", "clk_mux_sd_sys",
0153 CLK_SET_RATE_PARENT, 0x40, 17, 0, },
0154 { HI3660_CLK_GATE_SDIO0, "clk_gate_sdio0", "clk_mux_sdio_sys",
0155 CLK_SET_RATE_PARENT, 0x40, 19, 0, },
0156 { HI3660_CLK_GATE_ISP_SNCLK0, "clk_gate_isp_snclk0",
0157 "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 16, 0, },
0158 { HI3660_CLK_GATE_ISP_SNCLK1, "clk_gate_isp_snclk1",
0159 "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
0160 { HI3660_CLK_GATE_ISP_SNCLK2, "clk_gate_isp_snclk2",
0161 "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
0162
0163
0164
0165
0166 { HI3660_CLK_GATE_UFS_SUBSYS, "clk_gate_ufs_subsys", "clk_div_sysbus",
0167 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, },
0168 { HI3660_PCLK_GATE_DSI0, "pclk_gate_dsi0", "clk_div_cfgbus",
0169 CLK_SET_RATE_PARENT, 0x50, 28, 0, },
0170 { HI3660_PCLK_GATE_DSI1, "pclk_gate_dsi1", "clk_div_cfgbus",
0171 CLK_SET_RATE_PARENT, 0x50, 29, 0, },
0172 { HI3660_ACLK_GATE_PCIE, "aclk_gate_pcie", "clk_div_mmc1bus",
0173 CLK_SET_RATE_PARENT, 0x420, 5, 0, },
0174 { HI3660_PCLK_GATE_PCIE_SYS, "pclk_gate_pcie_sys", "clk_div_mmc1bus",
0175 CLK_SET_RATE_PARENT, 0x420, 7, 0, },
0176 { HI3660_CLK_GATE_PCIEAUX, "clk_gate_pcieaux", "clkin_sys",
0177 CLK_SET_RATE_PARENT, 0x420, 8, 0, },
0178 { HI3660_PCLK_GATE_PCIE_PHY, "pclk_gate_pcie_phy", "clk_div_mmc1bus",
0179 CLK_SET_RATE_PARENT, 0x420, 9, 0, },
0180 };
0181
0182 static const struct hisi_gate_clock hi3660_crgctrl_gate_clks[] = {
0183 { HI3660_CLK_ANDGT_LDI0, "clk_andgt_ldi0", "clk_mux_ldi0",
0184 CLK_SET_RATE_PARENT, 0xf0, 6, CLK_GATE_HIWORD_MASK, },
0185 { HI3660_CLK_ANDGT_LDI1, "clk_andgt_ldi1", "clk_mux_ldi1",
0186 CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, },
0187 { HI3660_CLK_ANDGT_EDC0, "clk_andgt_edc0", "clk_mux_edc0",
0188 CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, },
0189 { HI3660_CLK_ANDGT_VDEC, "clk_andgt_vdec", "clk_mux_vdec",
0190 CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, },
0191 { HI3660_CLK_ANDGT_VENC, "clk_andgt_venc", "clk_mux_venc",
0192 CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, },
0193 { HI3660_CLK_GATE_UFSPHY_GT, "clk_gate_ufsphy_gt", "clk_div_ufsperi",
0194 CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, },
0195 { HI3660_CLK_ANDGT_MMC, "clk_andgt_mmc", "clk_mux_mmc_pll",
0196 CLK_SET_RATE_PARENT, 0xf4, 2, CLK_GATE_HIWORD_MASK, },
0197 { HI3660_CLK_ANDGT_SD, "clk_andgt_sd", "clk_mux_sd_pll",
0198 CLK_SET_RATE_PARENT, 0xf4, 3, CLK_GATE_HIWORD_MASK, },
0199 { HI3660_CLK_A53HPM_ANDGT, "clk_a53hpm_andgt", "clk_mux_a53hpm",
0200 CLK_SET_RATE_PARENT, 0xf4, 7, CLK_GATE_HIWORD_MASK, },
0201 { HI3660_CLK_ANDGT_SDIO, "clk_andgt_sdio", "clk_mux_sdio_pll",
0202 CLK_SET_RATE_PARENT, 0xf4, 8, CLK_GATE_HIWORD_MASK, },
0203 { HI3660_CLK_ANDGT_UART0, "clk_andgt_uart0", "clk_div_320m",
0204 CLK_SET_RATE_PARENT, 0xf4, 9, CLK_GATE_HIWORD_MASK, },
0205 { HI3660_CLK_ANDGT_UART1, "clk_andgt_uart1", "clk_div_320m",
0206 CLK_SET_RATE_PARENT, 0xf4, 10, CLK_GATE_HIWORD_MASK, },
0207 { HI3660_CLK_ANDGT_UARTH, "clk_andgt_uarth", "clk_div_320m",
0208 CLK_SET_RATE_PARENT, 0xf4, 11, CLK_GATE_HIWORD_MASK, },
0209 { HI3660_CLK_ANDGT_SPI, "clk_andgt_spi", "clk_div_320m",
0210 CLK_SET_RATE_PARENT, 0xf4, 13, CLK_GATE_HIWORD_MASK, },
0211 { HI3660_CLK_VIVOBUS_ANDGT, "clk_vivobus_andgt", "clk_mux_vivobus",
0212 CLK_SET_RATE_PARENT, 0xf8, 1, CLK_GATE_HIWORD_MASK, },
0213 { HI3660_CLK_AOMM_ANDGT, "clk_aomm_andgt", "clk_ppll2",
0214 CLK_SET_RATE_PARENT, 0xf8, 3, CLK_GATE_HIWORD_MASK, },
0215 { HI3660_CLK_320M_PLL_GT, "clk_320m_pll_gt", "clk_mux_320m",
0216 CLK_SET_RATE_PARENT, 0xf8, 10, 0, },
0217 { HI3660_CLK_ANGT_ISP_SNCLK, "clk_isp_snclk_angt", "clk_div_a53hpm",
0218 CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
0219 { HI3660_AUTODIV_EMMC0BUS, "autodiv_emmc0bus", "autodiv_sysbus",
0220 CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
0221 { HI3660_AUTODIV_SYSBUS, "autodiv_sysbus", "clk_div_sysbus",
0222 CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
0223 { HI3660_CLK_GATE_UFSPHY_CFG, "clk_gate_ufsphy_cfg",
0224 "clk_div_ufsphy_cfg", CLK_SET_RATE_PARENT, 0x420, 12, 0, },
0225 { HI3660_CLK_GATE_UFSIO_REF, "clk_gate_ufsio_ref",
0226 "clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
0227 };
0228
0229 static const char *const
0230 clk_mux_sysbus_p[] = {"clk_ppll1", "clk_ppll0"};
0231 static const char *const
0232 clk_mux_sdio_sys_p[] = {"clk_factor_mmc", "clk_div_sdio",};
0233 static const char *const
0234 clk_mux_sd_sys_p[] = {"clk_factor_mmc", "clk_div_sd",};
0235 static const char *const
0236 clk_mux_pll_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll2",};
0237 static const char *const
0238 clk_mux_pll0123_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll2", "clk_ppll3",};
0239 static const char *const
0240 clk_mux_edc0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll1", "clk_inv",
0241 "clk_ppll2", "clk_inv", "clk_inv", "clk_inv",
0242 "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
0243 "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
0244 static const char *const
0245 clk_mux_ldi0_p[] = {"clk_inv", "clk_ppll0", "clk_ppll2", "clk_inv",
0246 "clk_ppll1", "clk_inv", "clk_inv", "clk_inv",
0247 "clk_ppll3", "clk_inv", "clk_inv", "clk_inv",
0248 "clk_inv", "clk_inv", "clk_inv", "clk_inv",};
0249 static const char *const
0250 clk_mux_uart0_p[] = {"clkin_sys", "clk_div_uart0",};
0251 static const char *const
0252 clk_mux_uart1_p[] = {"clkin_sys", "clk_div_uart1",};
0253 static const char *const
0254 clk_mux_uarth_p[] = {"clkin_sys", "clk_div_uarth",};
0255 static const char *const
0256 clk_mux_pll02p[] = {"clk_ppll0", "clk_ppll2",};
0257 static const char *const
0258 clk_mux_ioperi_p[] = {"clk_div_320m", "clk_div_a53hpm",};
0259 static const char *const
0260 clk_mux_spi_p[] = {"clkin_sys", "clk_div_spi",};
0261 static const char *const
0262 clk_mux_i2c_p[] = {"clkin_sys", "clk_div_i2c",};
0263 static const char *const
0264 clk_mux_venc_p[] = {"clk_ppll0", "clk_ppll1", "clk_ppll3", "clk_ppll3",};
0265 static const char *const
0266 clk_mux_isp_snclk_p[] = {"clkin_sys", "clk_isp_snclk_div"};
0267
0268 static const struct hisi_mux_clock hi3660_crgctrl_mux_clks[] = {
0269 { HI3660_CLK_MUX_SYSBUS, "clk_mux_sysbus", clk_mux_sysbus_p,
0270 ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
0271 CLK_MUX_HIWORD_MASK, },
0272 { HI3660_CLK_MUX_UART0, "clk_mux_uart0", clk_mux_uart0_p,
0273 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
0274 CLK_MUX_HIWORD_MASK, },
0275 { HI3660_CLK_MUX_UART1, "clk_mux_uart1", clk_mux_uart1_p,
0276 ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,
0277 CLK_MUX_HIWORD_MASK, },
0278 { HI3660_CLK_MUX_UARTH, "clk_mux_uarth", clk_mux_uarth_p,
0279 ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, 0xac, 4, 1,
0280 CLK_MUX_HIWORD_MASK, },
0281 { HI3660_CLK_MUX_SPI, "clk_mux_spi", clk_mux_spi_p,
0282 ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, 0xac, 8, 1,
0283 CLK_MUX_HIWORD_MASK, },
0284 { HI3660_CLK_MUX_I2C, "clk_mux_i2c", clk_mux_i2c_p,
0285 ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, 0xac, 13, 1,
0286 CLK_MUX_HIWORD_MASK, },
0287 { HI3660_CLK_MUX_MMC_PLL, "clk_mux_mmc_pll", clk_mux_pll02p,
0288 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xb4, 0, 1,
0289 CLK_MUX_HIWORD_MASK, },
0290 { HI3660_CLK_MUX_LDI1, "clk_mux_ldi1", clk_mux_ldi0_p,
0291 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
0292 CLK_MUX_HIWORD_MASK, },
0293 { HI3660_CLK_MUX_LDI0, "clk_mux_ldi0", clk_mux_ldi0_p,
0294 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
0295 CLK_MUX_HIWORD_MASK, },
0296 { HI3660_CLK_MUX_SD_PLL, "clk_mux_sd_pll", clk_mux_pll_p,
0297 ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xb8, 4, 2,
0298 CLK_MUX_HIWORD_MASK, },
0299 { HI3660_CLK_MUX_SD_SYS, "clk_mux_sd_sys", clk_mux_sd_sys_p,
0300 ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, 0xb8, 6, 1,
0301 CLK_MUX_HIWORD_MASK, },
0302 { HI3660_CLK_MUX_EDC0, "clk_mux_edc0", clk_mux_edc0_p,
0303 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
0304 CLK_MUX_HIWORD_MASK, },
0305 { HI3660_CLK_MUX_SDIO_SYS, "clk_mux_sdio_sys", clk_mux_sdio_sys_p,
0306 ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xc0, 6, 1,
0307 CLK_MUX_HIWORD_MASK, },
0308 { HI3660_CLK_MUX_SDIO_PLL, "clk_mux_sdio_pll", clk_mux_pll_p,
0309 ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2,
0310 CLK_MUX_HIWORD_MASK, },
0311 { HI3660_CLK_MUX_VENC, "clk_mux_venc", clk_mux_venc_p,
0312 ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2,
0313 CLK_MUX_HIWORD_MASK, },
0314 { HI3660_CLK_MUX_VDEC, "clk_mux_vdec", clk_mux_pll0123_p,
0315 ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2,
0316 CLK_MUX_HIWORD_MASK, },
0317 { HI3660_CLK_MUX_VIVOBUS, "clk_mux_vivobus", clk_mux_pll0123_p,
0318 ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2,
0319 CLK_MUX_HIWORD_MASK, },
0320 { HI3660_CLK_MUX_A53HPM, "clk_mux_a53hpm", clk_mux_pll02p,
0321 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xd4, 9, 1,
0322 CLK_MUX_HIWORD_MASK, },
0323 { HI3660_CLK_MUX_320M, "clk_mux_320m", clk_mux_pll02p,
0324 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1,
0325 CLK_MUX_HIWORD_MASK, },
0326 { HI3660_CLK_MUX_ISP_SNCLK, "clk_isp_snclk_mux", clk_mux_isp_snclk_p,
0327 ARRAY_SIZE(clk_mux_isp_snclk_p), CLK_SET_RATE_PARENT, 0x108, 3, 1,
0328 CLK_MUX_HIWORD_MASK, },
0329 { HI3660_CLK_MUX_IOPERI, "clk_mux_ioperi", clk_mux_ioperi_p,
0330 ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1,
0331 CLK_MUX_HIWORD_MASK, },
0332 };
0333
0334 static const struct hisi_divider_clock hi3660_crgctrl_divider_clks[] = {
0335 { HI3660_CLK_DIV_UART0, "clk_div_uart0", "clk_andgt_uart0",
0336 CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
0337 { HI3660_CLK_DIV_UART1, "clk_div_uart1", "clk_andgt_uart1",
0338 CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
0339 { HI3660_CLK_DIV_UARTH, "clk_div_uarth", "clk_andgt_uarth",
0340 CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
0341 { HI3660_CLK_DIV_MMC, "clk_div_mmc", "clk_andgt_mmc",
0342 CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, },
0343 { HI3660_CLK_DIV_SD, "clk_div_sd", "clk_andgt_sd",
0344 CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
0345 { HI3660_CLK_DIV_EDC0, "clk_div_edc0", "clk_andgt_edc0",
0346 CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0347 { HI3660_CLK_DIV_LDI0, "clk_div_ldi0", "clk_andgt_ldi0",
0348 CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
0349 { HI3660_CLK_DIV_SDIO, "clk_div_sdio", "clk_andgt_sdio",
0350 CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
0351 { HI3660_CLK_DIV_LDI1, "clk_div_ldi1", "clk_andgt_ldi1",
0352 CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
0353 { HI3660_CLK_DIV_SPI, "clk_div_spi", "clk_andgt_spi",
0354 CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
0355 { HI3660_CLK_DIV_VENC, "clk_div_venc", "clk_andgt_venc",
0356 CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, },
0357 { HI3660_CLK_DIV_VDEC, "clk_div_vdec", "clk_andgt_vdec",
0358 CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
0359 { HI3660_CLK_DIV_VIVOBUS, "clk_div_vivobus", "clk_vivobus_andgt",
0360 CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, },
0361 { HI3660_CLK_DIV_I2C, "clk_div_i2c", "clk_div_320m",
0362 CLK_SET_RATE_PARENT, 0xe8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
0363 { HI3660_CLK_DIV_UFSPHY, "clk_div_ufsphy_cfg", "clk_gate_ufsphy_gt",
0364 CLK_SET_RATE_PARENT, 0xe8, 9, 2, CLK_DIVIDER_HIWORD_MASK, },
0365 { HI3660_CLK_DIV_CFGBUS, "clk_div_cfgbus", "clk_div_sysbus",
0366 CLK_SET_RATE_PARENT, 0xec, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
0367 { HI3660_CLK_DIV_MMC0BUS, "clk_div_mmc0bus", "autodiv_emmc0bus",
0368 CLK_SET_RATE_PARENT, 0xec, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
0369 { HI3660_CLK_DIV_MMC1BUS, "clk_div_mmc1bus", "clk_div_sysbus",
0370 CLK_SET_RATE_PARENT, 0xec, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
0371 { HI3660_CLK_DIV_UFSPERI, "clk_div_ufsperi", "clk_gate_ufs_subsys",
0372 CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, },
0373 { HI3660_CLK_DIV_AOMM, "clk_div_aomm", "clk_aomm_andgt",
0374 CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, },
0375 { HI3660_CLK_DIV_ISP_SNCLK, "clk_isp_snclk_div", "clk_isp_snclk_fac",
0376 CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
0377 { HI3660_CLK_DIV_IOPERI, "clk_div_ioperi", "clk_mux_ioperi",
0378 CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
0379 };
0380
0381
0382
0383 static const struct hisi_gate_clock hi3660_pmu_gate_clks[] = {
0384 { HI3660_GATE_ABB_192, "clk_gate_abb_192", "clkin_sys",
0385 CLK_SET_RATE_PARENT, (0x10a << 2), 3, 0, },
0386 };
0387
0388
0389 static const struct hisi_gate_clock hi3660_pctrl_gate_clks[] = {
0390 { HI3660_GATE_UFS_TCXO_EN, "clk_gate_ufs_tcxo_en",
0391 "clk_gate_abb_192", CLK_SET_RATE_PARENT, 0x10, 0,
0392 CLK_GATE_HIWORD_MASK, },
0393 { HI3660_GATE_USB_TCXO_EN, "clk_gate_usb_tcxo_en", "clk_gate_abb_192",
0394 CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
0395 };
0396
0397
0398 static const struct hisi_gate_clock hi3660_sctrl_gate_sep_clks[] = {
0399 { HI3660_PCLK_AO_GPIO0, "pclk_ao_gpio0", "clk_div_aobus",
0400 CLK_SET_RATE_PARENT, 0x160, 11, 0, },
0401 { HI3660_PCLK_AO_GPIO1, "pclk_ao_gpio1", "clk_div_aobus",
0402 CLK_SET_RATE_PARENT, 0x160, 12, 0, },
0403 { HI3660_PCLK_AO_GPIO2, "pclk_ao_gpio2", "clk_div_aobus",
0404 CLK_SET_RATE_PARENT, 0x160, 13, 0, },
0405 { HI3660_PCLK_AO_GPIO3, "pclk_ao_gpio3", "clk_div_aobus",
0406 CLK_SET_RATE_PARENT, 0x160, 14, 0, },
0407 { HI3660_PCLK_AO_GPIO4, "pclk_ao_gpio4", "clk_div_aobus",
0408 CLK_SET_RATE_PARENT, 0x160, 21, 0, },
0409 { HI3660_PCLK_AO_GPIO5, "pclk_ao_gpio5", "clk_div_aobus",
0410 CLK_SET_RATE_PARENT, 0x160, 22, 0, },
0411 { HI3660_PCLK_AO_GPIO6, "pclk_ao_gpio6", "clk_div_aobus",
0412 CLK_SET_RATE_PARENT, 0x160, 25, 0, },
0413 { HI3660_PCLK_GATE_MMBUF, "pclk_gate_mmbuf", "pclk_div_mmbuf",
0414 CLK_SET_RATE_PARENT, 0x170, 23, 0, },
0415 { HI3660_CLK_GATE_DSS_AXI_MM, "clk_gate_dss_axi_mm", "aclk_mux_mmbuf",
0416 CLK_SET_RATE_PARENT, 0x170, 24, 0, },
0417 };
0418
0419 static const struct hisi_gate_clock hi3660_sctrl_gate_clks[] = {
0420 { HI3660_PCLK_MMBUF_ANDGT, "pclk_mmbuf_andgt", "clk_sw_mmbuf",
0421 CLK_SET_RATE_PARENT, 0x258, 7, CLK_GATE_HIWORD_MASK, },
0422 { HI3660_CLK_MMBUF_PLL_ANDGT, "clk_mmbuf_pll_andgt", "clk_ppll0",
0423 CLK_SET_RATE_PARENT, 0x260, 11, CLK_DIVIDER_HIWORD_MASK, },
0424 { HI3660_CLK_FLL_MMBUF_ANDGT, "clk_fll_mmbuf_andgt", "clk_fll_src",
0425 CLK_SET_RATE_PARENT, 0x260, 12, CLK_DIVIDER_HIWORD_MASK, },
0426 { HI3660_CLK_SYS_MMBUF_ANDGT, "clk_sys_mmbuf_andgt", "clkin_sys",
0427 CLK_SET_RATE_PARENT, 0x260, 13, CLK_DIVIDER_HIWORD_MASK, },
0428 { HI3660_CLK_GATE_PCIEPHY_GT, "clk_gate_pciephy_gt", "clk_ppll0",
0429 CLK_SET_RATE_PARENT, 0x268, 11, CLK_DIVIDER_HIWORD_MASK, },
0430 };
0431
0432 static const char *const
0433 aclk_mux_mmbuf_p[] = {"aclk_div_mmbuf", "clk_gate_aomm",};
0434 static const char *const
0435 clk_sw_mmbuf_p[] = {"clk_sys_mmbuf_andgt", "clk_fll_mmbuf_andgt",
0436 "aclk_mux_mmbuf", "aclk_mux_mmbuf"};
0437
0438 static const struct hisi_mux_clock hi3660_sctrl_mux_clks[] = {
0439 { HI3660_ACLK_MUX_MMBUF, "aclk_mux_mmbuf", aclk_mux_mmbuf_p,
0440 ARRAY_SIZE(aclk_mux_mmbuf_p), CLK_SET_RATE_PARENT, 0x250, 12, 1,
0441 CLK_MUX_HIWORD_MASK, },
0442 { HI3660_CLK_SW_MMBUF, "clk_sw_mmbuf", clk_sw_mmbuf_p,
0443 ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, 0x258, 8, 2,
0444 CLK_MUX_HIWORD_MASK, },
0445 };
0446
0447 static const struct hisi_divider_clock hi3660_sctrl_divider_clks[] = {
0448 { HI3660_CLK_DIV_AOBUS, "clk_div_aobus", "clk_ppll0",
0449 CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
0450 { HI3660_PCLK_DIV_MMBUF, "pclk_div_mmbuf", "pclk_mmbuf_andgt",
0451 CLK_SET_RATE_PARENT, 0x258, 10, 2, CLK_DIVIDER_HIWORD_MASK, },
0452 { HI3660_ACLK_DIV_MMBUF, "aclk_div_mmbuf", "clk_mmbuf_pll_andgt",
0453 CLK_SET_RATE_PARENT, 0x258, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
0454 { HI3660_CLK_DIV_PCIEPHY, "clk_div_pciephy", "clk_gate_pciephy_gt",
0455 CLK_SET_RATE_PARENT, 0x268, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
0456 };
0457
0458
0459 static const struct hisi_gate_clock hi3660_iomcu_gate_sep_clks[] = {
0460 { HI3660_CLK_I2C0_IOMCU, "clk_i2c0_iomcu", "clk_fll_src",
0461 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
0462 { HI3660_CLK_I2C1_IOMCU, "clk_i2c1_iomcu", "clk_fll_src",
0463 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
0464 { HI3660_CLK_I2C2_IOMCU, "clk_i2c2_iomcu", "clk_fll_src",
0465 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
0466 { HI3660_CLK_I2C6_IOMCU, "clk_i2c6_iomcu", "clk_fll_src",
0467 CLK_SET_RATE_PARENT, 0x10, 27, 0, },
0468 { HI3660_CLK_IOMCU_PERI0, "iomcu_peri0", "clk_ppll0",
0469 CLK_SET_RATE_PARENT, 0x90, 0, 0, },
0470 };
0471
0472 static struct hisi_clock_data *clk_crgctrl_data;
0473
0474 static void hi3660_clk_iomcu_init(struct device_node *np)
0475 {
0476 struct hisi_clock_data *clk_data;
0477 int nr = ARRAY_SIZE(hi3660_iomcu_gate_sep_clks);
0478
0479 clk_data = hisi_clk_init(np, nr);
0480 if (!clk_data)
0481 return;
0482
0483 hisi_clk_register_gate_sep(hi3660_iomcu_gate_sep_clks,
0484 ARRAY_SIZE(hi3660_iomcu_gate_sep_clks),
0485 clk_data);
0486 }
0487
0488 static void hi3660_clk_pmuctrl_init(struct device_node *np)
0489 {
0490 struct hisi_clock_data *clk_data;
0491 int nr = ARRAY_SIZE(hi3660_pmu_gate_clks);
0492
0493 clk_data = hisi_clk_init(np, nr);
0494 if (!clk_data)
0495 return;
0496
0497 hisi_clk_register_gate(hi3660_pmu_gate_clks,
0498 ARRAY_SIZE(hi3660_pmu_gate_clks), clk_data);
0499 }
0500
0501 static void hi3660_clk_pctrl_init(struct device_node *np)
0502 {
0503 struct hisi_clock_data *clk_data;
0504 int nr = ARRAY_SIZE(hi3660_pctrl_gate_clks);
0505
0506 clk_data = hisi_clk_init(np, nr);
0507 if (!clk_data)
0508 return;
0509 hisi_clk_register_gate(hi3660_pctrl_gate_clks,
0510 ARRAY_SIZE(hi3660_pctrl_gate_clks), clk_data);
0511 }
0512
0513 static void hi3660_clk_sctrl_init(struct device_node *np)
0514 {
0515 struct hisi_clock_data *clk_data;
0516 int nr = ARRAY_SIZE(hi3660_sctrl_gate_clks) +
0517 ARRAY_SIZE(hi3660_sctrl_gate_sep_clks) +
0518 ARRAY_SIZE(hi3660_sctrl_mux_clks) +
0519 ARRAY_SIZE(hi3660_sctrl_divider_clks);
0520
0521 clk_data = hisi_clk_init(np, nr);
0522 if (!clk_data)
0523 return;
0524 hisi_clk_register_gate(hi3660_sctrl_gate_clks,
0525 ARRAY_SIZE(hi3660_sctrl_gate_clks), clk_data);
0526 hisi_clk_register_gate_sep(hi3660_sctrl_gate_sep_clks,
0527 ARRAY_SIZE(hi3660_sctrl_gate_sep_clks),
0528 clk_data);
0529 hisi_clk_register_mux(hi3660_sctrl_mux_clks,
0530 ARRAY_SIZE(hi3660_sctrl_mux_clks), clk_data);
0531 hisi_clk_register_divider(hi3660_sctrl_divider_clks,
0532 ARRAY_SIZE(hi3660_sctrl_divider_clks),
0533 clk_data);
0534 }
0535
0536 static void hi3660_clk_crgctrl_early_init(struct device_node *np)
0537 {
0538 int nr = ARRAY_SIZE(hi3660_fixed_rate_clks) +
0539 ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks) +
0540 ARRAY_SIZE(hi3660_crgctrl_gate_clks) +
0541 ARRAY_SIZE(hi3660_crgctrl_mux_clks) +
0542 ARRAY_SIZE(hi3660_crg_fixed_factor_clks) +
0543 ARRAY_SIZE(hi3660_crgctrl_divider_clks);
0544 int i;
0545
0546 clk_crgctrl_data = hisi_clk_init(np, nr);
0547 if (!clk_crgctrl_data)
0548 return;
0549
0550 for (i = 0; i < nr; i++)
0551 clk_crgctrl_data->clk_data.clks[i] = ERR_PTR(-EPROBE_DEFER);
0552
0553 hisi_clk_register_fixed_rate(hi3660_fixed_rate_clks,
0554 ARRAY_SIZE(hi3660_fixed_rate_clks),
0555 clk_crgctrl_data);
0556 }
0557 CLK_OF_DECLARE_DRIVER(hi3660_clk_crgctrl, "hisilicon,hi3660-crgctrl",
0558 hi3660_clk_crgctrl_early_init);
0559
0560 static void hi3660_clk_crgctrl_init(struct device_node *np)
0561 {
0562 struct clk **clks;
0563 int i;
0564
0565 if (!clk_crgctrl_data)
0566 hi3660_clk_crgctrl_early_init(np);
0567
0568
0569 if (!clk_crgctrl_data)
0570 return;
0571
0572 hisi_clk_register_gate_sep(hi3660_crgctrl_gate_sep_clks,
0573 ARRAY_SIZE(hi3660_crgctrl_gate_sep_clks),
0574 clk_crgctrl_data);
0575 hisi_clk_register_gate(hi3660_crgctrl_gate_clks,
0576 ARRAY_SIZE(hi3660_crgctrl_gate_clks),
0577 clk_crgctrl_data);
0578 hisi_clk_register_mux(hi3660_crgctrl_mux_clks,
0579 ARRAY_SIZE(hi3660_crgctrl_mux_clks),
0580 clk_crgctrl_data);
0581 hisi_clk_register_fixed_factor(hi3660_crg_fixed_factor_clks,
0582 ARRAY_SIZE(hi3660_crg_fixed_factor_clks),
0583 clk_crgctrl_data);
0584 hisi_clk_register_divider(hi3660_crgctrl_divider_clks,
0585 ARRAY_SIZE(hi3660_crgctrl_divider_clks),
0586 clk_crgctrl_data);
0587
0588 clks = clk_crgctrl_data->clk_data.clks;
0589 for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) {
0590 if (IS_ERR(clks[i]) && PTR_ERR(clks[i]) != -EPROBE_DEFER)
0591 pr_err("Failed to register crgctrl clock[%d] err=%ld\n",
0592 i, PTR_ERR(clks[i]));
0593 }
0594 }
0595
0596 static const struct of_device_id hi3660_clk_match_table[] = {
0597 { .compatible = "hisilicon,hi3660-crgctrl",
0598 .data = hi3660_clk_crgctrl_init },
0599 { .compatible = "hisilicon,hi3660-pctrl",
0600 .data = hi3660_clk_pctrl_init },
0601 { .compatible = "hisilicon,hi3660-pmuctrl",
0602 .data = hi3660_clk_pmuctrl_init },
0603 { .compatible = "hisilicon,hi3660-sctrl",
0604 .data = hi3660_clk_sctrl_init },
0605 { .compatible = "hisilicon,hi3660-iomcu",
0606 .data = hi3660_clk_iomcu_init },
0607 { }
0608 };
0609
0610 static int hi3660_clk_probe(struct platform_device *pdev)
0611 {
0612 struct device *dev = &pdev->dev;
0613 struct device_node *np = pdev->dev.of_node;
0614 void (*init_func)(struct device_node *np);
0615
0616 init_func = of_device_get_match_data(dev);
0617 if (!init_func)
0618 return -ENODEV;
0619
0620 init_func(np);
0621
0622 return 0;
0623 }
0624
0625 static struct platform_driver hi3660_clk_driver = {
0626 .probe = hi3660_clk_probe,
0627 .driver = {
0628 .name = "hi3660-clk",
0629 .of_match_table = hi3660_clk_match_table,
0630 },
0631 };
0632
0633 static int __init hi3660_clk_init(void)
0634 {
0635 return platform_driver_register(&hi3660_clk_driver);
0636 }
0637 core_initcall(hi3660_clk_init);
