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0010 #include <linux/clk-provider.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/slab.h>
0015
0016 #include <dt-bindings/clock/hi3559av100-clock.h>
0017
0018 #include "clk.h"
0019 #include "crg.h"
0020 #include "reset.h"
0021
0022 #define CRG_BASE_ADDR 0x18020000
0023 #define PLL_MASK_WIDTH 24
0024
0025 struct hi3559av100_pll_clock {
0026 u32 id;
0027 const char *name;
0028 const char *parent_name;
0029 const u32 ctrl_reg1;
0030 const u8 frac_shift;
0031 const u8 frac_width;
0032 const u8 postdiv1_shift;
0033 const u8 postdiv1_width;
0034 const u8 postdiv2_shift;
0035 const u8 postdiv2_width;
0036 const u32 ctrl_reg2;
0037 const u8 fbdiv_shift;
0038 const u8 fbdiv_width;
0039 const u8 refdiv_shift;
0040 const u8 refdiv_width;
0041 };
0042
0043 struct hi3559av100_clk_pll {
0044 struct clk_hw hw;
0045 u32 id;
0046 void __iomem *ctrl_reg1;
0047 u8 frac_shift;
0048 u8 frac_width;
0049 u8 postdiv1_shift;
0050 u8 postdiv1_width;
0051 u8 postdiv2_shift;
0052 u8 postdiv2_width;
0053 void __iomem *ctrl_reg2;
0054 u8 fbdiv_shift;
0055 u8 fbdiv_width;
0056 u8 refdiv_shift;
0057 u8 refdiv_width;
0058 };
0059
0060
0061 static const struct hisi_fixed_rate_clock hi3559av100_fixed_rate_clks_crg[] = {
0062 { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
0063 { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
0064 { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
0065 { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
0066 { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
0067 { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
0068 { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
0069 { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
0070 { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
0071 { HI3559AV100_FIXED_600M, "600m", NULL, 0, 600000000, },
0072 { HI3559AV100_FIXED_568M, "568m", NULL, 0, 568000000, },
0073 { HI3559AV100_FIXED_500M, "500m", NULL, 0, 500000000, },
0074 { HI3559AV100_FIXED_475M, "475m", NULL, 0, 475000000, },
0075 { HI3559AV100_FIXED_428M, "428m", NULL, 0, 428000000, },
0076 { HI3559AV100_FIXED_400M, "400m", NULL, 0, 400000000, },
0077 { HI3559AV100_FIXED_396M, "396m", NULL, 0, 396000000, },
0078 { HI3559AV100_FIXED_300M, "300m", NULL, 0, 300000000, },
0079 { HI3559AV100_FIXED_250M, "250m", NULL, 0, 250000000, },
0080 { HI3559AV100_FIXED_200M, "200m", NULL, 0, 200000000, },
0081 { HI3559AV100_FIXED_198M, "198m", NULL, 0, 198000000, },
0082 { HI3559AV100_FIXED_187p5M, "187p5m", NULL, 0, 187500000, },
0083 { HI3559AV100_FIXED_150M, "150m", NULL, 0, 150000000, },
0084 { HI3559AV100_FIXED_148p5M, "148p5m", NULL, 0, 1485000000, },
0085 { HI3559AV100_FIXED_125M, "125m", NULL, 0, 125000000, },
0086 { HI3559AV100_FIXED_107M, "107m", NULL, 0, 107000000, },
0087 { HI3559AV100_FIXED_100M, "100m", NULL, 0, 100000000, },
0088 { HI3559AV100_FIXED_99M, "99m", NULL, 0, 99000000, },
0089 { HI3559AV100_FIXED_75M, "75m", NULL, 0, 75000000, },
0090 { HI3559AV100_FIXED_74p25M, "74p25m", NULL, 0, 74250000, },
0091 { HI3559AV100_FIXED_72M, "72m", NULL, 0, 72000000, },
0092 { HI3559AV100_FIXED_60M, "60m", NULL, 0, 60000000, },
0093 { HI3559AV100_FIXED_54M, "54m", NULL, 0, 54000000, },
0094 { HI3559AV100_FIXED_50M, "50m", NULL, 0, 50000000, },
0095 { HI3559AV100_FIXED_49p5M, "49p5m", NULL, 0, 49500000, },
0096 { HI3559AV100_FIXED_37p125M, "37p125m", NULL, 0, 37125000, },
0097 { HI3559AV100_FIXED_36M, "36m", NULL, 0, 36000000, },
0098 { HI3559AV100_FIXED_32p4M, "32p4m", NULL, 0, 32400000, },
0099 { HI3559AV100_FIXED_27M, "27m", NULL, 0, 27000000, },
0100 { HI3559AV100_FIXED_25M, "25m", NULL, 0, 25000000, },
0101 { HI3559AV100_FIXED_24M, "24m", NULL, 0, 24000000, },
0102 { HI3559AV100_FIXED_12M, "12m", NULL, 0, 12000000, },
0103 { HI3559AV100_FIXED_3M, "3m", NULL, 0, 3000000, },
0104 { HI3559AV100_FIXED_1p6M, "1p6m", NULL, 0, 1600000, },
0105 { HI3559AV100_FIXED_400K, "400k", NULL, 0, 400000, },
0106 { HI3559AV100_FIXED_100K, "100k", NULL, 0, 100000, },
0107 };
0108
0109
0110 static const char *fmc_mux_p[] = {
0111 "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m"
0112 };
0113
0114 static const char *mmc_mux_p[] = {
0115 "100k", "25m", "49p5m", "99m", "187p5m", "150m", "198m", "400k"
0116 };
0117
0118 static const char *sysapb_mux_p[] = {
0119 "24m", "50m",
0120 };
0121
0122 static const char *sysbus_mux_p[] = {
0123 "24m", "300m"
0124 };
0125
0126 static const char *uart_mux_p[] = { "50m", "24m", "3m" };
0127
0128 static const char *a73_clksel_mux_p[] = {
0129 "24m", "apll", "1000m"
0130 };
0131
0132 static const u32 fmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
0133 static const u32 mmc_mux_table[] = { 0, 1, 2, 3, 4, 5, 6, 7 };
0134 static const u32 sysapb_mux_table[] = { 0, 1 };
0135 static const u32 sysbus_mux_table[] = { 0, 1 };
0136 static const u32 uart_mux_table[] = { 0, 1, 2 };
0137 static const u32 a73_clksel_mux_table[] = { 0, 1, 2 };
0138
0139 static struct hisi_mux_clock hi3559av100_mux_clks_crg[] = {
0140 {
0141 HI3559AV100_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
0142 CLK_SET_RATE_PARENT, 0x170, 2, 3, 0, fmc_mux_table,
0143 },
0144 {
0145 HI3559AV100_MMC0_MUX, "mmc0_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
0146 CLK_SET_RATE_PARENT, 0x1a8, 24, 3, 0, mmc_mux_table,
0147 },
0148 {
0149 HI3559AV100_MMC1_MUX, "mmc1_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
0150 CLK_SET_RATE_PARENT, 0x1ec, 24, 3, 0, mmc_mux_table,
0151 },
0152
0153 {
0154 HI3559AV100_MMC2_MUX, "mmc2_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
0155 CLK_SET_RATE_PARENT, 0x214, 24, 3, 0, mmc_mux_table,
0156 },
0157
0158 {
0159 HI3559AV100_MMC3_MUX, "mmc3_mux", mmc_mux_p, ARRAY_SIZE(mmc_mux_p),
0160 CLK_SET_RATE_PARENT, 0x23c, 24, 3, 0, mmc_mux_table,
0161 },
0162
0163 {
0164 HI3559AV100_SYSAPB_MUX, "sysapb_mux", sysapb_mux_p, ARRAY_SIZE(sysapb_mux_p),
0165 CLK_SET_RATE_PARENT, 0xe8, 3, 1, 0, sysapb_mux_table
0166 },
0167
0168 {
0169 HI3559AV100_SYSBUS_MUX, "sysbus_mux", sysbus_mux_p, ARRAY_SIZE(sysbus_mux_p),
0170 CLK_SET_RATE_PARENT, 0xe8, 0, 1, 0, sysbus_mux_table
0171 },
0172
0173 {
0174 HI3559AV100_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
0175 CLK_SET_RATE_PARENT, 0x198, 28, 2, 0, uart_mux_table
0176 },
0177
0178 {
0179 HI3559AV100_A73_MUX, "a73_mux", a73_clksel_mux_p, ARRAY_SIZE(a73_clksel_mux_p),
0180 CLK_SET_RATE_PARENT, 0xe4, 0, 2, 0, a73_clksel_mux_table
0181 },
0182 };
0183
0184 static struct hisi_gate_clock hi3559av100_gate_clks[] = {
0185 {
0186 HI3559AV100_FMC_CLK, "clk_fmc", "fmc_mux",
0187 CLK_SET_RATE_PARENT, 0x170, 1, 0,
0188 },
0189 {
0190 HI3559AV100_MMC0_CLK, "clk_mmc0", "mmc0_mux",
0191 CLK_SET_RATE_PARENT, 0x1a8, 28, 0,
0192 },
0193 {
0194 HI3559AV100_MMC1_CLK, "clk_mmc1", "mmc1_mux",
0195 CLK_SET_RATE_PARENT, 0x1ec, 28, 0,
0196 },
0197 {
0198 HI3559AV100_MMC2_CLK, "clk_mmc2", "mmc2_mux",
0199 CLK_SET_RATE_PARENT, 0x214, 28, 0,
0200 },
0201 {
0202 HI3559AV100_MMC3_CLK, "clk_mmc3", "mmc3_mux",
0203 CLK_SET_RATE_PARENT, 0x23c, 28, 0,
0204 },
0205 {
0206 HI3559AV100_UART0_CLK, "clk_uart0", "uart_mux",
0207 CLK_SET_RATE_PARENT, 0x198, 23, 0,
0208 },
0209 {
0210 HI3559AV100_UART1_CLK, "clk_uart1", "uart_mux",
0211 CLK_SET_RATE_PARENT, 0x198, 24, 0,
0212 },
0213 {
0214 HI3559AV100_UART2_CLK, "clk_uart2", "uart_mux",
0215 CLK_SET_RATE_PARENT, 0x198, 25, 0,
0216 },
0217 {
0218 HI3559AV100_UART3_CLK, "clk_uart3", "uart_mux",
0219 CLK_SET_RATE_PARENT, 0x198, 26, 0,
0220 },
0221 {
0222 HI3559AV100_UART4_CLK, "clk_uart4", "uart_mux",
0223 CLK_SET_RATE_PARENT, 0x198, 27, 0,
0224 },
0225 {
0226 HI3559AV100_ETH_CLK, "clk_eth", NULL,
0227 CLK_SET_RATE_PARENT, 0x0174, 1, 0,
0228 },
0229 {
0230 HI3559AV100_ETH_MACIF_CLK, "clk_eth_macif", NULL,
0231 CLK_SET_RATE_PARENT, 0x0174, 5, 0,
0232 },
0233 {
0234 HI3559AV100_ETH1_CLK, "clk_eth1", NULL,
0235 CLK_SET_RATE_PARENT, 0x0174, 3, 0,
0236 },
0237 {
0238 HI3559AV100_ETH1_MACIF_CLK, "clk_eth1_macif", NULL,
0239 CLK_SET_RATE_PARENT, 0x0174, 7, 0,
0240 },
0241 {
0242 HI3559AV100_I2C0_CLK, "clk_i2c0", "50m",
0243 CLK_SET_RATE_PARENT, 0x01a0, 16, 0,
0244 },
0245 {
0246 HI3559AV100_I2C1_CLK, "clk_i2c1", "50m",
0247 CLK_SET_RATE_PARENT, 0x01a0, 17, 0,
0248 },
0249 {
0250 HI3559AV100_I2C2_CLK, "clk_i2c2", "50m",
0251 CLK_SET_RATE_PARENT, 0x01a0, 18, 0,
0252 },
0253 {
0254 HI3559AV100_I2C3_CLK, "clk_i2c3", "50m",
0255 CLK_SET_RATE_PARENT, 0x01a0, 19, 0,
0256 },
0257 {
0258 HI3559AV100_I2C4_CLK, "clk_i2c4", "50m",
0259 CLK_SET_RATE_PARENT, 0x01a0, 20, 0,
0260 },
0261 {
0262 HI3559AV100_I2C5_CLK, "clk_i2c5", "50m",
0263 CLK_SET_RATE_PARENT, 0x01a0, 21, 0,
0264 },
0265 {
0266 HI3559AV100_I2C6_CLK, "clk_i2c6", "50m",
0267 CLK_SET_RATE_PARENT, 0x01a0, 22, 0,
0268 },
0269 {
0270 HI3559AV100_I2C7_CLK, "clk_i2c7", "50m",
0271 CLK_SET_RATE_PARENT, 0x01a0, 23, 0,
0272 },
0273 {
0274 HI3559AV100_I2C8_CLK, "clk_i2c8", "50m",
0275 CLK_SET_RATE_PARENT, 0x01a0, 24, 0,
0276 },
0277 {
0278 HI3559AV100_I2C9_CLK, "clk_i2c9", "50m",
0279 CLK_SET_RATE_PARENT, 0x01a0, 25, 0,
0280 },
0281 {
0282 HI3559AV100_I2C10_CLK, "clk_i2c10", "50m",
0283 CLK_SET_RATE_PARENT, 0x01a0, 26, 0,
0284 },
0285 {
0286 HI3559AV100_I2C11_CLK, "clk_i2c11", "50m",
0287 CLK_SET_RATE_PARENT, 0x01a0, 27, 0,
0288 },
0289 {
0290 HI3559AV100_SPI0_CLK, "clk_spi0", "100m",
0291 CLK_SET_RATE_PARENT, 0x0198, 16, 0,
0292 },
0293 {
0294 HI3559AV100_SPI1_CLK, "clk_spi1", "100m",
0295 CLK_SET_RATE_PARENT, 0x0198, 17, 0,
0296 },
0297 {
0298 HI3559AV100_SPI2_CLK, "clk_spi2", "100m",
0299 CLK_SET_RATE_PARENT, 0x0198, 18, 0,
0300 },
0301 {
0302 HI3559AV100_SPI3_CLK, "clk_spi3", "100m",
0303 CLK_SET_RATE_PARENT, 0x0198, 19, 0,
0304 },
0305 {
0306 HI3559AV100_SPI4_CLK, "clk_spi4", "100m",
0307 CLK_SET_RATE_PARENT, 0x0198, 20, 0,
0308 },
0309 {
0310 HI3559AV100_SPI5_CLK, "clk_spi5", "100m",
0311 CLK_SET_RATE_PARENT, 0x0198, 21, 0,
0312 },
0313 {
0314 HI3559AV100_SPI6_CLK, "clk_spi6", "100m",
0315 CLK_SET_RATE_PARENT, 0x0198, 22, 0,
0316 },
0317 {
0318 HI3559AV100_EDMAC_AXICLK, "axi_clk_edmac", NULL,
0319 CLK_SET_RATE_PARENT, 0x16c, 6, 0,
0320 },
0321 {
0322 HI3559AV100_EDMAC_CLK, "clk_edmac", NULL,
0323 CLK_SET_RATE_PARENT, 0x16c, 5, 0,
0324 },
0325 {
0326 HI3559AV100_EDMAC1_AXICLK, "axi_clk_edmac1", NULL,
0327 CLK_SET_RATE_PARENT, 0x16c, 9, 0,
0328 },
0329 {
0330 HI3559AV100_EDMAC1_CLK, "clk_edmac1", NULL,
0331 CLK_SET_RATE_PARENT, 0x16c, 8, 0,
0332 },
0333 {
0334 HI3559AV100_VDMAC_CLK, "clk_vdmac", NULL,
0335 CLK_SET_RATE_PARENT, 0x14c, 5, 0,
0336 },
0337 };
0338
0339 static struct hi3559av100_pll_clock hi3559av100_pll_clks[] = {
0340 {
0341 HI3559AV100_APLL_CLK, "apll", NULL, 0x0, 0, 24, 24, 3, 28, 3,
0342 0x4, 0, 12, 12, 6
0343 },
0344 {
0345 HI3559AV100_GPLL_CLK, "gpll", NULL, 0x20, 0, 24, 24, 3, 28, 3,
0346 0x24, 0, 12, 12, 6
0347 },
0348 };
0349
0350 #define to_pll_clk(_hw) container_of(_hw, struct hi3559av100_clk_pll, hw)
0351 static void hi3559av100_calc_pll(u32 *frac_val, u32 *postdiv1_val,
0352 u32 *postdiv2_val,
0353 u32 *fbdiv_val, u32 *refdiv_val, u64 rate)
0354 {
0355 u64 rem;
0356
0357 *postdiv1_val = 2;
0358 *postdiv2_val = 1;
0359
0360 rate = rate * ((*postdiv1_val) * (*postdiv2_val));
0361
0362 *frac_val = 0;
0363 rem = do_div(rate, 1000000);
0364 rem = do_div(rate, PLL_MASK_WIDTH);
0365 *fbdiv_val = rate;
0366 *refdiv_val = 1;
0367 rem = rem * (1 << PLL_MASK_WIDTH);
0368 do_div(rem, PLL_MASK_WIDTH);
0369 *frac_val = rem;
0370 }
0371
0372 static int clk_pll_set_rate(struct clk_hw *hw,
0373 unsigned long rate,
0374 unsigned long parent_rate)
0375 {
0376 struct hi3559av100_clk_pll *clk = to_pll_clk(hw);
0377 u32 frac_val, postdiv1_val, postdiv2_val, fbdiv_val, refdiv_val;
0378 u32 val;
0379
0380 postdiv1_val = postdiv2_val = 0;
0381
0382 hi3559av100_calc_pll(&frac_val, &postdiv1_val, &postdiv2_val,
0383 &fbdiv_val, &refdiv_val, (u64)rate);
0384
0385 val = readl_relaxed(clk->ctrl_reg1);
0386 val &= ~(((1 << clk->frac_width) - 1) << clk->frac_shift);
0387 val &= ~(((1 << clk->postdiv1_width) - 1) << clk->postdiv1_shift);
0388 val &= ~(((1 << clk->postdiv2_width) - 1) << clk->postdiv2_shift);
0389
0390 val |= frac_val << clk->frac_shift;
0391 val |= postdiv1_val << clk->postdiv1_shift;
0392 val |= postdiv2_val << clk->postdiv2_shift;
0393 writel_relaxed(val, clk->ctrl_reg1);
0394
0395 val = readl_relaxed(clk->ctrl_reg2);
0396 val &= ~(((1 << clk->fbdiv_width) - 1) << clk->fbdiv_shift);
0397 val &= ~(((1 << clk->refdiv_width) - 1) << clk->refdiv_shift);
0398
0399 val |= fbdiv_val << clk->fbdiv_shift;
0400 val |= refdiv_val << clk->refdiv_shift;
0401 writel_relaxed(val, clk->ctrl_reg2);
0402
0403 return 0;
0404 }
0405
0406 static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
0407 unsigned long parent_rate)
0408 {
0409 struct hi3559av100_clk_pll *clk = to_pll_clk(hw);
0410 u64 frac_val, fbdiv_val, refdiv_val;
0411 u32 postdiv1_val, postdiv2_val;
0412 u32 val;
0413 u64 tmp, rate;
0414
0415 val = readl_relaxed(clk->ctrl_reg1);
0416 val = val >> clk->frac_shift;
0417 val &= ((1 << clk->frac_width) - 1);
0418 frac_val = val;
0419
0420 val = readl_relaxed(clk->ctrl_reg1);
0421 val = val >> clk->postdiv1_shift;
0422 val &= ((1 << clk->postdiv1_width) - 1);
0423 postdiv1_val = val;
0424
0425 val = readl_relaxed(clk->ctrl_reg1);
0426 val = val >> clk->postdiv2_shift;
0427 val &= ((1 << clk->postdiv2_width) - 1);
0428 postdiv2_val = val;
0429
0430 val = readl_relaxed(clk->ctrl_reg2);
0431 val = val >> clk->fbdiv_shift;
0432 val &= ((1 << clk->fbdiv_width) - 1);
0433 fbdiv_val = val;
0434
0435 val = readl_relaxed(clk->ctrl_reg2);
0436 val = val >> clk->refdiv_shift;
0437 val &= ((1 << clk->refdiv_width) - 1);
0438 refdiv_val = val;
0439
0440
0441 rate = 0;
0442 tmp = 24000000 * fbdiv_val + (24000000 * frac_val) / (1 << 24);
0443 rate += tmp;
0444 do_div(rate, refdiv_val);
0445 do_div(rate, postdiv1_val * postdiv2_val);
0446
0447 return rate;
0448 }
0449
0450 static const struct clk_ops hisi_clk_pll_ops = {
0451 .set_rate = clk_pll_set_rate,
0452 .recalc_rate = clk_pll_recalc_rate,
0453 };
0454
0455 static void hisi_clk_register_pll(struct hi3559av100_pll_clock *clks,
0456 int nums, struct hisi_clock_data *data, struct device *dev)
0457 {
0458 void __iomem *base = data->base;
0459 struct hi3559av100_clk_pll *p_clk = NULL;
0460 struct clk *clk = NULL;
0461 struct clk_init_data init;
0462 int i;
0463
0464 p_clk = devm_kzalloc(dev, sizeof(*p_clk) * nums, GFP_KERNEL);
0465
0466 if (!p_clk)
0467 return;
0468
0469 for (i = 0; i < nums; i++) {
0470 init.name = clks[i].name;
0471 init.flags = 0;
0472 init.parent_names =
0473 (clks[i].parent_name ? &clks[i].parent_name : NULL);
0474 init.num_parents = (clks[i].parent_name ? 1 : 0);
0475 init.ops = &hisi_clk_pll_ops;
0476
0477 p_clk->ctrl_reg1 = base + clks[i].ctrl_reg1;
0478 p_clk->frac_shift = clks[i].frac_shift;
0479 p_clk->frac_width = clks[i].frac_width;
0480 p_clk->postdiv1_shift = clks[i].postdiv1_shift;
0481 p_clk->postdiv1_width = clks[i].postdiv1_width;
0482 p_clk->postdiv2_shift = clks[i].postdiv2_shift;
0483 p_clk->postdiv2_width = clks[i].postdiv2_width;
0484
0485 p_clk->ctrl_reg2 = base + clks[i].ctrl_reg2;
0486 p_clk->fbdiv_shift = clks[i].fbdiv_shift;
0487 p_clk->fbdiv_width = clks[i].fbdiv_width;
0488 p_clk->refdiv_shift = clks[i].refdiv_shift;
0489 p_clk->refdiv_width = clks[i].refdiv_width;
0490 p_clk->hw.init = &init;
0491
0492 clk = clk_register(NULL, &p_clk->hw);
0493 if (IS_ERR(clk)) {
0494 devm_kfree(dev, p_clk);
0495 dev_err(dev, "%s: failed to register clock %s\n",
0496 __func__, clks[i].name);
0497 continue;
0498 }
0499
0500 data->clk_data.clks[clks[i].id] = clk;
0501 p_clk++;
0502 }
0503 }
0504
0505 static struct hisi_clock_data *hi3559av100_clk_register(
0506 struct platform_device *pdev)
0507 {
0508 struct hisi_clock_data *clk_data;
0509 int ret;
0510
0511 clk_data = hisi_clk_alloc(pdev, HI3559AV100_CRG_NR_CLKS);
0512 if (!clk_data)
0513 return ERR_PTR(-ENOMEM);
0514
0515 ret = hisi_clk_register_fixed_rate(hi3559av100_fixed_rate_clks_crg,
0516 ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
0517 if (ret)
0518 return ERR_PTR(ret);
0519
0520 hisi_clk_register_pll(hi3559av100_pll_clks,
0521 ARRAY_SIZE(hi3559av100_pll_clks), clk_data, &pdev->dev);
0522
0523 ret = hisi_clk_register_mux(hi3559av100_mux_clks_crg,
0524 ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
0525 if (ret)
0526 goto unregister_fixed_rate;
0527
0528 ret = hisi_clk_register_gate(hi3559av100_gate_clks,
0529 ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
0530 if (ret)
0531 goto unregister_mux;
0532
0533 ret = of_clk_add_provider(pdev->dev.of_node,
0534 of_clk_src_onecell_get, &clk_data->clk_data);
0535 if (ret)
0536 goto unregister_gate;
0537
0538 return clk_data;
0539
0540 unregister_gate:
0541 hisi_clk_unregister_gate(hi3559av100_gate_clks,
0542 ARRAY_SIZE(hi3559av100_gate_clks), clk_data);
0543 unregister_mux:
0544 hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
0545 ARRAY_SIZE(hi3559av100_mux_clks_crg), clk_data);
0546 unregister_fixed_rate:
0547 hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
0548 ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), clk_data);
0549 return ERR_PTR(ret);
0550 }
0551
0552 static void hi3559av100_clk_unregister(struct platform_device *pdev)
0553 {
0554 struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
0555
0556 of_clk_del_provider(pdev->dev.of_node);
0557
0558 hisi_clk_unregister_gate(hi3559av100_gate_clks,
0559 ARRAY_SIZE(hi3559av100_gate_clks), crg->clk_data);
0560 hisi_clk_unregister_mux(hi3559av100_mux_clks_crg,
0561 ARRAY_SIZE(hi3559av100_mux_clks_crg), crg->clk_data);
0562 hisi_clk_unregister_fixed_rate(hi3559av100_fixed_rate_clks_crg,
0563 ARRAY_SIZE(hi3559av100_fixed_rate_clks_crg), crg->clk_data);
0564 }
0565
0566 static const struct hisi_crg_funcs hi3559av100_crg_funcs = {
0567 .register_clks = hi3559av100_clk_register,
0568 .unregister_clks = hi3559av100_clk_unregister,
0569 };
0570
0571 static struct hisi_fixed_rate_clock hi3559av100_shub_fixed_rate_clks[] = {
0572 { HI3559AV100_SHUB_SOURCE_SOC_24M, "clk_source_24M", NULL, 0, 24000000UL, },
0573 { HI3559AV100_SHUB_SOURCE_SOC_200M, "clk_source_200M", NULL, 0, 200000000UL, },
0574 { HI3559AV100_SHUB_SOURCE_SOC_300M, "clk_source_300M", NULL, 0, 300000000UL, },
0575 { HI3559AV100_SHUB_SOURCE_PLL, "clk_source_PLL", NULL, 0, 192000000UL, },
0576 { HI3559AV100_SHUB_I2C0_CLK, "clk_shub_i2c0", NULL, 0, 48000000UL, },
0577 { HI3559AV100_SHUB_I2C1_CLK, "clk_shub_i2c1", NULL, 0, 48000000UL, },
0578 { HI3559AV100_SHUB_I2C2_CLK, "clk_shub_i2c2", NULL, 0, 48000000UL, },
0579 { HI3559AV100_SHUB_I2C3_CLK, "clk_shub_i2c3", NULL, 0, 48000000UL, },
0580 { HI3559AV100_SHUB_I2C4_CLK, "clk_shub_i2c4", NULL, 0, 48000000UL, },
0581 { HI3559AV100_SHUB_I2C5_CLK, "clk_shub_i2c5", NULL, 0, 48000000UL, },
0582 { HI3559AV100_SHUB_I2C6_CLK, "clk_shub_i2c6", NULL, 0, 48000000UL, },
0583 { HI3559AV100_SHUB_I2C7_CLK, "clk_shub_i2c7", NULL, 0, 48000000UL, },
0584 { HI3559AV100_SHUB_UART_CLK_32K, "clk_uart_32K", NULL, 0, 32000UL, },
0585 };
0586
0587
0588 static u32 shub_source_clk_mux_table[] = {0, 1, 2, 3};
0589 static const char *shub_source_clk_mux_p[] = {
0590 "clk_source_24M", "clk_source_200M", "clk_source_300M", "clk_source_PLL"
0591 };
0592
0593 static u32 shub_uart_source_clk_mux_table[] = {0, 1, 2, 3};
0594 static const char *shub_uart_source_clk_mux_p[] = {
0595 "clk_uart_32K", "clk_uart_div_clk", "clk_uart_div_clk", "clk_source_24M"
0596 };
0597
0598 static struct hisi_mux_clock hi3559av100_shub_mux_clks[] = {
0599 {
0600 HI3559AV100_SHUB_SOURCE_CLK, "shub_clk", shub_source_clk_mux_p,
0601 ARRAY_SIZE(shub_source_clk_mux_p),
0602 0, 0x0, 0, 2, 0, shub_source_clk_mux_table,
0603 },
0604
0605 {
0606 HI3559AV100_SHUB_UART_SOURCE_CLK, "shub_uart_source_clk",
0607 shub_uart_source_clk_mux_p, ARRAY_SIZE(shub_uart_source_clk_mux_p),
0608 0, 0x1c, 28, 2, 0, shub_uart_source_clk_mux_table,
0609 },
0610 };
0611
0612
0613
0614 static struct clk_div_table shub_spi_clk_table[] = {{0, 8}, {1, 4}, {2, 2}, {}};
0615 static struct clk_div_table shub_uart_div_clk_table[] = {{1, 8}, {2, 4}, {}};
0616
0617 static struct hisi_divider_clock hi3559av100_shub_div_clks[] = {
0618 { HI3559AV100_SHUB_SPI_SOURCE_CLK, "clk_spi_clk", "shub_clk", 0, 0x20, 24, 2,
0619 CLK_DIVIDER_ALLOW_ZERO, shub_spi_clk_table,
0620 },
0621 { HI3559AV100_SHUB_UART_DIV_CLK, "clk_uart_div_clk", "shub_clk", 0, 0x1c, 28, 2,
0622 CLK_DIVIDER_ALLOW_ZERO, shub_uart_div_clk_table,
0623 },
0624 };
0625
0626
0627 static struct hisi_gate_clock hi3559av100_shub_gate_clks[] = {
0628 {
0629 HI3559AV100_SHUB_SPI0_CLK, "clk_shub_spi0", "clk_spi_clk",
0630 0, 0x20, 1, 0,
0631 },
0632 {
0633 HI3559AV100_SHUB_SPI1_CLK, "clk_shub_spi1", "clk_spi_clk",
0634 0, 0x20, 5, 0,
0635 },
0636 {
0637 HI3559AV100_SHUB_SPI2_CLK, "clk_shub_spi2", "clk_spi_clk",
0638 0, 0x20, 9, 0,
0639 },
0640
0641 {
0642 HI3559AV100_SHUB_UART0_CLK, "clk_shub_uart0", "shub_uart_source_clk",
0643 0, 0x1c, 1, 0,
0644 },
0645 {
0646 HI3559AV100_SHUB_UART1_CLK, "clk_shub_uart1", "shub_uart_source_clk",
0647 0, 0x1c, 5, 0,
0648 },
0649 {
0650 HI3559AV100_SHUB_UART2_CLK, "clk_shub_uart2", "shub_uart_source_clk",
0651 0, 0x1c, 9, 0,
0652 },
0653 {
0654 HI3559AV100_SHUB_UART3_CLK, "clk_shub_uart3", "shub_uart_source_clk",
0655 0, 0x1c, 13, 0,
0656 },
0657 {
0658 HI3559AV100_SHUB_UART4_CLK, "clk_shub_uart4", "shub_uart_source_clk",
0659 0, 0x1c, 17, 0,
0660 },
0661 {
0662 HI3559AV100_SHUB_UART5_CLK, "clk_shub_uart5", "shub_uart_source_clk",
0663 0, 0x1c, 21, 0,
0664 },
0665 {
0666 HI3559AV100_SHUB_UART6_CLK, "clk_shub_uart6", "shub_uart_source_clk",
0667 0, 0x1c, 25, 0,
0668 },
0669
0670 {
0671 HI3559AV100_SHUB_EDMAC_CLK, "clk_shub_dmac", "shub_clk",
0672 0, 0x24, 4, 0,
0673 },
0674 };
0675
0676 static int hi3559av100_shub_default_clk_set(void)
0677 {
0678 void __iomem *crg_base;
0679 unsigned int val;
0680
0681 crg_base = ioremap(CRG_BASE_ADDR, SZ_4K);
0682
0683
0684 val = readl_relaxed(crg_base + 0x20);
0685 val |= (0x2 << 24);
0686 writel_relaxed(val, crg_base + 0x20);
0687
0688
0689 val = readl_relaxed(crg_base + 0x1C);
0690 val |= (0x1 << 28);
0691 writel_relaxed(val, crg_base + 0x1C);
0692
0693 iounmap(crg_base);
0694 crg_base = NULL;
0695
0696 return 0;
0697 }
0698
0699 static struct hisi_clock_data *hi3559av100_shub_clk_register(
0700 struct platform_device *pdev)
0701 {
0702 struct hisi_clock_data *clk_data = NULL;
0703 int ret;
0704
0705 hi3559av100_shub_default_clk_set();
0706
0707 clk_data = hisi_clk_alloc(pdev, HI3559AV100_SHUB_NR_CLKS);
0708 if (!clk_data)
0709 return ERR_PTR(-ENOMEM);
0710
0711 ret = hisi_clk_register_fixed_rate(hi3559av100_shub_fixed_rate_clks,
0712 ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
0713 if (ret)
0714 return ERR_PTR(ret);
0715
0716 ret = hisi_clk_register_mux(hi3559av100_shub_mux_clks,
0717 ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
0718 if (ret)
0719 goto unregister_fixed_rate;
0720
0721 ret = hisi_clk_register_divider(hi3559av100_shub_div_clks,
0722 ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
0723 if (ret)
0724 goto unregister_mux;
0725
0726 ret = hisi_clk_register_gate(hi3559av100_shub_gate_clks,
0727 ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
0728 if (ret)
0729 goto unregister_factor;
0730
0731 ret = of_clk_add_provider(pdev->dev.of_node,
0732 of_clk_src_onecell_get, &clk_data->clk_data);
0733 if (ret)
0734 goto unregister_gate;
0735
0736 return clk_data;
0737
0738 unregister_gate:
0739 hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
0740 ARRAY_SIZE(hi3559av100_shub_gate_clks), clk_data);
0741 unregister_factor:
0742 hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
0743 ARRAY_SIZE(hi3559av100_shub_div_clks), clk_data);
0744 unregister_mux:
0745 hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
0746 ARRAY_SIZE(hi3559av100_shub_mux_clks), clk_data);
0747 unregister_fixed_rate:
0748 hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
0749 ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), clk_data);
0750 return ERR_PTR(ret);
0751 }
0752
0753 static void hi3559av100_shub_clk_unregister(struct platform_device *pdev)
0754 {
0755 struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
0756
0757 of_clk_del_provider(pdev->dev.of_node);
0758
0759 hisi_clk_unregister_gate(hi3559av100_shub_gate_clks,
0760 ARRAY_SIZE(hi3559av100_shub_gate_clks), crg->clk_data);
0761 hisi_clk_unregister_divider(hi3559av100_shub_div_clks,
0762 ARRAY_SIZE(hi3559av100_shub_div_clks), crg->clk_data);
0763 hisi_clk_unregister_mux(hi3559av100_shub_mux_clks,
0764 ARRAY_SIZE(hi3559av100_shub_mux_clks), crg->clk_data);
0765 hisi_clk_unregister_fixed_rate(hi3559av100_shub_fixed_rate_clks,
0766 ARRAY_SIZE(hi3559av100_shub_fixed_rate_clks), crg->clk_data);
0767 }
0768
0769 static const struct hisi_crg_funcs hi3559av100_shub_crg_funcs = {
0770 .register_clks = hi3559av100_shub_clk_register,
0771 .unregister_clks = hi3559av100_shub_clk_unregister,
0772 };
0773
0774 static const struct of_device_id hi3559av100_crg_match_table[] = {
0775 {
0776 .compatible = "hisilicon,hi3559av100-clock",
0777 .data = &hi3559av100_crg_funcs
0778 },
0779 {
0780 .compatible = "hisilicon,hi3559av100-shub-clock",
0781 .data = &hi3559av100_shub_crg_funcs
0782 },
0783 { }
0784 };
0785 MODULE_DEVICE_TABLE(of, hi3559av100_crg_match_table);
0786
0787 static int hi3559av100_crg_probe(struct platform_device *pdev)
0788 {
0789 struct hisi_crg_dev *crg;
0790
0791 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
0792 if (!crg)
0793 return -ENOMEM;
0794
0795 crg->funcs = of_device_get_match_data(&pdev->dev);
0796 if (!crg->funcs)
0797 return -ENOENT;
0798
0799 crg->rstc = hisi_reset_init(pdev);
0800 if (!crg->rstc)
0801 return -ENOMEM;
0802
0803 crg->clk_data = crg->funcs->register_clks(pdev);
0804 if (IS_ERR(crg->clk_data)) {
0805 hisi_reset_exit(crg->rstc);
0806 return PTR_ERR(crg->clk_data);
0807 }
0808
0809 platform_set_drvdata(pdev, crg);
0810 return 0;
0811 }
0812
0813 static int hi3559av100_crg_remove(struct platform_device *pdev)
0814 {
0815 struct hisi_crg_dev *crg = platform_get_drvdata(pdev);
0816
0817 hisi_reset_exit(crg->rstc);
0818 crg->funcs->unregister_clks(pdev);
0819 return 0;
0820 }
0821
0822 static struct platform_driver hi3559av100_crg_driver = {
0823 .probe = hi3559av100_crg_probe,
0824 .remove = hi3559av100_crg_remove,
0825 .driver = {
0826 .name = "hi3559av100-clock",
0827 .of_match_table = hi3559av100_crg_match_table,
0828 },
0829 };
0830
0831 static int __init hi3559av100_crg_init(void)
0832 {
0833 return platform_driver_register(&hi3559av100_crg_driver);
0834 }
0835 core_initcall(hi3559av100_crg_init);
0836
0837 static void __exit hi3559av100_crg_exit(void)
0838 {
0839 platform_driver_unregister(&hi3559av100_crg_driver);
0840 }
0841 module_exit(hi3559av100_crg_exit);
0842
0843
0844 MODULE_LICENSE("GPL v2");
0845 MODULE_DESCRIPTION("HiSilicon Hi3559AV100 CRG Driver");
