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0008 #include <dt-bindings/clock/hi3519-clock.h>
0009 #include <linux/clk-provider.h>
0010 #include <linux/module.h>
0011 #include <linux/platform_device.h>
0012 #include "clk.h"
0013 #include "reset.h"
0014
0015 #define HI3519_INNER_CLK_OFFSET 64
0016 #define HI3519_FIXED_24M 65
0017 #define HI3519_FIXED_50M 66
0018 #define HI3519_FIXED_75M 67
0019 #define HI3519_FIXED_125M 68
0020 #define HI3519_FIXED_150M 69
0021 #define HI3519_FIXED_200M 70
0022 #define HI3519_FIXED_250M 71
0023 #define HI3519_FIXED_300M 72
0024 #define HI3519_FIXED_400M 73
0025 #define HI3519_FMC_MUX 74
0026
0027 #define HI3519_NR_CLKS 128
0028
0029 struct hi3519_crg_data {
0030 struct hisi_clock_data *clk_data;
0031 struct hisi_reset_controller *rstc;
0032 };
0033
0034 static const struct hisi_fixed_rate_clock hi3519_fixed_rate_clks[] = {
0035 { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
0036 { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
0037 { HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
0038 { HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
0039 { HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
0040 { HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
0041 { HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
0042 { HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
0043 { HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
0044 };
0045
0046 static const char *const fmc_mux_p[] = {
0047 "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
0048 static u32 fmc_mux_table[] = {0, 1, 2, 3, 4, 5, 6, 7};
0049
0050 static const struct hisi_mux_clock hi3519_mux_clks[] = {
0051 { HI3519_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
0052 CLK_SET_RATE_PARENT, 0xc0, 2, 3, 0, fmc_mux_table, },
0053 };
0054
0055 static const struct hisi_gate_clock hi3519_gate_clks[] = {
0056 { HI3519_FMC_CLK, "clk_fmc", "fmc_mux",
0057 CLK_SET_RATE_PARENT, 0xc0, 1, 0, },
0058 { HI3519_UART0_CLK, "clk_uart0", "24m",
0059 CLK_SET_RATE_PARENT, 0xe4, 20, 0, },
0060 { HI3519_UART1_CLK, "clk_uart1", "24m",
0061 CLK_SET_RATE_PARENT, 0xe4, 21, 0, },
0062 { HI3519_UART2_CLK, "clk_uart2", "24m",
0063 CLK_SET_RATE_PARENT, 0xe4, 22, 0, },
0064 { HI3519_UART3_CLK, "clk_uart3", "24m",
0065 CLK_SET_RATE_PARENT, 0xe4, 23, 0, },
0066 { HI3519_UART4_CLK, "clk_uart4", "24m",
0067 CLK_SET_RATE_PARENT, 0xe4, 24, 0, },
0068 { HI3519_SPI0_CLK, "clk_spi0", "50m",
0069 CLK_SET_RATE_PARENT, 0xe4, 16, 0, },
0070 { HI3519_SPI1_CLK, "clk_spi1", "50m",
0071 CLK_SET_RATE_PARENT, 0xe4, 17, 0, },
0072 { HI3519_SPI2_CLK, "clk_spi2", "50m",
0073 CLK_SET_RATE_PARENT, 0xe4, 18, 0, },
0074 };
0075
0076 static struct hisi_clock_data *hi3519_clk_register(struct platform_device *pdev)
0077 {
0078 struct hisi_clock_data *clk_data;
0079 int ret;
0080
0081 clk_data = hisi_clk_alloc(pdev, HI3519_NR_CLKS);
0082 if (!clk_data)
0083 return ERR_PTR(-ENOMEM);
0084
0085 ret = hisi_clk_register_fixed_rate(hi3519_fixed_rate_clks,
0086 ARRAY_SIZE(hi3519_fixed_rate_clks),
0087 clk_data);
0088 if (ret)
0089 return ERR_PTR(ret);
0090
0091 ret = hisi_clk_register_mux(hi3519_mux_clks,
0092 ARRAY_SIZE(hi3519_mux_clks),
0093 clk_data);
0094 if (ret)
0095 goto unregister_fixed_rate;
0096
0097 ret = hisi_clk_register_gate(hi3519_gate_clks,
0098 ARRAY_SIZE(hi3519_gate_clks),
0099 clk_data);
0100 if (ret)
0101 goto unregister_mux;
0102
0103 ret = of_clk_add_provider(pdev->dev.of_node,
0104 of_clk_src_onecell_get, &clk_data->clk_data);
0105 if (ret)
0106 goto unregister_gate;
0107
0108 return clk_data;
0109
0110 unregister_fixed_rate:
0111 hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
0112 ARRAY_SIZE(hi3519_fixed_rate_clks),
0113 clk_data);
0114
0115 unregister_mux:
0116 hisi_clk_unregister_mux(hi3519_mux_clks,
0117 ARRAY_SIZE(hi3519_mux_clks),
0118 clk_data);
0119 unregister_gate:
0120 hisi_clk_unregister_gate(hi3519_gate_clks,
0121 ARRAY_SIZE(hi3519_gate_clks),
0122 clk_data);
0123 return ERR_PTR(ret);
0124 }
0125
0126 static void hi3519_clk_unregister(struct platform_device *pdev)
0127 {
0128 struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
0129
0130 of_clk_del_provider(pdev->dev.of_node);
0131
0132 hisi_clk_unregister_gate(hi3519_gate_clks,
0133 ARRAY_SIZE(hi3519_mux_clks),
0134 crg->clk_data);
0135 hisi_clk_unregister_mux(hi3519_mux_clks,
0136 ARRAY_SIZE(hi3519_mux_clks),
0137 crg->clk_data);
0138 hisi_clk_unregister_fixed_rate(hi3519_fixed_rate_clks,
0139 ARRAY_SIZE(hi3519_fixed_rate_clks),
0140 crg->clk_data);
0141 }
0142
0143 static int hi3519_clk_probe(struct platform_device *pdev)
0144 {
0145 struct hi3519_crg_data *crg;
0146
0147 crg = devm_kmalloc(&pdev->dev, sizeof(*crg), GFP_KERNEL);
0148 if (!crg)
0149 return -ENOMEM;
0150
0151 crg->rstc = hisi_reset_init(pdev);
0152 if (!crg->rstc)
0153 return -ENOMEM;
0154
0155 crg->clk_data = hi3519_clk_register(pdev);
0156 if (IS_ERR(crg->clk_data)) {
0157 hisi_reset_exit(crg->rstc);
0158 return PTR_ERR(crg->clk_data);
0159 }
0160
0161 platform_set_drvdata(pdev, crg);
0162 return 0;
0163 }
0164
0165 static int hi3519_clk_remove(struct platform_device *pdev)
0166 {
0167 struct hi3519_crg_data *crg = platform_get_drvdata(pdev);
0168
0169 hisi_reset_exit(crg->rstc);
0170 hi3519_clk_unregister(pdev);
0171 return 0;
0172 }
0173
0174
0175 static const struct of_device_id hi3519_clk_match_table[] = {
0176 { .compatible = "hisilicon,hi3519-crg" },
0177 { }
0178 };
0179 MODULE_DEVICE_TABLE(of, hi3519_clk_match_table);
0180
0181 static struct platform_driver hi3519_clk_driver = {
0182 .probe = hi3519_clk_probe,
0183 .remove = hi3519_clk_remove,
0184 .driver = {
0185 .name = "hi3519-clk",
0186 .of_match_table = hi3519_clk_match_table,
0187 },
0188 };
0189
0190 static int __init hi3519_clk_init(void)
0191 {
0192 return platform_driver_register(&hi3519_clk_driver);
0193 }
0194 core_initcall(hi3519_clk_init);
0195
0196 static void __exit hi3519_clk_exit(void)
0197 {
0198 platform_driver_unregister(&hi3519_clk_driver);
0199 }
0200 module_exit(hi3519_clk_exit);
0201
0202 MODULE_LICENSE("GPL v2");
0203 MODULE_DESCRIPTION("HiSilicon Hi3519 Clock Driver");
