Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Clock driver for TI Davinci PSC controllers
0004  *
0005  * Copyright (C) 2017 David Lechner <david@lechnology.com>
0006  *
0007  * Based on: drivers/clk/keystone/gate.c
0008  * Copyright (C) 2013 Texas Instruments.
0009  *  Murali Karicheri <m-karicheri2@ti.com>
0010  *  Santosh Shilimkar <santosh.shilimkar@ti.com>
0011  *
0012  * And: arch/arm/mach-davinci/psc.c
0013  * Copyright (C) 2006 Texas Instruments.
0014  */
0015 
0016 #include <linux/clk-provider.h>
0017 #include <linux/clk.h>
0018 #include <linux/clk/davinci.h>
0019 #include <linux/clkdev.h>
0020 #include <linux/err.h>
0021 #include <linux/of_address.h>
0022 #include <linux/of_device.h>
0023 #include <linux/of.h>
0024 #include <linux/platform_device.h>
0025 #include <linux/pm_clock.h>
0026 #include <linux/pm_domain.h>
0027 #include <linux/regmap.h>
0028 #include <linux/reset-controller.h>
0029 #include <linux/slab.h>
0030 #include <linux/types.h>
0031 
0032 #include "psc.h"
0033 
0034 /* PSC register offsets */
0035 #define EPCPR           0x070
0036 #define PTCMD           0x120
0037 #define PTSTAT          0x128
0038 #define PDSTAT(n)       (0x200 + 4 * (n))
0039 #define PDCTL(n)        (0x300 + 4 * (n))
0040 #define MDSTAT(n)       (0x800 + 4 * (n))
0041 #define MDCTL(n)        (0xa00 + 4 * (n))
0042 
0043 /* PSC module states */
0044 enum davinci_lpsc_state {
0045     LPSC_STATE_SWRSTDISABLE = 0,
0046     LPSC_STATE_SYNCRST  = 1,
0047     LPSC_STATE_DISABLE  = 2,
0048     LPSC_STATE_ENABLE   = 3,
0049 };
0050 
0051 #define MDSTAT_STATE_MASK   GENMASK(5, 0)
0052 #define MDSTAT_MCKOUT       BIT(12)
0053 #define PDSTAT_STATE_MASK   GENMASK(4, 0)
0054 #define MDCTL_FORCE     BIT(31)
0055 #define MDCTL_LRESET        BIT(8)
0056 #define PDCTL_EPCGOOD       BIT(8)
0057 #define PDCTL_NEXT      BIT(0)
0058 
0059 struct davinci_psc_data {
0060     struct clk_onecell_data clk_data;
0061     struct genpd_onecell_data pm_data;
0062     struct reset_controller_dev rcdev;
0063 };
0064 
0065 /**
0066  * struct davinci_lpsc_clk - LPSC clock structure
0067  * @dev: the device that provides this LPSC or NULL
0068  * @hw: clk_hw for the LPSC
0069  * @pm_domain: power domain for the LPSC
0070  * @genpd_clk: clock reference owned by @pm_domain
0071  * @regmap: PSC MMIO region
0072  * @md: Module domain (LPSC module id)
0073  * @pd: Power domain
0074  * @flags: LPSC_* quirk flags
0075  */
0076 struct davinci_lpsc_clk {
0077     struct device *dev;
0078     struct clk_hw hw;
0079     struct generic_pm_domain pm_domain;
0080     struct clk *genpd_clk;
0081     struct regmap *regmap;
0082     u32 md;
0083     u32 pd;
0084     u32 flags;
0085 };
0086 
0087 #define to_davinci_psc_data(x) container_of(x, struct davinci_psc_data, x)
0088 #define to_davinci_lpsc_clk(x) container_of(x, struct davinci_lpsc_clk, x)
0089 
0090 /**
0091  * best_dev_name - get the "best" device name.
0092  * @dev: the device
0093  *
0094  * Returns the device tree compatible name if the device has a DT node,
0095  * otherwise return the device name. This is mainly needed because clkdev
0096  * lookups are limited to 20 chars for dev_id and when using device tree,
0097  * dev_name(dev) is much longer than that.
0098  */
0099 static inline const char *best_dev_name(struct device *dev)
0100 {
0101     const char *compatible;
0102 
0103     if (!of_property_read_string(dev->of_node, "compatible", &compatible))
0104         return compatible;
0105 
0106     return dev_name(dev);
0107 }
0108 
0109 static void davinci_lpsc_config(struct davinci_lpsc_clk *lpsc,
0110                 enum davinci_lpsc_state next_state)
0111 {
0112     u32 epcpr, pdstat, mdstat, ptstat;
0113 
0114     regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDSTAT_STATE_MASK,
0115               next_state);
0116 
0117     if (lpsc->flags & LPSC_FORCE)
0118         regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_FORCE,
0119                   MDCTL_FORCE);
0120 
0121     regmap_read(lpsc->regmap, PDSTAT(lpsc->pd), &pdstat);
0122     if ((pdstat & PDSTAT_STATE_MASK) == 0) {
0123         regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_NEXT,
0124                   PDCTL_NEXT);
0125 
0126         regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
0127 
0128         regmap_read_poll_timeout(lpsc->regmap, EPCPR, epcpr,
0129                      epcpr & BIT(lpsc->pd), 0, 0);
0130 
0131         regmap_write_bits(lpsc->regmap, PDCTL(lpsc->pd), PDCTL_EPCGOOD,
0132                   PDCTL_EPCGOOD);
0133     } else {
0134         regmap_write(lpsc->regmap, PTCMD, BIT(lpsc->pd));
0135     }
0136 
0137     regmap_read_poll_timeout(lpsc->regmap, PTSTAT, ptstat,
0138                  !(ptstat & BIT(lpsc->pd)), 0, 0);
0139 
0140     regmap_read_poll_timeout(lpsc->regmap, MDSTAT(lpsc->md), mdstat,
0141                  (mdstat & MDSTAT_STATE_MASK) == next_state,
0142                  0, 0);
0143 }
0144 
0145 static int davinci_lpsc_clk_enable(struct clk_hw *hw)
0146 {
0147     struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
0148 
0149     davinci_lpsc_config(lpsc, LPSC_STATE_ENABLE);
0150 
0151     return 0;
0152 }
0153 
0154 static void davinci_lpsc_clk_disable(struct clk_hw *hw)
0155 {
0156     struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
0157 
0158     davinci_lpsc_config(lpsc, LPSC_STATE_DISABLE);
0159 }
0160 
0161 static int davinci_lpsc_clk_is_enabled(struct clk_hw *hw)
0162 {
0163     struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
0164     u32 mdstat;
0165 
0166     regmap_read(lpsc->regmap, MDSTAT(lpsc->md), &mdstat);
0167 
0168     return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
0169 }
0170 
0171 static const struct clk_ops davinci_lpsc_clk_ops = {
0172     .enable     = davinci_lpsc_clk_enable,
0173     .disable    = davinci_lpsc_clk_disable,
0174     .is_enabled = davinci_lpsc_clk_is_enabled,
0175 };
0176 
0177 static int davinci_psc_genpd_attach_dev(struct generic_pm_domain *pm_domain,
0178                     struct device *dev)
0179 {
0180     struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
0181     struct clk *clk;
0182     int ret;
0183 
0184     /*
0185      * pm_clk_remove_clk() will call clk_put(), so we have to use clk_get()
0186      * to get the clock instead of using lpsc->hw.clk directly.
0187      */
0188     clk = clk_get_sys(best_dev_name(lpsc->dev), clk_hw_get_name(&lpsc->hw));
0189     if (IS_ERR(clk))
0190         return (PTR_ERR(clk));
0191 
0192     ret = pm_clk_create(dev);
0193     if (ret < 0)
0194         goto fail_clk_put;
0195 
0196     ret = pm_clk_add_clk(dev, clk);
0197     if (ret < 0)
0198         goto fail_pm_clk_destroy;
0199 
0200     lpsc->genpd_clk = clk;
0201 
0202     return 0;
0203 
0204 fail_pm_clk_destroy:
0205     pm_clk_destroy(dev);
0206 fail_clk_put:
0207     clk_put(clk);
0208 
0209     return ret;
0210 }
0211 
0212 static void davinci_psc_genpd_detach_dev(struct generic_pm_domain *pm_domain,
0213                      struct device *dev)
0214 {
0215     struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(pm_domain);
0216 
0217     pm_clk_remove_clk(dev, lpsc->genpd_clk);
0218     pm_clk_destroy(dev);
0219 
0220     lpsc->genpd_clk = NULL;
0221 }
0222 
0223 /**
0224  * davinci_lpsc_clk_register - register LPSC clock
0225  * @dev: the clocks's device or NULL
0226  * @name: name of this clock
0227  * @parent_name: name of clock's parent
0228  * @regmap: PSC MMIO region
0229  * @md: local PSC number
0230  * @pd: power domain
0231  * @flags: LPSC_* flags
0232  */
0233 static struct davinci_lpsc_clk *
0234 davinci_lpsc_clk_register(struct device *dev, const char *name,
0235               const char *parent_name, struct regmap *regmap,
0236               u32 md, u32 pd, u32 flags)
0237 {
0238     struct clk_init_data init;
0239     struct davinci_lpsc_clk *lpsc;
0240     int ret;
0241     bool is_on;
0242 
0243     lpsc = kzalloc(sizeof(*lpsc), GFP_KERNEL);
0244     if (!lpsc)
0245         return ERR_PTR(-ENOMEM);
0246 
0247     init.name = name;
0248     init.ops = &davinci_lpsc_clk_ops;
0249     init.parent_names = (parent_name ? &parent_name : NULL);
0250     init.num_parents = (parent_name ? 1 : 0);
0251     init.flags = 0;
0252 
0253     if (flags & LPSC_ALWAYS_ENABLED)
0254         init.flags |= CLK_IS_CRITICAL;
0255 
0256     if (flags & LPSC_SET_RATE_PARENT)
0257         init.flags |= CLK_SET_RATE_PARENT;
0258 
0259     lpsc->dev = dev;
0260     lpsc->regmap = regmap;
0261     lpsc->hw.init = &init;
0262     lpsc->md = md;
0263     lpsc->pd = pd;
0264     lpsc->flags = flags;
0265 
0266     ret = clk_hw_register(dev, &lpsc->hw);
0267     if (ret < 0) {
0268         kfree(lpsc);
0269         return ERR_PTR(ret);
0270     }
0271 
0272     /* for now, genpd is only registered when using device-tree */
0273     if (!dev || !dev->of_node)
0274         return lpsc;
0275 
0276     /* genpd attach needs a way to look up this clock */
0277     ret = clk_hw_register_clkdev(&lpsc->hw, name, best_dev_name(dev));
0278 
0279     lpsc->pm_domain.name = devm_kasprintf(dev, GFP_KERNEL, "%s: %s",
0280                           best_dev_name(dev), name);
0281     lpsc->pm_domain.attach_dev = davinci_psc_genpd_attach_dev;
0282     lpsc->pm_domain.detach_dev = davinci_psc_genpd_detach_dev;
0283     lpsc->pm_domain.flags = GENPD_FLAG_PM_CLK;
0284 
0285     is_on = davinci_lpsc_clk_is_enabled(&lpsc->hw);
0286     pm_genpd_init(&lpsc->pm_domain, NULL, is_on);
0287 
0288     return lpsc;
0289 }
0290 
0291 static int davinci_lpsc_clk_reset(struct clk *clk, bool reset)
0292 {
0293     struct clk_hw *hw = __clk_get_hw(clk);
0294     struct davinci_lpsc_clk *lpsc = to_davinci_lpsc_clk(hw);
0295     u32 mdctl;
0296 
0297     if (IS_ERR_OR_NULL(lpsc))
0298         return -EINVAL;
0299 
0300     mdctl = reset ? 0 : MDCTL_LRESET;
0301     regmap_write_bits(lpsc->regmap, MDCTL(lpsc->md), MDCTL_LRESET, mdctl);
0302 
0303     return 0;
0304 }
0305 
0306 static int davinci_psc_reset_assert(struct reset_controller_dev *rcdev,
0307                     unsigned long id)
0308 {
0309     struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
0310     struct clk *clk = psc->clk_data.clks[id];
0311 
0312     return davinci_lpsc_clk_reset(clk, true);
0313 }
0314 
0315 static int davinci_psc_reset_deassert(struct reset_controller_dev *rcdev,
0316                       unsigned long id)
0317 {
0318     struct davinci_psc_data *psc = to_davinci_psc_data(rcdev);
0319     struct clk *clk = psc->clk_data.clks[id];
0320 
0321     return davinci_lpsc_clk_reset(clk, false);
0322 }
0323 
0324 static const struct reset_control_ops davinci_psc_reset_ops = {
0325     .assert     = davinci_psc_reset_assert,
0326     .deassert   = davinci_psc_reset_deassert,
0327 };
0328 
0329 static int davinci_psc_reset_of_xlate(struct reset_controller_dev *rcdev,
0330                       const struct of_phandle_args *reset_spec)
0331 {
0332     struct of_phandle_args clkspec = *reset_spec; /* discard const qualifier */
0333     struct clk *clk;
0334     struct clk_hw *hw;
0335     struct davinci_lpsc_clk *lpsc;
0336 
0337     /* the clock node is the same as the reset node */
0338     clk = of_clk_get_from_provider(&clkspec);
0339     if (IS_ERR(clk))
0340         return PTR_ERR(clk);
0341 
0342     hw = __clk_get_hw(clk);
0343     lpsc = to_davinci_lpsc_clk(hw);
0344     clk_put(clk);
0345 
0346     /* not all modules support local reset */
0347     if (!(lpsc->flags & LPSC_LOCAL_RESET))
0348         return -EINVAL;
0349 
0350     return lpsc->md;
0351 }
0352 
0353 static const struct regmap_config davinci_psc_regmap_config = {
0354     .reg_bits   = 32,
0355     .reg_stride = 4,
0356     .val_bits   = 32,
0357 };
0358 
0359 static struct davinci_psc_data *
0360 __davinci_psc_register_clocks(struct device *dev,
0361                   const struct davinci_lpsc_clk_info *info,
0362                   int num_clks,
0363                   void __iomem *base)
0364 {
0365     struct davinci_psc_data *psc;
0366     struct clk **clks;
0367     struct generic_pm_domain **pm_domains;
0368     struct regmap *regmap;
0369     int i, ret;
0370 
0371     psc = kzalloc(sizeof(*psc), GFP_KERNEL);
0372     if (!psc)
0373         return ERR_PTR(-ENOMEM);
0374 
0375     clks = kmalloc_array(num_clks, sizeof(*clks), GFP_KERNEL);
0376     if (!clks) {
0377         ret = -ENOMEM;
0378         goto err_free_psc;
0379     }
0380 
0381     psc->clk_data.clks = clks;
0382     psc->clk_data.clk_num = num_clks;
0383 
0384     /*
0385      * init array with error so that of_clk_src_onecell_get() doesn't
0386      * return NULL for gaps in the sparse array
0387      */
0388     for (i = 0; i < num_clks; i++)
0389         clks[i] = ERR_PTR(-ENOENT);
0390 
0391     pm_domains = kcalloc(num_clks, sizeof(*pm_domains), GFP_KERNEL);
0392     if (!pm_domains) {
0393         ret = -ENOMEM;
0394         goto err_free_clks;
0395     }
0396 
0397     psc->pm_data.domains = pm_domains;
0398     psc->pm_data.num_domains = num_clks;
0399 
0400     regmap = regmap_init_mmio(dev, base, &davinci_psc_regmap_config);
0401     if (IS_ERR(regmap)) {
0402         ret = PTR_ERR(regmap);
0403         goto err_free_pm_domains;
0404     }
0405 
0406     for (; info->name; info++) {
0407         struct davinci_lpsc_clk *lpsc;
0408 
0409         lpsc = davinci_lpsc_clk_register(dev, info->name, info->parent,
0410                          regmap, info->md, info->pd,
0411                          info->flags);
0412         if (IS_ERR(lpsc)) {
0413             dev_warn(dev, "Failed to register %s (%ld)\n",
0414                  info->name, PTR_ERR(lpsc));
0415             continue;
0416         }
0417 
0418         clks[info->md] = lpsc->hw.clk;
0419         pm_domains[info->md] = &lpsc->pm_domain;
0420     }
0421 
0422     /*
0423      * for now, a reset controller is only registered when there is a device
0424      * to associate it with.
0425      */
0426     if (!dev)
0427         return psc;
0428 
0429     psc->rcdev.ops = &davinci_psc_reset_ops;
0430     psc->rcdev.owner = THIS_MODULE;
0431     psc->rcdev.dev = dev;
0432     psc->rcdev.of_node = dev->of_node;
0433     psc->rcdev.of_reset_n_cells = 1;
0434     psc->rcdev.of_xlate = davinci_psc_reset_of_xlate;
0435     psc->rcdev.nr_resets = num_clks;
0436 
0437     ret = devm_reset_controller_register(dev, &psc->rcdev);
0438     if (ret < 0)
0439         dev_warn(dev, "Failed to register reset controller (%d)\n", ret);
0440 
0441     return psc;
0442 
0443 err_free_pm_domains:
0444     kfree(pm_domains);
0445 err_free_clks:
0446     kfree(clks);
0447 err_free_psc:
0448     kfree(psc);
0449 
0450     return ERR_PTR(ret);
0451 }
0452 
0453 int davinci_psc_register_clocks(struct device *dev,
0454                 const struct davinci_lpsc_clk_info *info,
0455                 u8 num_clks,
0456                 void __iomem *base)
0457 {
0458     struct davinci_psc_data *psc;
0459 
0460     psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
0461     if (IS_ERR(psc))
0462         return PTR_ERR(psc);
0463 
0464     for (; info->name; info++) {
0465         const struct davinci_lpsc_clkdev_info *cdevs = info->cdevs;
0466         struct clk *clk = psc->clk_data.clks[info->md];
0467 
0468         if (!cdevs || IS_ERR_OR_NULL(clk))
0469             continue;
0470 
0471         for (; cdevs->con_id || cdevs->dev_id; cdevs++)
0472             clk_register_clkdev(clk, cdevs->con_id, cdevs->dev_id);
0473     }
0474 
0475     return 0;
0476 }
0477 
0478 int of_davinci_psc_clk_init(struct device *dev,
0479                 const struct davinci_lpsc_clk_info *info,
0480                 u8 num_clks,
0481                 void __iomem *base)
0482 {
0483     struct device_node *node = dev->of_node;
0484     struct davinci_psc_data *psc;
0485 
0486     psc = __davinci_psc_register_clocks(dev, info, num_clks, base);
0487     if (IS_ERR(psc))
0488         return PTR_ERR(psc);
0489 
0490     of_genpd_add_provider_onecell(node, &psc->pm_data);
0491 
0492     of_clk_add_provider(node, of_clk_src_onecell_get, &psc->clk_data);
0493 
0494     return 0;
0495 }
0496 
0497 static const struct of_device_id davinci_psc_of_match[] = {
0498 #ifdef CONFIG_ARCH_DAVINCI_DA850
0499     { .compatible = "ti,da850-psc0", .data = &of_da850_psc0_init_data },
0500     { .compatible = "ti,da850-psc1", .data = &of_da850_psc1_init_data },
0501 #endif
0502     { }
0503 };
0504 
0505 static const struct platform_device_id davinci_psc_id_table[] = {
0506 #ifdef CONFIG_ARCH_DAVINCI_DA830
0507     { .name = "da830-psc0", .driver_data = (kernel_ulong_t)&da830_psc0_init_data },
0508     { .name = "da830-psc1", .driver_data = (kernel_ulong_t)&da830_psc1_init_data },
0509 #endif
0510 #ifdef CONFIG_ARCH_DAVINCI_DA850
0511     { .name = "da850-psc0", .driver_data = (kernel_ulong_t)&da850_psc0_init_data },
0512     { .name = "da850-psc1", .driver_data = (kernel_ulong_t)&da850_psc1_init_data },
0513 #endif
0514 #ifdef CONFIG_ARCH_DAVINCI_DM355
0515     { .name = "dm355-psc",  .driver_data = (kernel_ulong_t)&dm355_psc_init_data  },
0516 #endif
0517 #ifdef CONFIG_ARCH_DAVINCI_DM365
0518     { .name = "dm365-psc",  .driver_data = (kernel_ulong_t)&dm365_psc_init_data  },
0519 #endif
0520 #ifdef CONFIG_ARCH_DAVINCI_DM644x
0521     { .name = "dm644x-psc", .driver_data = (kernel_ulong_t)&dm644x_psc_init_data },
0522 #endif
0523 #ifdef CONFIG_ARCH_DAVINCI_DM646x
0524     { .name = "dm646x-psc", .driver_data = (kernel_ulong_t)&dm646x_psc_init_data },
0525 #endif
0526     { }
0527 };
0528 
0529 static int davinci_psc_probe(struct platform_device *pdev)
0530 {
0531     struct device *dev = &pdev->dev;
0532     const struct of_device_id *of_id;
0533     const struct davinci_psc_init_data *init_data = NULL;
0534     void __iomem *base;
0535     int ret;
0536 
0537     of_id = of_match_device(davinci_psc_of_match, dev);
0538     if (of_id)
0539         init_data = of_id->data;
0540     else if (pdev->id_entry)
0541         init_data = (void *)pdev->id_entry->driver_data;
0542 
0543     if (!init_data) {
0544         dev_err(dev, "unable to find driver init data\n");
0545         return -EINVAL;
0546     }
0547 
0548     base = devm_platform_ioremap_resource(pdev, 0);
0549     if (IS_ERR(base))
0550         return PTR_ERR(base);
0551 
0552     ret = devm_clk_bulk_get(dev, init_data->num_parent_clks,
0553                 init_data->parent_clks);
0554     if (ret < 0)
0555         return ret;
0556 
0557     return init_data->psc_init(dev, base);
0558 }
0559 
0560 static struct platform_driver davinci_psc_driver = {
0561     .probe      = davinci_psc_probe,
0562     .driver     = {
0563         .name       = "davinci-psc-clk",
0564         .of_match_table = davinci_psc_of_match,
0565     },
0566     .id_table   = davinci_psc_id_table,
0567 };
0568 
0569 static int __init davinci_psc_driver_init(void)
0570 {
0571     return platform_driver_register(&davinci_psc_driver);
0572 }
0573 
0574 /* has to be postcore_initcall because davinci_gpio depend on PSC clocks */
0575 postcore_initcall(davinci_psc_driver_init);
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!