clk/davinci/psc-dm365.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PSC clock descriptions for TI DaVinci DM365
0004  *
0005  * Copyright (C) 2018 David Lechner <david@lechnology.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk/davinci.h>
0010 #include <linux/clk.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/init.h>
0013 #include <linux/kernel.h>
0014 #include <linux/types.h>
0015
0016 #include "psc.h"
0017
0018 LPSC_CLKDEV1(vpss_slave_clkdev,     "slave",    "vpss");
0019 LPSC_CLKDEV1(spi1_clkdev,       NULL,       "spi_davinci.1");
0020 LPSC_CLKDEV1(mmcsd1_clkdev,     NULL,       "da830-mmc.1");
0021 LPSC_CLKDEV1(asp0_clkdev,       NULL,       "davinci-mcbsp");
0022 LPSC_CLKDEV1(usb_clkdev,        "usb",      NULL);
0023 LPSC_CLKDEV1(spi2_clkdev,       NULL,       "spi_davinci.2");
0024 LPSC_CLKDEV2(aemif_clkdev,      "aemif",    NULL,
0025                     NULL,       "ti-aemif");
0026 LPSC_CLKDEV1(mmcsd0_clkdev,     NULL,       "da830-mmc.0");
0027 LPSC_CLKDEV1(i2c_clkdev,        NULL,       "i2c_davinci.1");
0028 LPSC_CLKDEV1(uart0_clkdev,      NULL,       "serial8250.0");
0029 LPSC_CLKDEV1(uart1_clkdev,      NULL,       "serial8250.1");
0030 LPSC_CLKDEV1(spi0_clkdev,       NULL,       "spi_davinci.0");
0031 /* REVISIT: gpio-davinci.c should be modified to drop con_id */
0032 LPSC_CLKDEV1(gpio_clkdev,       "gpio",     NULL);
0033 LPSC_CLKDEV1(timer0_clkdev,     "timer0",   NULL);
0034 LPSC_CLKDEV1(timer2_clkdev,     NULL,       "davinci-wdt");
0035 LPSC_CLKDEV1(spi3_clkdev,       NULL,       "spi_davinci.3");
0036 LPSC_CLKDEV1(spi4_clkdev,       NULL,       "spi_davinci.4");
0037 LPSC_CLKDEV2(emac_clkdev,       NULL,       "davinci_emac.1",
0038                     "fck",      "davinci_mdio.0");
0039 LPSC_CLKDEV1(voice_codec_clkdev,    NULL,       "davinci_voicecodec");
0040 LPSC_CLKDEV1(vpss_dac_clkdev,       "vpss_dac", NULL);
0041 LPSC_CLKDEV1(vpss_master_clkdev,    "master",   "vpss");
0042
0043 static const struct davinci_lpsc_clk_info dm365_psc_info[] = {
0044     LPSC(1,  0, vpss_slave,  pll1_sysclk5, vpss_slave_clkdev,  0),
0045     LPSC(5,  0, timer3,      pll1_auxclk,  NULL,               0),
0046     LPSC(6,  0, spi1,        pll1_sysclk4, spi1_clkdev,        0),
0047     LPSC(7,  0, mmcsd1,      pll1_sysclk4, mmcsd1_clkdev,      0),
0048     LPSC(8,  0, asp0,        pll1_sysclk4, asp0_clkdev,        0),
0049     LPSC(9,  0, usb,         pll1_auxclk,  usb_clkdev,         0),
0050     LPSC(10, 0, pwm3,        pll1_auxclk,  NULL,               0),
0051     LPSC(11, 0, spi2,        pll1_sysclk4, spi2_clkdev,        0),
0052     LPSC(12, 0, rto,         pll1_sysclk4, NULL,               0),
0053     LPSC(14, 0, aemif,       pll1_sysclk4, aemif_clkdev,       0),
0054     LPSC(15, 0, mmcsd0,      pll1_sysclk8, mmcsd0_clkdev,      0),
0055     LPSC(18, 0, i2c,         pll1_auxclk,  i2c_clkdev,         0),
0056     LPSC(19, 0, uart0,       pll1_auxclk,  uart0_clkdev,       0),
0057     LPSC(20, 0, uart1,       pll1_sysclk4, uart1_clkdev,       0),
0058     LPSC(22, 0, spi0,        pll1_sysclk4, spi0_clkdev,        0),
0059     LPSC(23, 0, pwm0,        pll1_auxclk,  NULL,               0),
0060     LPSC(24, 0, pwm1,        pll1_auxclk,  NULL,               0),
0061     LPSC(25, 0, pwm2,        pll1_auxclk,  NULL,               0),
0062     LPSC(26, 0, gpio,        pll1_sysclk4, gpio_clkdev,        0),
0063     LPSC(27, 0, timer0,      pll1_auxclk,  timer0_clkdev,      LPSC_ALWAYS_ENABLED),
0064     LPSC(28, 0, timer1,      pll1_auxclk,  NULL,               0),
0065     /* REVISIT: why can't this be disabled? */
0066     LPSC(29, 0, timer2,      pll1_auxclk,  timer2_clkdev,      LPSC_ALWAYS_ENABLED),
0067     LPSC(31, 0, arm,         pll2_sysclk2, NULL,               LPSC_ALWAYS_ENABLED),
0068     LPSC(38, 0, spi3,        pll1_sysclk4, spi3_clkdev,        0),
0069     LPSC(39, 0, spi4,        pll1_auxclk,  spi4_clkdev,        0),
0070     LPSC(40, 0, emac,        pll1_sysclk4, emac_clkdev,        0),
0071     /*
0072      * The TRM (ARM Subsystem User's Guide) shows two clocks input into
0073      * voice codec module (PLL2 SYSCLK4 with a DIV2 and PLL1 SYSCLK4). Its
0074      * not fully clear from documentation which clock should be considered
0075      * as parent for PSC. The clock chosen here is to maintain
0076      * compatibility with existing code in arch/arm/mach-davinci/dm365.c
0077      */
0078     LPSC(44, 0, voice_codec, pll2_sysclk4, voice_codec_clkdev, 0),
0079     /*
0080      * Its not fully clear from TRM (ARM Subsystem User's Guide) as to what
0081      * the parent of VPSS DAC LPSC should actually be. PLL1 SYSCLK3 feeds
0082      * into HDVICP and MJCP. The clock chosen here is to remain compatible
0083      * with code existing in arch/arm/mach-davinci/dm365.c
0084      */
0085     LPSC(46, 0, vpss_dac,    pll1_sysclk3, vpss_dac_clkdev,    0),
0086     LPSC(47, 0, vpss_master, pll1_sysclk5, vpss_master_clkdev, 0),
0087     LPSC(50, 0, mjcp,        pll1_sysclk3, NULL,               0),
0088     { }
0089 };
0090
0091 int dm365_psc_init(struct device *dev, void __iomem *base)
0092 {
0093     return davinci_psc_register_clocks(dev, dm365_psc_info, 52, base);
0094 }
0095
0096 static struct clk_bulk_data dm365_psc_parent_clks[] = {
0097     { .id = "pll1_sysclk1" },
0098     { .id = "pll1_sysclk3" },
0099     { .id = "pll1_sysclk4" },
0100     { .id = "pll1_sysclk5" },
0101     { .id = "pll1_sysclk8" },
0102     { .id = "pll2_sysclk2" },
0103     { .id = "pll2_sysclk4" },
0104     { .id = "pll1_auxclk"  },
0105 };
0106
0107 const struct davinci_psc_init_data dm365_psc_init_data = {
0108     .parent_clks        = dm365_psc_parent_clks,
0109     .num_parent_clks    = ARRAY_SIZE(dm365_psc_parent_clks),
0110     .psc_init       = &dm365_psc_init,
0111 };