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0008 #include <linux/clk-provider.h>
0009 #include <linux/reset-controller.h>
0010 #include <linux/clk.h>
0011 #include <linux/clkdev.h>
0012 #include <linux/init.h>
0013 #include <linux/kernel.h>
0014 #include <linux/of.h>
0015 #include <linux/types.h>
0016
0017 #include "psc.h"
0018
0019 LPSC_CLKDEV1(emifa_clkdev, NULL, "ti-aemif");
0020 LPSC_CLKDEV1(spi0_clkdev, NULL, "spi_davinci.0");
0021 LPSC_CLKDEV1(mmcsd0_clkdev, NULL, "da830-mmc.0");
0022 LPSC_CLKDEV1(uart0_clkdev, NULL, "serial8250.0");
0023
0024 LPSC_CLKDEV1(arm_clkdev, "arm", NULL);
0025 LPSC_CLKDEV1(dsp_clkdev, NULL, "davinci-rproc.0");
0026
0027 static const struct davinci_lpsc_clk_info da850_psc0_info[] = {
0028 LPSC(0, 0, tpcc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
0029 LPSC(1, 0, tptc0, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
0030 LPSC(2, 0, tptc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
0031 LPSC(3, 0, emifa, async1, emifa_clkdev, 0),
0032 LPSC(4, 0, spi0, pll0_sysclk2, spi0_clkdev, 0),
0033 LPSC(5, 0, mmcsd0, pll0_sysclk2, mmcsd0_clkdev, 0),
0034 LPSC(6, 0, aintc, pll0_sysclk4, NULL, LPSC_ALWAYS_ENABLED),
0035 LPSC(7, 0, arm_rom, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
0036 LPSC(9, 0, uart0, pll0_sysclk2, uart0_clkdev, 0),
0037 LPSC(13, 0, pruss, pll0_sysclk2, NULL, 0),
0038 LPSC(14, 0, arm, pll0_sysclk6, arm_clkdev, LPSC_ALWAYS_ENABLED | LPSC_SET_RATE_PARENT),
0039 LPSC(15, 1, dsp, pll0_sysclk1, dsp_clkdev, LPSC_FORCE | LPSC_LOCAL_RESET),
0040 { }
0041 };
0042
0043 LPSC_CLKDEV3(usb0_clkdev, "fck", "da830-usb-phy-clks",
0044 NULL, "musb-da8xx",
0045 NULL, "cppi41-dmaengine");
0046 LPSC_CLKDEV1(usb1_clkdev, NULL, "ohci-da8xx");
0047
0048 LPSC_CLKDEV1(gpio_clkdev, "gpio", NULL);
0049 LPSC_CLKDEV2(emac_clkdev, NULL, "davinci_emac.1",
0050 "fck", "davinci_mdio.0");
0051 LPSC_CLKDEV1(mcasp0_clkdev, NULL, "davinci-mcasp.0");
0052 LPSC_CLKDEV1(sata_clkdev, "fck", "ahci_da850");
0053 LPSC_CLKDEV1(vpif_clkdev, NULL, "vpif");
0054 LPSC_CLKDEV1(spi1_clkdev, NULL, "spi_davinci.1");
0055 LPSC_CLKDEV1(i2c1_clkdev, NULL, "i2c_davinci.2");
0056 LPSC_CLKDEV1(uart1_clkdev, NULL, "serial8250.1");
0057 LPSC_CLKDEV1(uart2_clkdev, NULL, "serial8250.2");
0058 LPSC_CLKDEV1(mcbsp0_clkdev, NULL, "davinci-mcbsp.0");
0059 LPSC_CLKDEV1(mcbsp1_clkdev, NULL, "davinci-mcbsp.1");
0060 LPSC_CLKDEV1(lcdc_clkdev, "fck", "da8xx_lcdc.0");
0061 LPSC_CLKDEV3(ehrpwm_clkdev, "fck", "ehrpwm.0",
0062 "fck", "ehrpwm.1",
0063 NULL, "da830-tbclksync");
0064 LPSC_CLKDEV1(mmcsd1_clkdev, NULL, "da830-mmc.1");
0065 LPSC_CLKDEV3(ecap_clkdev, "fck", "ecap.0",
0066 "fck", "ecap.1",
0067 "fck", "ecap.2");
0068
0069 static struct reset_control_lookup da850_psc0_reset_lookup_table[] = {
0070 RESET_LOOKUP("da850-psc0", 15, "davinci-rproc.0", NULL),
0071 };
0072
0073 static int da850_psc0_init(struct device *dev, void __iomem *base)
0074 {
0075 reset_controller_add_lookup(da850_psc0_reset_lookup_table,
0076 ARRAY_SIZE(da850_psc0_reset_lookup_table));
0077 return davinci_psc_register_clocks(dev, da850_psc0_info, 16, base);
0078 }
0079
0080 static int of_da850_psc0_init(struct device *dev, void __iomem *base)
0081 {
0082 return of_davinci_psc_clk_init(dev, da850_psc0_info, 16, base);
0083 }
0084
0085 static struct clk_bulk_data da850_psc0_parent_clks[] = {
0086 { .id = "pll0_sysclk1" },
0087 { .id = "pll0_sysclk2" },
0088 { .id = "pll0_sysclk4" },
0089 { .id = "pll0_sysclk6" },
0090 { .id = "async1" },
0091 };
0092
0093 const struct davinci_psc_init_data da850_psc0_init_data = {
0094 .parent_clks = da850_psc0_parent_clks,
0095 .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks),
0096 .psc_init = &da850_psc0_init,
0097 };
0098
0099 const struct davinci_psc_init_data of_da850_psc0_init_data = {
0100 .parent_clks = da850_psc0_parent_clks,
0101 .num_parent_clks = ARRAY_SIZE(da850_psc0_parent_clks),
0102 .psc_init = &of_da850_psc0_init,
0103 };
0104
0105 static const struct davinci_lpsc_clk_info da850_psc1_info[] = {
0106 LPSC(0, 0, tpcc1, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
0107 LPSC(1, 0, usb0, pll0_sysclk2, usb0_clkdev, 0),
0108 LPSC(2, 0, usb1, pll0_sysclk4, usb1_clkdev, 0),
0109 LPSC(3, 0, gpio, pll0_sysclk4, gpio_clkdev, 0),
0110 LPSC(5, 0, emac, pll0_sysclk4, emac_clkdev, 0),
0111 LPSC(6, 0, ddr, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
0112 LPSC(7, 0, mcasp0, async3, mcasp0_clkdev, 0),
0113 LPSC(8, 0, sata, pll0_sysclk2, sata_clkdev, LPSC_FORCE),
0114 LPSC(9, 0, vpif, pll0_sysclk2, vpif_clkdev, 0),
0115 LPSC(10, 0, spi1, async3, spi1_clkdev, 0),
0116 LPSC(11, 0, i2c1, pll0_sysclk4, i2c1_clkdev, 0),
0117 LPSC(12, 0, uart1, async3, uart1_clkdev, 0),
0118 LPSC(13, 0, uart2, async3, uart2_clkdev, 0),
0119 LPSC(14, 0, mcbsp0, async3, mcbsp0_clkdev, 0),
0120 LPSC(15, 0, mcbsp1, async3, mcbsp1_clkdev, 0),
0121 LPSC(16, 0, lcdc, pll0_sysclk2, lcdc_clkdev, 0),
0122 LPSC(17, 0, ehrpwm, async3, ehrpwm_clkdev, 0),
0123 LPSC(18, 0, mmcsd1, pll0_sysclk2, mmcsd1_clkdev, 0),
0124 LPSC(20, 0, ecap, async3, ecap_clkdev, 0),
0125 LPSC(21, 0, tptc2, pll0_sysclk2, NULL, LPSC_ALWAYS_ENABLED),
0126 { }
0127 };
0128
0129 static int da850_psc1_init(struct device *dev, void __iomem *base)
0130 {
0131 return davinci_psc_register_clocks(dev, da850_psc1_info, 32, base);
0132 }
0133
0134 static int of_da850_psc1_init(struct device *dev, void __iomem *base)
0135 {
0136 return of_davinci_psc_clk_init(dev, da850_psc1_info, 32, base);
0137 }
0138
0139 static struct clk_bulk_data da850_psc1_parent_clks[] = {
0140 { .id = "pll0_sysclk2" },
0141 { .id = "pll0_sysclk4" },
0142 { .id = "async3" },
0143 };
0144
0145 const struct davinci_psc_init_data da850_psc1_init_data = {
0146 .parent_clks = da850_psc1_parent_clks,
0147 .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks),
0148 .psc_init = &da850_psc1_init,
0149 };
0150
0151 const struct davinci_psc_init_data of_da850_psc1_init_data = {
0152 .parent_clks = da850_psc1_parent_clks,
0153 .num_parent_clks = ARRAY_SIZE(da850_psc1_parent_clks),
0154 .psc_init = &of_da850_psc1_init,
0155 };
