clk/davinci/psc-da830.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PSC clock descriptions for TI DA830/OMAP-L137/AM17XX
0004  *
0005  * Copyright (C) 2018 David Lechner <david@lechnology.com>
0006  */
0007
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk.h>
0010 #include <linux/clkdev.h>
0011 #include <linux/init.h>
0012 #include <linux/kernel.h>
0013 #include <linux/types.h>
0014
0015 #include "psc.h"
0016
0017 LPSC_CLKDEV1(aemif_clkdev,  NULL,   "ti-aemif");
0018 LPSC_CLKDEV1(spi0_clkdev,   NULL,   "spi_davinci.0");
0019 LPSC_CLKDEV1(mmcsd_clkdev,  NULL,   "da830-mmc.0");
0020 LPSC_CLKDEV1(uart0_clkdev,  NULL,   "serial8250.0");
0021
0022 static const struct davinci_lpsc_clk_info da830_psc0_info[] = {
0023     LPSC(0,  0, tpcc,     pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0024     LPSC(1,  0, tptc0,    pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0025     LPSC(2,  0, tptc1,    pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0026     LPSC(3,  0, aemif,    pll0_sysclk3, aemif_clkdev, LPSC_ALWAYS_ENABLED),
0027     LPSC(4,  0, spi0,     pll0_sysclk2, spi0_clkdev,  0),
0028     LPSC(5,  0, mmcsd,    pll0_sysclk2, mmcsd_clkdev, 0),
0029     LPSC(6,  0, aintc,    pll0_sysclk4, NULL,         LPSC_ALWAYS_ENABLED),
0030     LPSC(7,  0, arm_rom,  pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0031     LPSC(8,  0, secu_mgr, pll0_sysclk4, NULL,         LPSC_ALWAYS_ENABLED),
0032     LPSC(9,  0, uart0,    pll0_sysclk2, uart0_clkdev, 0),
0033     LPSC(10, 0, scr0_ss,  pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0034     LPSC(11, 0, scr1_ss,  pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0035     LPSC(12, 0, scr2_ss,  pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0036     LPSC(13, 0, pruss,    pll0_sysclk2, NULL,         LPSC_ALWAYS_ENABLED),
0037     LPSC(14, 0, arm,      pll0_sysclk6, NULL,         LPSC_ALWAYS_ENABLED),
0038     { }
0039 };
0040
0041 static int da830_psc0_init(struct device *dev, void __iomem *base)
0042 {
0043     return davinci_psc_register_clocks(dev, da830_psc0_info, 16, base);
0044 }
0045
0046 static struct clk_bulk_data da830_psc0_parent_clks[] = {
0047     { .id = "pll0_sysclk2" },
0048     { .id = "pll0_sysclk3" },
0049     { .id = "pll0_sysclk4" },
0050     { .id = "pll0_sysclk6" },
0051 };
0052
0053 const struct davinci_psc_init_data da830_psc0_init_data = {
0054     .parent_clks        = da830_psc0_parent_clks,
0055     .num_parent_clks    = ARRAY_SIZE(da830_psc0_parent_clks),
0056     .psc_init       = &da830_psc0_init,
0057 };
0058
0059 LPSC_CLKDEV3(usb0_clkdev,   "fck",  "da830-usb-phy-clks",
0060                 NULL,   "musb-da8xx",
0061                 NULL,   "cppi41-dmaengine");
0062 LPSC_CLKDEV1(usb1_clkdev,   NULL,   "ohci-da8xx");
0063 /* REVISIT: gpio-davinci.c should be modified to drop con_id */
0064 LPSC_CLKDEV1(gpio_clkdev,   "gpio", NULL);
0065 LPSC_CLKDEV2(emac_clkdev,   NULL,   "davinci_emac.1",
0066                 "fck",  "davinci_mdio.0");
0067 LPSC_CLKDEV1(mcasp0_clkdev, NULL,   "davinci-mcasp.0");
0068 LPSC_CLKDEV1(mcasp1_clkdev, NULL,   "davinci-mcasp.1");
0069 LPSC_CLKDEV1(mcasp2_clkdev, NULL,   "davinci-mcasp.2");
0070 LPSC_CLKDEV1(spi1_clkdev,   NULL,   "spi_davinci.1");
0071 LPSC_CLKDEV1(i2c1_clkdev,   NULL,   "i2c_davinci.2");
0072 LPSC_CLKDEV1(uart1_clkdev,  NULL,   "serial8250.1");
0073 LPSC_CLKDEV1(uart2_clkdev,  NULL,   "serial8250.2");
0074 LPSC_CLKDEV1(lcdc_clkdev,   "fck",  "da8xx_lcdc.0");
0075 LPSC_CLKDEV2(pwm_clkdev,    "fck",  "ehrpwm.0",
0076                 "fck",  "ehrpwm.1");
0077 LPSC_CLKDEV3(ecap_clkdev,   "fck",  "ecap.0",
0078                 "fck",  "ecap.1",
0079                 "fck",  "ecap.2");
0080 LPSC_CLKDEV2(eqep_clkdev,   NULL,   "eqep.0",
0081                 NULL,   "eqep.1");
0082
0083 static const struct davinci_lpsc_clk_info da830_psc1_info[] = {
0084     LPSC(1,  0, usb0,   pll0_sysclk2, usb0_clkdev,   0),
0085     LPSC(2,  0, usb1,   pll0_sysclk4, usb1_clkdev,   0),
0086     LPSC(3,  0, gpio,   pll0_sysclk4, gpio_clkdev,   0),
0087     LPSC(5,  0, emac,   pll0_sysclk4, emac_clkdev,   0),
0088     LPSC(6,  0, emif3,  pll0_sysclk5, NULL,          LPSC_ALWAYS_ENABLED),
0089     LPSC(7,  0, mcasp0, pll0_sysclk2, mcasp0_clkdev, 0),
0090     LPSC(8,  0, mcasp1, pll0_sysclk2, mcasp1_clkdev, 0),
0091     LPSC(9,  0, mcasp2, pll0_sysclk2, mcasp2_clkdev, 0),
0092     LPSC(10, 0, spi1,   pll0_sysclk2, spi1_clkdev,   0),
0093     LPSC(11, 0, i2c1,   pll0_sysclk4, i2c1_clkdev,   0),
0094     LPSC(12, 0, uart1,  pll0_sysclk2, uart1_clkdev,  0),
0095     LPSC(13, 0, uart2,  pll0_sysclk2, uart2_clkdev,  0),
0096     LPSC(16, 0, lcdc,   pll0_sysclk2, lcdc_clkdev,   0),
0097     LPSC(17, 0, pwm,    pll0_sysclk2, pwm_clkdev,    0),
0098     LPSC(20, 0, ecap,   pll0_sysclk2, ecap_clkdev,   0),
0099     LPSC(21, 0, eqep,   pll0_sysclk2, eqep_clkdev,   0),
0100     { }
0101 };
0102
0103 static int da830_psc1_init(struct device *dev, void __iomem *base)
0104 {
0105     return davinci_psc_register_clocks(dev, da830_psc1_info, 32, base);
0106 }
0107
0108 static struct clk_bulk_data da830_psc1_parent_clks[] = {
0109     { .id = "pll0_sysclk2" },
0110     { .id = "pll0_sysclk4" },
0111     { .id = "pll0_sysclk5" },
0112 };
0113
0114 const struct davinci_psc_init_data da830_psc1_init_data = {
0115     .parent_clks        = da830_psc1_parent_clks,
0116     .num_parent_clks    = ARRAY_SIZE(da830_psc1_parent_clks),
0117     .psc_init       = &da830_psc1_init,
0118 };