clk/davinci/pll-dm644x.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PLL clock descriptions for TI DM644X
0004  *
0005  * Copyright (C) 2018 David Lechner <david@lechnology.com>
0006  */
0007
0008 #include <linux/bitops.h>
0009 #include <linux/clk/davinci.h>
0010 #include <linux/clkdev.h>
0011 #include <linux/init.h>
0012 #include <linux/types.h>
0013
0014 #include "pll.h"
0015
0016 static const struct davinci_pll_clk_info dm644x_pll1_info = {
0017     .name = "pll1",
0018     .pllm_mask = GENMASK(4, 0),
0019     .pllm_min = 1,
0020     .pllm_max = 32,
0021     .pllout_min_rate = 400000000,
0022     .pllout_max_rate = 600000000, /* 810MHz @ 1.3V, -810 only */
0023     .flags = PLL_HAS_CLKMODE | PLL_HAS_POSTDIV,
0024 };
0025
0026 SYSCLK(1, pll1_sysclk1, pll1_pllen, 4, SYSCLK_FIXED_DIV);
0027 SYSCLK(2, pll1_sysclk2, pll1_pllen, 4, SYSCLK_FIXED_DIV);
0028 SYSCLK(3, pll1_sysclk3, pll1_pllen, 4, SYSCLK_FIXED_DIV);
0029 SYSCLK(5, pll1_sysclk5, pll1_pllen, 4, SYSCLK_FIXED_DIV);
0030
0031 int dm644x_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
0032 {
0033     struct clk *clk;
0034
0035     davinci_pll_clk_register(dev, &dm644x_pll1_info, "ref_clk", base, cfgchip);
0036
0037     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
0038     clk_register_clkdev(clk, "pll1_sysclk1", "dm644x-psc");
0039
0040     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
0041     clk_register_clkdev(clk, "pll1_sysclk2", "dm644x-psc");
0042
0043     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
0044     clk_register_clkdev(clk, "pll1_sysclk3", "dm644x-psc");
0045
0046     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
0047     clk_register_clkdev(clk, "pll1_sysclk5", "dm644x-psc");
0048
0049     clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
0050     clk_register_clkdev(clk, "pll1_auxclk", "dm644x-psc");
0051
0052     davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
0053
0054     return 0;
0055 }
0056
0057 static const struct davinci_pll_clk_info dm644x_pll2_info = {
0058     .name = "pll2",
0059     .pllm_mask = GENMASK(4, 0),
0060     .pllm_min = 1,
0061     .pllm_max = 32,
0062     .pllout_min_rate = 400000000,
0063     .pllout_max_rate = 900000000,
0064     .flags = PLL_HAS_POSTDIV | PLL_POSTDIV_FIXED_DIV,
0065 };
0066
0067 SYSCLK(1, pll2_sysclk1, pll2_pllen, 4, 0);
0068 SYSCLK(2, pll2_sysclk2, pll2_pllen, 4, 0);
0069
0070 int dm644x_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
0071 {
0072     davinci_pll_clk_register(dev, &dm644x_pll2_info, "oscin", base, cfgchip);
0073
0074     davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
0075
0076     davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
0077
0078     davinci_pll_sysclkbp_clk_register(dev, "pll2_sysclkbp", base);
0079
0080     return 0;
0081 }