clk/davinci/pll-dm365.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * PLL clock descriptions for TI DM365
0004  *
0005  * Copyright (C) 2018 David Lechner <david@lechnology.com>
0006  */
0007
0008 #include <linux/bitops.h>
0009 #include <linux/clkdev.h>
0010 #include <linux/clk/davinci.h>
0011 #include <linux/init.h>
0012 #include <linux/kernel.h>
0013 #include <linux/types.h>
0014
0015 #include "pll.h"
0016
0017 #define OCSEL_OCSRC_ENABLE  0
0018
0019 static const struct davinci_pll_clk_info dm365_pll1_info = {
0020     .name = "pll1",
0021     .pllm_mask = GENMASK(9, 0),
0022     .pllm_min = 1,
0023     .pllm_max = 1023,
0024     .flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
0025          PLL_POSTDIV_ALWAYS_ENABLED | PLL_PLLM_2X,
0026 };
0027
0028 SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0029 SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0030 SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0031 SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0032 SYSCLK(5, pll1_sysclk5, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0033 SYSCLK(6, pll1_sysclk6, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0034 SYSCLK(7, pll1_sysclk7, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0035 SYSCLK(8, pll1_sysclk8, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0036 SYSCLK(9, pll1_sysclk9, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0037
0038 /*
0039  * This is a bit of a hack to make OCSEL[OCSRC] on DM365 look like OCSEL[OCSRC]
0040  * on DA850. On DM365, OCSEL[OCSRC] is just an enable/disable bit instead of a
0041  * multiplexer. By modeling it as a single parent mux clock, the clock code will
0042  * still do the right thing in this case.
0043  */
0044 static const char * const dm365_pll_obsclk_parent_names[] = {
0045     "oscin",
0046 };
0047
0048 static u32 dm365_pll_obsclk_table[] = {
0049     OCSEL_OCSRC_ENABLE,
0050 };
0051
0052 static const struct davinci_pll_obsclk_info dm365_pll1_obsclk_info = {
0053     .name = "pll1_obsclk",
0054     .parent_names = dm365_pll_obsclk_parent_names,
0055     .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
0056     .table = dm365_pll_obsclk_table,
0057     .ocsrc_mask = BIT(4),
0058 };
0059
0060 int dm365_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
0061 {
0062     struct clk *clk;
0063
0064     davinci_pll_clk_register(dev, &dm365_pll1_info, "ref_clk", base, cfgchip);
0065
0066     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
0067     clk_register_clkdev(clk, "pll1_sysclk1", "dm365-psc");
0068
0069     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
0070     clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
0071
0072     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
0073     clk_register_clkdev(clk, "pll1_sysclk3", "dm365-psc");
0074
0075     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk4, base);
0076     clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
0077
0078     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk5, base);
0079     clk_register_clkdev(clk, "pll1_sysclk5", "dm365-psc");
0080
0081     davinci_pll_sysclk_register(dev, &pll1_sysclk6, base);
0082
0083     davinci_pll_sysclk_register(dev, &pll1_sysclk7, base);
0084
0085     clk = davinci_pll_sysclk_register(dev, &pll1_sysclk8, base);
0086     clk_register_clkdev(clk, "pll1_sysclk8", "dm365-psc");
0087
0088     davinci_pll_sysclk_register(dev, &pll1_sysclk9, base);
0089
0090     clk = davinci_pll_auxclk_register(dev, "pll1_auxclk", base);
0091     clk_register_clkdev(clk, "pll1_auxclk", "dm355-psc");
0092
0093     davinci_pll_sysclkbp_clk_register(dev, "pll1_sysclkbp", base);
0094
0095     davinci_pll_obsclk_register(dev, &dm365_pll1_obsclk_info, base);
0096
0097     return 0;
0098 }
0099
0100 static const struct davinci_pll_clk_info dm365_pll2_info = {
0101     .name = "pll2",
0102     .pllm_mask = GENMASK(9, 0),
0103     .pllm_min = 1,
0104     .pllm_max = 1023,
0105     .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV | PLL_POSTDIV_ALWAYS_ENABLED |
0106          PLL_PLLM_2X,
0107 };
0108
0109 SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0110 SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0111 SYSCLK(3, pll2_sysclk3, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0112 SYSCLK(4, pll2_sysclk4, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0113 SYSCLK(5, pll2_sysclk5, pll2_pllen, 5, SYSCLK_ALWAYS_ENABLED);
0114
0115 static const struct davinci_pll_obsclk_info dm365_pll2_obsclk_info = {
0116     .name = "pll2_obsclk",
0117     .parent_names = dm365_pll_obsclk_parent_names,
0118     .num_parents = ARRAY_SIZE(dm365_pll_obsclk_parent_names),
0119     .table = dm365_pll_obsclk_table,
0120     .ocsrc_mask = BIT(4),
0121 };
0122
0123 int dm365_pll2_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
0124 {
0125     struct clk *clk;
0126
0127     davinci_pll_clk_register(dev, &dm365_pll2_info, "oscin", base, cfgchip);
0128
0129     davinci_pll_sysclk_register(dev, &pll2_sysclk1, base);
0130
0131     clk = davinci_pll_sysclk_register(dev, &pll2_sysclk2, base);
0132     clk_register_clkdev(clk, "pll1_sysclk2", "dm365-psc");
0133
0134     davinci_pll_sysclk_register(dev, &pll2_sysclk3, base);
0135
0136     clk = davinci_pll_sysclk_register(dev, &pll2_sysclk4, base);
0137     clk_register_clkdev(clk, "pll1_sysclk4", "dm365-psc");
0138
0139     davinci_pll_sysclk_register(dev, &pll2_sysclk5, base);
0140
0141     davinci_pll_auxclk_register(dev, "pll2_auxclk", base);
0142
0143     davinci_pll_obsclk_register(dev, &dm365_pll2_obsclk_info, base);
0144
0145     return 0;
0146 }