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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP
0004  *
0005  * Copyright (C) 2018 David Lechner <david@lechnology.com>
0006  */
0007 
0008 #include <linux/clk-provider.h>
0009 #include <linux/clk.h>
0010 #include <linux/clkdev.h>
0011 #include <linux/init.h>
0012 #include <linux/mfd/da8xx-cfgchip.h>
0013 #include <linux/mfd/syscon.h>
0014 #include <linux/of_device.h>
0015 #include <linux/of.h>
0016 #include <linux/platform_data/clk-da8xx-cfgchip.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/regmap.h>
0019 #include <linux/slab.h>
0020 
0021 /* --- Gate clocks --- */
0022 
0023 #define DA8XX_GATE_CLOCK_IS_DIV4P5  BIT(1)
0024 
0025 struct da8xx_cfgchip_gate_clk_info {
0026     const char *name;
0027     u32 cfgchip;
0028     u32 bit;
0029     u32 flags;
0030 };
0031 
0032 struct da8xx_cfgchip_gate_clk {
0033     struct clk_hw hw;
0034     struct regmap *regmap;
0035     u32 reg;
0036     u32 mask;
0037 };
0038 
0039 #define to_da8xx_cfgchip_gate_clk(_hw) \
0040     container_of((_hw), struct da8xx_cfgchip_gate_clk, hw)
0041 
0042 static int da8xx_cfgchip_gate_clk_enable(struct clk_hw *hw)
0043 {
0044     struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
0045 
0046     return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask);
0047 }
0048 
0049 static void da8xx_cfgchip_gate_clk_disable(struct clk_hw *hw)
0050 {
0051     struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
0052 
0053     regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0);
0054 }
0055 
0056 static int da8xx_cfgchip_gate_clk_is_enabled(struct clk_hw *hw)
0057 {
0058     struct da8xx_cfgchip_gate_clk *clk = to_da8xx_cfgchip_gate_clk(hw);
0059     unsigned int val;
0060 
0061     regmap_read(clk->regmap, clk->reg, &val);
0062 
0063     return !!(val & clk->mask);
0064 }
0065 
0066 static unsigned long da8xx_cfgchip_div4p5_recalc_rate(struct clk_hw *hw,
0067                               unsigned long parent_rate)
0068 {
0069     /* this clock divides by 4.5 */
0070     return parent_rate * 2 / 9;
0071 }
0072 
0073 static const struct clk_ops da8xx_cfgchip_gate_clk_ops = {
0074     .enable     = da8xx_cfgchip_gate_clk_enable,
0075     .disable    = da8xx_cfgchip_gate_clk_disable,
0076     .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
0077 };
0078 
0079 static const struct clk_ops da8xx_cfgchip_div4p5_clk_ops = {
0080     .enable     = da8xx_cfgchip_gate_clk_enable,
0081     .disable    = da8xx_cfgchip_gate_clk_disable,
0082     .is_enabled = da8xx_cfgchip_gate_clk_is_enabled,
0083     .recalc_rate    = da8xx_cfgchip_div4p5_recalc_rate,
0084 };
0085 
0086 static struct da8xx_cfgchip_gate_clk * __init
0087 da8xx_cfgchip_gate_clk_register(struct device *dev,
0088                 const struct da8xx_cfgchip_gate_clk_info *info,
0089                 struct regmap *regmap)
0090 {
0091     struct clk *parent;
0092     const char *parent_name;
0093     struct da8xx_cfgchip_gate_clk *gate;
0094     struct clk_init_data init;
0095     int ret;
0096 
0097     parent = devm_clk_get(dev, NULL);
0098     if (IS_ERR(parent))
0099         return ERR_CAST(parent);
0100 
0101     parent_name = __clk_get_name(parent);
0102 
0103     gate = devm_kzalloc(dev, sizeof(*gate), GFP_KERNEL);
0104     if (!gate)
0105         return ERR_PTR(-ENOMEM);
0106 
0107     init.name = info->name;
0108     if (info->flags & DA8XX_GATE_CLOCK_IS_DIV4P5)
0109         init.ops = &da8xx_cfgchip_div4p5_clk_ops;
0110     else
0111         init.ops = &da8xx_cfgchip_gate_clk_ops;
0112     init.parent_names = &parent_name;
0113     init.num_parents = 1;
0114     init.flags = 0;
0115 
0116     gate->hw.init = &init;
0117     gate->regmap = regmap;
0118     gate->reg = info->cfgchip;
0119     gate->mask = info->bit;
0120 
0121     ret = devm_clk_hw_register(dev, &gate->hw);
0122     if (ret < 0)
0123         return ERR_PTR(ret);
0124 
0125     return gate;
0126 }
0127 
0128 static const struct da8xx_cfgchip_gate_clk_info da8xx_tbclksync_info __initconst = {
0129     .name = "ehrpwm_tbclk",
0130     .cfgchip = CFGCHIP(1),
0131     .bit = CFGCHIP1_TBCLKSYNC,
0132 };
0133 
0134 static int __init da8xx_cfgchip_register_tbclk(struct device *dev,
0135                            struct regmap *regmap)
0136 {
0137     struct da8xx_cfgchip_gate_clk *gate;
0138 
0139     gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_tbclksync_info,
0140                            regmap);
0141     if (IS_ERR(gate))
0142         return PTR_ERR(gate);
0143 
0144     clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.0");
0145     clk_hw_register_clkdev(&gate->hw, "tbclk", "ehrpwm.1");
0146 
0147     return 0;
0148 }
0149 
0150 static const struct da8xx_cfgchip_gate_clk_info da8xx_div4p5ena_info __initconst = {
0151     .name = "div4.5",
0152     .cfgchip = CFGCHIP(3),
0153     .bit = CFGCHIP3_DIV45PENA,
0154     .flags = DA8XX_GATE_CLOCK_IS_DIV4P5,
0155 };
0156 
0157 static int __init da8xx_cfgchip_register_div4p5(struct device *dev,
0158                         struct regmap *regmap)
0159 {
0160     struct da8xx_cfgchip_gate_clk *gate;
0161 
0162     gate = da8xx_cfgchip_gate_clk_register(dev, &da8xx_div4p5ena_info, regmap);
0163 
0164     return PTR_ERR_OR_ZERO(gate);
0165 }
0166 
0167 static int __init
0168 of_da8xx_cfgchip_gate_clk_init(struct device *dev,
0169                    const struct da8xx_cfgchip_gate_clk_info *info,
0170                    struct regmap *regmap)
0171 {
0172     struct da8xx_cfgchip_gate_clk *gate;
0173 
0174     gate = da8xx_cfgchip_gate_clk_register(dev, info, regmap);
0175     if (IS_ERR(gate))
0176         return PTR_ERR(gate);
0177 
0178     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, gate);
0179 }
0180 
0181 static int __init of_da8xx_tbclksync_init(struct device *dev,
0182                       struct regmap *regmap)
0183 {
0184     return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_tbclksync_info, regmap);
0185 }
0186 
0187 static int __init of_da8xx_div4p5ena_init(struct device *dev,
0188                       struct regmap *regmap)
0189 {
0190     return of_da8xx_cfgchip_gate_clk_init(dev, &da8xx_div4p5ena_info, regmap);
0191 }
0192 
0193 /* --- MUX clocks --- */
0194 
0195 struct da8xx_cfgchip_mux_clk_info {
0196     const char *name;
0197     const char *parent0;
0198     const char *parent1;
0199     u32 cfgchip;
0200     u32 bit;
0201 };
0202 
0203 struct da8xx_cfgchip_mux_clk {
0204     struct clk_hw hw;
0205     struct regmap *regmap;
0206     u32 reg;
0207     u32 mask;
0208 };
0209 
0210 #define to_da8xx_cfgchip_mux_clk(_hw) \
0211     container_of((_hw), struct da8xx_cfgchip_mux_clk, hw)
0212 
0213 static int da8xx_cfgchip_mux_clk_set_parent(struct clk_hw *hw, u8 index)
0214 {
0215     struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
0216     unsigned int val = index ? clk->mask : 0;
0217 
0218     return regmap_write_bits(clk->regmap, clk->reg, clk->mask, val);
0219 }
0220 
0221 static u8 da8xx_cfgchip_mux_clk_get_parent(struct clk_hw *hw)
0222 {
0223     struct da8xx_cfgchip_mux_clk *clk = to_da8xx_cfgchip_mux_clk(hw);
0224     unsigned int val;
0225 
0226     regmap_read(clk->regmap, clk->reg, &val);
0227 
0228     return (val & clk->mask) ? 1 : 0;
0229 }
0230 
0231 static const struct clk_ops da8xx_cfgchip_mux_clk_ops = {
0232     .set_parent = da8xx_cfgchip_mux_clk_set_parent,
0233     .get_parent = da8xx_cfgchip_mux_clk_get_parent,
0234 };
0235 
0236 static struct da8xx_cfgchip_mux_clk * __init
0237 da8xx_cfgchip_mux_clk_register(struct device *dev,
0238                    const struct da8xx_cfgchip_mux_clk_info *info,
0239                    struct regmap *regmap)
0240 {
0241     const char * const parent_names[] = { info->parent0, info->parent1 };
0242     struct da8xx_cfgchip_mux_clk *mux;
0243     struct clk_init_data init;
0244     int ret;
0245 
0246     mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
0247     if (!mux)
0248         return ERR_PTR(-ENOMEM);
0249 
0250     init.name = info->name;
0251     init.ops = &da8xx_cfgchip_mux_clk_ops;
0252     init.parent_names = parent_names;
0253     init.num_parents = 2;
0254     init.flags = 0;
0255 
0256     mux->hw.init = &init;
0257     mux->regmap = regmap;
0258     mux->reg = info->cfgchip;
0259     mux->mask = info->bit;
0260 
0261     ret = devm_clk_hw_register(dev, &mux->hw);
0262     if (ret < 0)
0263         return ERR_PTR(ret);
0264 
0265     return mux;
0266 }
0267 
0268 static const struct da8xx_cfgchip_mux_clk_info da850_async1_info __initconst = {
0269     .name = "async1",
0270     .parent0 = "pll0_sysclk3",
0271     .parent1 = "div4.5",
0272     .cfgchip = CFGCHIP(3),
0273     .bit = CFGCHIP3_EMA_CLKSRC,
0274 };
0275 
0276 static int __init da8xx_cfgchip_register_async1(struct device *dev,
0277                         struct regmap *regmap)
0278 {
0279     struct da8xx_cfgchip_mux_clk *mux;
0280 
0281     mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async1_info, regmap);
0282     if (IS_ERR(mux))
0283         return PTR_ERR(mux);
0284 
0285     clk_hw_register_clkdev(&mux->hw, "async1", "da850-psc0");
0286 
0287     return 0;
0288 }
0289 
0290 static const struct da8xx_cfgchip_mux_clk_info da850_async3_info __initconst = {
0291     .name = "async3",
0292     .parent0 = "pll0_sysclk2",
0293     .parent1 = "pll1_sysclk2",
0294     .cfgchip = CFGCHIP(3),
0295     .bit = CFGCHIP3_ASYNC3_CLKSRC,
0296 };
0297 
0298 static int __init da850_cfgchip_register_async3(struct device *dev,
0299                         struct regmap *regmap)
0300 {
0301     struct da8xx_cfgchip_mux_clk *mux;
0302     struct clk_hw *parent;
0303 
0304     mux = da8xx_cfgchip_mux_clk_register(dev, &da850_async3_info, regmap);
0305     if (IS_ERR(mux))
0306         return PTR_ERR(mux);
0307 
0308     clk_hw_register_clkdev(&mux->hw, "async3", "da850-psc1");
0309 
0310     /* pll1_sysclk2 is not affected by CPU scaling, so use it for async3 */
0311     parent = clk_hw_get_parent_by_index(&mux->hw, 1);
0312     if (parent)
0313         clk_set_parent(mux->hw.clk, parent->clk);
0314     else
0315         dev_warn(dev, "Failed to find async3 parent clock\n");
0316 
0317     return 0;
0318 }
0319 
0320 static int __init
0321 of_da8xx_cfgchip_init_mux_clock(struct device *dev,
0322                 const struct da8xx_cfgchip_mux_clk_info *info,
0323                 struct regmap *regmap)
0324 {
0325     struct da8xx_cfgchip_mux_clk *mux;
0326 
0327     mux = da8xx_cfgchip_mux_clk_register(dev, info, regmap);
0328     if (IS_ERR(mux))
0329         return PTR_ERR(mux);
0330 
0331     return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mux->hw);
0332 }
0333 
0334 static int __init of_da850_async1_init(struct device *dev, struct regmap *regmap)
0335 {
0336     return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async1_info, regmap);
0337 }
0338 
0339 static int __init of_da850_async3_init(struct device *dev, struct regmap *regmap)
0340 {
0341     return of_da8xx_cfgchip_init_mux_clock(dev, &da850_async3_info, regmap);
0342 }
0343 
0344 /* --- USB 2.0 PHY clock --- */
0345 
0346 struct da8xx_usb0_clk48 {
0347     struct clk_hw hw;
0348     struct clk *fck;
0349     struct regmap *regmap;
0350 };
0351 
0352 #define to_da8xx_usb0_clk48(_hw) \
0353     container_of((_hw), struct da8xx_usb0_clk48, hw)
0354 
0355 static int da8xx_usb0_clk48_prepare(struct clk_hw *hw)
0356 {
0357     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0358 
0359     /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0
0360      * PHY clock enable, but since clk_prepare() can't be called in an
0361      * atomic context (i.e. in clk_enable()), we have to prepare it here.
0362      */
0363     return clk_prepare(usb0->fck);
0364 }
0365 
0366 static void da8xx_usb0_clk48_unprepare(struct clk_hw *hw)
0367 {
0368     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0369 
0370     clk_unprepare(usb0->fck);
0371 }
0372 
0373 static int da8xx_usb0_clk48_enable(struct clk_hw *hw)
0374 {
0375     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0376     unsigned int mask, val;
0377     int ret;
0378 
0379     /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled
0380      * temporaily. It can be turned back off once the PLL is locked.
0381      */
0382     clk_enable(usb0->fck);
0383 
0384     /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
0385      * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used.
0386      */
0387     mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON;
0388     val = CFGCHIP2_PHY_PLLON;
0389 
0390     regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
0391     ret = regmap_read_poll_timeout(usb0->regmap, CFGCHIP(2), val,
0392                        val & CFGCHIP2_PHYCLKGD, 0, 500000);
0393 
0394     clk_disable(usb0->fck);
0395 
0396     return ret;
0397 }
0398 
0399 static void da8xx_usb0_clk48_disable(struct clk_hw *hw)
0400 {
0401     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0402     unsigned int val;
0403 
0404     val = CFGCHIP2_PHYPWRDN;
0405     regmap_write_bits(usb0->regmap, CFGCHIP(2), val, val);
0406 }
0407 
0408 static int da8xx_usb0_clk48_is_enabled(struct clk_hw *hw)
0409 {
0410     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0411     unsigned int val;
0412 
0413     regmap_read(usb0->regmap, CFGCHIP(2), &val);
0414 
0415     return !!(val & CFGCHIP2_PHYCLKGD);
0416 }
0417 
0418 static unsigned long da8xx_usb0_clk48_recalc_rate(struct clk_hw *hw,
0419                           unsigned long parent_rate)
0420 {
0421     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0422     unsigned int mask, val;
0423 
0424     /* The parent clock rate must be one of the following */
0425     mask = CFGCHIP2_REFFREQ_MASK;
0426     switch (parent_rate) {
0427     case 12000000:
0428         val = CFGCHIP2_REFFREQ_12MHZ;
0429         break;
0430     case 13000000:
0431         val = CFGCHIP2_REFFREQ_13MHZ;
0432         break;
0433     case 19200000:
0434         val = CFGCHIP2_REFFREQ_19_2MHZ;
0435         break;
0436     case 20000000:
0437         val = CFGCHIP2_REFFREQ_20MHZ;
0438         break;
0439     case 24000000:
0440         val = CFGCHIP2_REFFREQ_24MHZ;
0441         break;
0442     case 26000000:
0443         val = CFGCHIP2_REFFREQ_26MHZ;
0444         break;
0445     case 38400000:
0446         val = CFGCHIP2_REFFREQ_38_4MHZ;
0447         break;
0448     case 40000000:
0449         val = CFGCHIP2_REFFREQ_40MHZ;
0450         break;
0451     case 48000000:
0452         val = CFGCHIP2_REFFREQ_48MHZ;
0453         break;
0454     default:
0455         return 0;
0456     }
0457 
0458     regmap_write_bits(usb0->regmap, CFGCHIP(2), mask, val);
0459 
0460     /* USB 2.0 PLL always supplies 48MHz */
0461     return 48000000;
0462 }
0463 
0464 static long da8xx_usb0_clk48_round_rate(struct clk_hw *hw, unsigned long rate,
0465                     unsigned long *parent_rate)
0466 {
0467     return 48000000;
0468 }
0469 
0470 static int da8xx_usb0_clk48_set_parent(struct clk_hw *hw, u8 index)
0471 {
0472     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0473 
0474     return regmap_write_bits(usb0->regmap, CFGCHIP(2),
0475                  CFGCHIP2_USB2PHYCLKMUX,
0476                  index ? CFGCHIP2_USB2PHYCLKMUX : 0);
0477 }
0478 
0479 static u8 da8xx_usb0_clk48_get_parent(struct clk_hw *hw)
0480 {
0481     struct da8xx_usb0_clk48 *usb0 = to_da8xx_usb0_clk48(hw);
0482     unsigned int val;
0483 
0484     regmap_read(usb0->regmap, CFGCHIP(2), &val);
0485 
0486     return (val & CFGCHIP2_USB2PHYCLKMUX) ? 1 : 0;
0487 }
0488 
0489 static const struct clk_ops da8xx_usb0_clk48_ops = {
0490     .prepare    = da8xx_usb0_clk48_prepare,
0491     .unprepare  = da8xx_usb0_clk48_unprepare,
0492     .enable     = da8xx_usb0_clk48_enable,
0493     .disable    = da8xx_usb0_clk48_disable,
0494     .is_enabled = da8xx_usb0_clk48_is_enabled,
0495     .recalc_rate    = da8xx_usb0_clk48_recalc_rate,
0496     .round_rate = da8xx_usb0_clk48_round_rate,
0497     .set_parent = da8xx_usb0_clk48_set_parent,
0498     .get_parent = da8xx_usb0_clk48_get_parent,
0499 };
0500 
0501 static struct da8xx_usb0_clk48 *
0502 da8xx_cfgchip_register_usb0_clk48(struct device *dev,
0503                   struct regmap *regmap)
0504 {
0505     const char * const parent_names[] = { "usb_refclkin", "pll0_auxclk" };
0506     struct clk *fck_clk;
0507     struct da8xx_usb0_clk48 *usb0;
0508     struct clk_init_data init;
0509     int ret;
0510 
0511     fck_clk = devm_clk_get(dev, "fck");
0512     if (IS_ERR(fck_clk)) {
0513         if (PTR_ERR(fck_clk) != -EPROBE_DEFER)
0514             dev_err(dev, "Missing fck clock\n");
0515         return ERR_CAST(fck_clk);
0516     }
0517 
0518     usb0 = devm_kzalloc(dev, sizeof(*usb0), GFP_KERNEL);
0519     if (!usb0)
0520         return ERR_PTR(-ENOMEM);
0521 
0522     init.name = "usb0_clk48";
0523     init.ops = &da8xx_usb0_clk48_ops;
0524     init.parent_names = parent_names;
0525     init.num_parents = 2;
0526 
0527     usb0->hw.init = &init;
0528     usb0->fck = fck_clk;
0529     usb0->regmap = regmap;
0530 
0531     ret = devm_clk_hw_register(dev, &usb0->hw);
0532     if (ret < 0)
0533         return ERR_PTR(ret);
0534 
0535     return usb0;
0536 }
0537 
0538 /* --- USB 1.1 PHY clock --- */
0539 
0540 struct da8xx_usb1_clk48 {
0541     struct clk_hw hw;
0542     struct regmap *regmap;
0543 };
0544 
0545 #define to_da8xx_usb1_clk48(_hw) \
0546     container_of((_hw), struct da8xx_usb1_clk48, hw)
0547 
0548 static int da8xx_usb1_clk48_set_parent(struct clk_hw *hw, u8 index)
0549 {
0550     struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
0551 
0552     return regmap_write_bits(usb1->regmap, CFGCHIP(2),
0553                  CFGCHIP2_USB1PHYCLKMUX,
0554                  index ? CFGCHIP2_USB1PHYCLKMUX : 0);
0555 }
0556 
0557 static u8 da8xx_usb1_clk48_get_parent(struct clk_hw *hw)
0558 {
0559     struct da8xx_usb1_clk48 *usb1 = to_da8xx_usb1_clk48(hw);
0560     unsigned int val;
0561 
0562     regmap_read(usb1->regmap, CFGCHIP(2), &val);
0563 
0564     return (val & CFGCHIP2_USB1PHYCLKMUX) ? 1 : 0;
0565 }
0566 
0567 static const struct clk_ops da8xx_usb1_clk48_ops = {
0568     .set_parent = da8xx_usb1_clk48_set_parent,
0569     .get_parent = da8xx_usb1_clk48_get_parent,
0570 };
0571 
0572 /**
0573  * da8xx_cfgchip_register_usb1_clk48 - Register a new USB 1.1 PHY clock
0574  * @dev: The device
0575  * @regmap: The CFGCHIP regmap
0576  */
0577 static struct da8xx_usb1_clk48 *
0578 da8xx_cfgchip_register_usb1_clk48(struct device *dev,
0579                   struct regmap *regmap)
0580 {
0581     const char * const parent_names[] = { "usb0_clk48", "usb_refclkin" };
0582     struct da8xx_usb1_clk48 *usb1;
0583     struct clk_init_data init;
0584     int ret;
0585 
0586     usb1 = devm_kzalloc(dev, sizeof(*usb1), GFP_KERNEL);
0587     if (!usb1)
0588         return ERR_PTR(-ENOMEM);
0589 
0590     init.name = "usb1_clk48";
0591     init.ops = &da8xx_usb1_clk48_ops;
0592     init.parent_names = parent_names;
0593     init.num_parents = 2;
0594 
0595     usb1->hw.init = &init;
0596     usb1->regmap = regmap;
0597 
0598     ret = devm_clk_hw_register(dev, &usb1->hw);
0599     if (ret < 0)
0600         return ERR_PTR(ret);
0601 
0602     return usb1;
0603 }
0604 
0605 static int da8xx_cfgchip_register_usb_phy_clk(struct device *dev,
0606                           struct regmap *regmap)
0607 {
0608     struct da8xx_usb0_clk48 *usb0;
0609     struct da8xx_usb1_clk48 *usb1;
0610     struct clk_hw *parent;
0611 
0612     usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
0613     if (IS_ERR(usb0))
0614         return PTR_ERR(usb0);
0615 
0616     /*
0617      * All existing boards use pll0_auxclk as the parent and new boards
0618      * should use device tree, so hard-coding the value (1) here.
0619      */
0620     parent = clk_hw_get_parent_by_index(&usb0->hw, 1);
0621     if (parent)
0622         clk_set_parent(usb0->hw.clk, parent->clk);
0623     else
0624         dev_warn(dev, "Failed to find usb0 parent clock\n");
0625 
0626     usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
0627     if (IS_ERR(usb1))
0628         return PTR_ERR(usb1);
0629 
0630     /*
0631      * All existing boards use usb0_clk48 as the parent and new boards
0632      * should use device tree, so hard-coding the value (0) here.
0633      */
0634     parent = clk_hw_get_parent_by_index(&usb1->hw, 0);
0635     if (parent)
0636         clk_set_parent(usb1->hw.clk, parent->clk);
0637     else
0638         dev_warn(dev, "Failed to find usb1 parent clock\n");
0639 
0640     clk_hw_register_clkdev(&usb0->hw, "usb0_clk48", "da8xx-usb-phy");
0641     clk_hw_register_clkdev(&usb1->hw, "usb1_clk48", "da8xx-usb-phy");
0642 
0643     return 0;
0644 }
0645 
0646 static int of_da8xx_usb_phy_clk_init(struct device *dev, struct regmap *regmap)
0647 {
0648     struct clk_hw_onecell_data *clk_data;
0649     struct da8xx_usb0_clk48 *usb0;
0650     struct da8xx_usb1_clk48 *usb1;
0651 
0652     clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, 2),
0653                 GFP_KERNEL);
0654     if (!clk_data)
0655         return -ENOMEM;
0656 
0657     clk_data->num = 2;
0658 
0659     usb0 = da8xx_cfgchip_register_usb0_clk48(dev, regmap);
0660     if (IS_ERR(usb0)) {
0661         if (PTR_ERR(usb0) == -EPROBE_DEFER)
0662             return -EPROBE_DEFER;
0663 
0664         dev_warn(dev, "Failed to register usb0_clk48 (%ld)\n",
0665              PTR_ERR(usb0));
0666 
0667         clk_data->hws[0] = ERR_PTR(-ENOENT);
0668     } else {
0669         clk_data->hws[0] = &usb0->hw;
0670     }
0671 
0672     usb1 = da8xx_cfgchip_register_usb1_clk48(dev, regmap);
0673     if (IS_ERR(usb1)) {
0674         if (PTR_ERR(usb1) == -EPROBE_DEFER)
0675             return -EPROBE_DEFER;
0676 
0677         dev_warn(dev, "Failed to register usb1_clk48 (%ld)\n",
0678              PTR_ERR(usb1));
0679 
0680         clk_data->hws[1] = ERR_PTR(-ENOENT);
0681     } else {
0682         clk_data->hws[1] = &usb1->hw;
0683     }
0684 
0685     return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data);
0686 }
0687 
0688 /* --- platform device --- */
0689 
0690 static const struct of_device_id da8xx_cfgchip_of_match[] = {
0691     {
0692         .compatible = "ti,da830-tbclksync",
0693         .data = of_da8xx_tbclksync_init,
0694     },
0695     {
0696         .compatible = "ti,da830-div4p5ena",
0697         .data = of_da8xx_div4p5ena_init,
0698     },
0699     {
0700         .compatible = "ti,da850-async1-clksrc",
0701         .data = of_da850_async1_init,
0702     },
0703     {
0704         .compatible = "ti,da850-async3-clksrc",
0705         .data = of_da850_async3_init,
0706     },
0707     {
0708         .compatible = "ti,da830-usb-phy-clocks",
0709         .data = of_da8xx_usb_phy_clk_init,
0710     },
0711     { }
0712 };
0713 
0714 static const struct platform_device_id da8xx_cfgchip_id_table[] = {
0715     {
0716         .name = "da830-tbclksync",
0717         .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_tbclk,
0718     },
0719     {
0720         .name = "da830-div4p5ena",
0721         .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_div4p5,
0722     },
0723     {
0724         .name = "da850-async1-clksrc",
0725         .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_async1,
0726     },
0727     {
0728         .name = "da850-async3-clksrc",
0729         .driver_data = (kernel_ulong_t)da850_cfgchip_register_async3,
0730     },
0731     {
0732         .name = "da830-usb-phy-clks",
0733         .driver_data = (kernel_ulong_t)da8xx_cfgchip_register_usb_phy_clk,
0734     },
0735     { }
0736 };
0737 
0738 typedef int (*da8xx_cfgchip_init)(struct device *dev, struct regmap *regmap);
0739 
0740 static int da8xx_cfgchip_probe(struct platform_device *pdev)
0741 {
0742     struct device *dev = &pdev->dev;
0743     struct da8xx_cfgchip_clk_platform_data *pdata = dev->platform_data;
0744     const struct of_device_id *of_id;
0745     da8xx_cfgchip_init clk_init = NULL;
0746     struct regmap *regmap = NULL;
0747 
0748     of_id = of_match_device(da8xx_cfgchip_of_match, dev);
0749     if (of_id) {
0750         struct device_node *parent;
0751 
0752         clk_init = of_id->data;
0753         parent = of_get_parent(dev->of_node);
0754         regmap = syscon_node_to_regmap(parent);
0755         of_node_put(parent);
0756     } else if (pdev->id_entry && pdata) {
0757         clk_init = (void *)pdev->id_entry->driver_data;
0758         regmap = pdata->cfgchip;
0759     }
0760 
0761     if (!clk_init) {
0762         dev_err(dev, "unable to find driver data\n");
0763         return -EINVAL;
0764     }
0765 
0766     if (IS_ERR_OR_NULL(regmap)) {
0767         dev_err(dev, "no regmap for CFGCHIP syscon\n");
0768         return regmap ? PTR_ERR(regmap) : -ENOENT;
0769     }
0770 
0771     return clk_init(dev, regmap);
0772 }
0773 
0774 static struct platform_driver da8xx_cfgchip_driver = {
0775     .probe      = da8xx_cfgchip_probe,
0776     .driver     = {
0777         .name       = "da8xx-cfgchip-clk",
0778         .of_match_table = da8xx_cfgchip_of_match,
0779     },
0780     .id_table   = da8xx_cfgchip_id_table,
0781 };
0782 
0783 static int __init da8xx_cfgchip_driver_init(void)
0784 {
0785     return platform_driver_register(&da8xx_cfgchip_driver);
0786 }
0787 
0788 /* has to be postcore_initcall because PSC devices depend on the async3 clock */
0789 postcore_initcall(da8xx_cfgchip_driver_init);
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