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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Clock implementation for VIA/Wondermedia SoC's
0004  * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
0005  */
0006 
0007 #include <linux/io.h>
0008 #include <linux/of.h>
0009 #include <linux/of_address.h>
0010 #include <linux/slab.h>
0011 #include <linux/bitops.h>
0012 #include <linux/clkdev.h>
0013 #include <linux/clk-provider.h>
0014 
0015 #define LEGACY_PMC_BASE     0xD8130000
0016 
0017 /* All clocks share the same lock as none can be changed concurrently */
0018 static DEFINE_SPINLOCK(_lock);
0019 
0020 struct clk_device {
0021     struct clk_hw   hw;
0022     void __iomem    *div_reg;
0023     unsigned int    div_mask;
0024     void __iomem    *en_reg;
0025     int     en_bit;
0026     spinlock_t  *lock;
0027 };
0028 
0029 /*
0030  * Add new PLL_TYPE_x definitions here as required. Use the first known model
0031  * to support the new type as the name.
0032  * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
0033  * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
0034  */
0035 
0036 #define PLL_TYPE_VT8500     0
0037 #define PLL_TYPE_WM8650     1
0038 #define PLL_TYPE_WM8750     2
0039 #define PLL_TYPE_WM8850     3
0040 
0041 struct clk_pll {
0042     struct clk_hw   hw;
0043     void __iomem    *reg;
0044     spinlock_t  *lock;
0045     int     type;
0046 };
0047 
0048 static void __iomem *pmc_base;
0049 
0050 static __init void vtwm_set_pmc_base(void)
0051 {
0052     struct device_node *np =
0053         of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
0054 
0055     if (np)
0056         pmc_base = of_iomap(np, 0);
0057     else
0058         pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
0059     of_node_put(np);
0060 
0061     if (!pmc_base)
0062         pr_err("%s:of_iomap(pmc) failed\n", __func__);
0063 }
0064 
0065 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
0066 
0067 #define VT8500_PMC_BUSY_MASK        0x18
0068 
0069 static void vt8500_pmc_wait_busy(void)
0070 {
0071     while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
0072         cpu_relax();
0073 }
0074 
0075 static int vt8500_dclk_enable(struct clk_hw *hw)
0076 {
0077     struct clk_device *cdev = to_clk_device(hw);
0078     u32 en_val;
0079     unsigned long flags = 0;
0080 
0081     spin_lock_irqsave(cdev->lock, flags);
0082 
0083     en_val = readl(cdev->en_reg);
0084     en_val |= BIT(cdev->en_bit);
0085     writel(en_val, cdev->en_reg);
0086 
0087     spin_unlock_irqrestore(cdev->lock, flags);
0088     return 0;
0089 }
0090 
0091 static void vt8500_dclk_disable(struct clk_hw *hw)
0092 {
0093     struct clk_device *cdev = to_clk_device(hw);
0094     u32 en_val;
0095     unsigned long flags = 0;
0096 
0097     spin_lock_irqsave(cdev->lock, flags);
0098 
0099     en_val = readl(cdev->en_reg);
0100     en_val &= ~BIT(cdev->en_bit);
0101     writel(en_val, cdev->en_reg);
0102 
0103     spin_unlock_irqrestore(cdev->lock, flags);
0104 }
0105 
0106 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
0107 {
0108     struct clk_device *cdev = to_clk_device(hw);
0109     u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
0110 
0111     return en_val ? 1 : 0;
0112 }
0113 
0114 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
0115                 unsigned long parent_rate)
0116 {
0117     struct clk_device *cdev = to_clk_device(hw);
0118     u32 div = readl(cdev->div_reg) & cdev->div_mask;
0119 
0120     /* Special case for SDMMC devices */
0121     if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
0122         div = 64 * (div & 0x1f);
0123 
0124     /* div == 0 is actually the highest divisor */
0125     if (div == 0)
0126         div = (cdev->div_mask + 1);
0127 
0128     return parent_rate / div;
0129 }
0130 
0131 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
0132                 unsigned long *prate)
0133 {
0134     struct clk_device *cdev = to_clk_device(hw);
0135     u32 divisor;
0136 
0137     if (rate == 0)
0138         return 0;
0139 
0140     divisor = *prate / rate;
0141 
0142     /* If prate / rate would be decimal, incr the divisor */
0143     if (rate * divisor < *prate)
0144         divisor++;
0145 
0146     /*
0147      * If this is a request for SDMMC we have to adjust the divisor
0148      * when >31 to use the fixed predivisor
0149      */
0150     if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
0151         divisor = 64 * ((divisor / 64) + 1);
0152     }
0153 
0154     return *prate / divisor;
0155 }
0156 
0157 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
0158                 unsigned long parent_rate)
0159 {
0160     struct clk_device *cdev = to_clk_device(hw);
0161     u32 divisor;
0162     unsigned long flags = 0;
0163 
0164     if (rate == 0)
0165         return 0;
0166 
0167     divisor =  parent_rate / rate;
0168 
0169     if (divisor == cdev->div_mask + 1)
0170         divisor = 0;
0171 
0172     /* SDMMC mask may need to be corrected before testing if its valid */
0173     if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
0174         /*
0175          * Bit 5 is a fixed /64 predivisor. If the requested divisor
0176          * is >31 then correct for the fixed divisor being required.
0177          */
0178         divisor = 0x20 + (divisor / 64);
0179     }
0180 
0181     if (divisor > cdev->div_mask) {
0182         pr_err("%s: invalid divisor for clock\n", __func__);
0183         return -EINVAL;
0184     }
0185 
0186     spin_lock_irqsave(cdev->lock, flags);
0187 
0188     vt8500_pmc_wait_busy();
0189     writel(divisor, cdev->div_reg);
0190     vt8500_pmc_wait_busy();
0191 
0192     spin_unlock_irqrestore(cdev->lock, flags);
0193 
0194     return 0;
0195 }
0196 
0197 
0198 static const struct clk_ops vt8500_gated_clk_ops = {
0199     .enable = vt8500_dclk_enable,
0200     .disable = vt8500_dclk_disable,
0201     .is_enabled = vt8500_dclk_is_enabled,
0202 };
0203 
0204 static const struct clk_ops vt8500_divisor_clk_ops = {
0205     .round_rate = vt8500_dclk_round_rate,
0206     .set_rate = vt8500_dclk_set_rate,
0207     .recalc_rate = vt8500_dclk_recalc_rate,
0208 };
0209 
0210 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
0211     .enable = vt8500_dclk_enable,
0212     .disable = vt8500_dclk_disable,
0213     .is_enabled = vt8500_dclk_is_enabled,
0214     .round_rate = vt8500_dclk_round_rate,
0215     .set_rate = vt8500_dclk_set_rate,
0216     .recalc_rate = vt8500_dclk_recalc_rate,
0217 };
0218 
0219 #define CLK_INIT_GATED          BIT(0)
0220 #define CLK_INIT_DIVISOR        BIT(1)
0221 #define CLK_INIT_GATED_DIVISOR      (CLK_INIT_DIVISOR | CLK_INIT_GATED)
0222 
0223 static __init void vtwm_device_clk_init(struct device_node *node)
0224 {
0225     u32 en_reg, div_reg;
0226     struct clk_hw *hw;
0227     struct clk_device *dev_clk;
0228     const char *clk_name = node->name;
0229     const char *parent_name;
0230     struct clk_init_data init;
0231     int rc;
0232     int clk_init_flags = 0;
0233 
0234     if (!pmc_base)
0235         vtwm_set_pmc_base();
0236 
0237     dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
0238     if (WARN_ON(!dev_clk))
0239         return;
0240 
0241     dev_clk->lock = &_lock;
0242 
0243     rc = of_property_read_u32(node, "enable-reg", &en_reg);
0244     if (!rc) {
0245         dev_clk->en_reg = pmc_base + en_reg;
0246         rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
0247         if (rc) {
0248             pr_err("%s: enable-bit property required for gated clock\n",
0249                                 __func__);
0250             return;
0251         }
0252         clk_init_flags |= CLK_INIT_GATED;
0253     }
0254 
0255     rc = of_property_read_u32(node, "divisor-reg", &div_reg);
0256     if (!rc) {
0257         dev_clk->div_reg = pmc_base + div_reg;
0258         /*
0259          * use 0x1f as the default mask since it covers
0260          * almost all the clocks and reduces dts properties
0261          */
0262         dev_clk->div_mask = 0x1f;
0263 
0264         of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
0265         clk_init_flags |= CLK_INIT_DIVISOR;
0266     }
0267 
0268     of_property_read_string(node, "clock-output-names", &clk_name);
0269 
0270     switch (clk_init_flags) {
0271     case CLK_INIT_GATED:
0272         init.ops = &vt8500_gated_clk_ops;
0273         break;
0274     case CLK_INIT_DIVISOR:
0275         init.ops = &vt8500_divisor_clk_ops;
0276         break;
0277     case CLK_INIT_GATED_DIVISOR:
0278         init.ops = &vt8500_gated_divisor_clk_ops;
0279         break;
0280     default:
0281         pr_err("%s: Invalid clock description in device tree\n",
0282                                 __func__);
0283         kfree(dev_clk);
0284         return;
0285     }
0286 
0287     init.name = clk_name;
0288     init.flags = 0;
0289     parent_name = of_clk_get_parent_name(node, 0);
0290     init.parent_names = &parent_name;
0291     init.num_parents = 1;
0292 
0293     dev_clk->hw.init = &init;
0294 
0295     hw = &dev_clk->hw;
0296     rc = clk_hw_register(NULL, hw);
0297     if (WARN_ON(rc)) {
0298         kfree(dev_clk);
0299         return;
0300     }
0301     rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
0302     clk_hw_register_clkdev(hw, clk_name, NULL);
0303 }
0304 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
0305 
0306 /* PLL clock related functions */
0307 
0308 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
0309 
0310 /* Helper macros for PLL_VT8500 */
0311 #define VT8500_PLL_MUL(x)   ((x & 0x1F) << 1)
0312 #define VT8500_PLL_DIV(x)   ((x & 0x100) ? 1 : 2)
0313 
0314 #define VT8500_BITS_TO_FREQ(r, m, d)                    \
0315                 ((r / d) * m)
0316 
0317 #define VT8500_BITS_TO_VAL(m, d)                    \
0318                 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
0319 
0320 /* Helper macros for PLL_WM8650 */
0321 #define WM8650_PLL_MUL(x)   (x & 0x3FF)
0322 #define WM8650_PLL_DIV(x)   (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
0323 
0324 #define WM8650_BITS_TO_FREQ(r, m, d1, d2)               \
0325                 (r * m / (d1 * (1 << d2)))
0326 
0327 #define WM8650_BITS_TO_VAL(m, d1, d2)                   \
0328                 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
0329 
0330 /* Helper macros for PLL_WM8750 */
0331 #define WM8750_PLL_MUL(x)   (((x >> 16) & 0xFF) + 1)
0332 #define WM8750_PLL_DIV(x)   ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
0333 
0334 #define WM8750_BITS_TO_FREQ(r, m, d1, d2)               \
0335                 (r * (m+1) / ((d1+1) * (1 << d2)))
0336 
0337 #define WM8750_BITS_TO_VAL(f, m, d1, d2)                \
0338         ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
0339 
0340 /* Helper macros for PLL_WM8850 */
0341 #define WM8850_PLL_MUL(x)   ((((x >> 16) & 0x7F) + 1) * 2)
0342 #define WM8850_PLL_DIV(x)   ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
0343 
0344 #define WM8850_BITS_TO_FREQ(r, m, d1, d2)               \
0345                 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
0346 
0347 #define WM8850_BITS_TO_VAL(m, d1, d2)                   \
0348         ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
0349 
0350 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
0351                 u32 *multiplier, u32 *prediv)
0352 {
0353     unsigned long tclk;
0354 
0355     /* sanity check */
0356     if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
0357         pr_err("%s: requested rate out of range\n", __func__);
0358         *multiplier = 0;
0359         *prediv = 1;
0360         return -EINVAL;
0361     }
0362     if (rate <= parent_rate * 31)
0363         /* use the prediv to double the resolution */
0364         *prediv = 2;
0365     else
0366         *prediv = 1;
0367 
0368     *multiplier = rate / (parent_rate / *prediv);
0369     tclk = (parent_rate / *prediv) * *multiplier;
0370 
0371     if (tclk != rate)
0372         pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
0373                                 rate, tclk);
0374 
0375     return 0;
0376 }
0377 
0378 /*
0379  * M * parent [O1] => / P [O2] => / D [O3]
0380  * Where O1 is 900MHz...3GHz;
0381  * O2 is 600MHz >= (M * parent) / P >= 300MHz;
0382  * M is 36...120 [25MHz parent]; D is 1 or 2 or 4 or 8.
0383  * Possible ranges (O3):
0384  * D = 8: 37,5MHz...75MHz
0385  * D = 4: 75MHz...150MHz
0386  * D = 2: 150MHz...300MHz
0387  * D = 1: 300MHz...600MHz
0388  */
0389 static int wm8650_find_pll_bits(unsigned long rate,
0390     unsigned long parent_rate, u32 *multiplier, u32 *divisor1,
0391     u32 *divisor2)
0392 {
0393     unsigned long O1, min_err, rate_err;
0394 
0395     if (!parent_rate || (rate < 37500000) || (rate > 600000000))
0396         return -EINVAL;
0397 
0398     *divisor2 = rate <= 75000000 ? 3 : rate <= 150000000 ? 2 :
0399                        rate <= 300000000 ? 1 : 0;
0400     /*
0401      * Divisor P cannot be calculated. Test all divisors and find where M
0402      * will be as close as possible to the requested rate.
0403      */
0404     min_err = ULONG_MAX;
0405     for (*divisor1 = 5; *divisor1 >= 3; (*divisor1)--) {
0406         O1 = rate * *divisor1 * (1 << (*divisor2));
0407         rate_err = O1 % parent_rate;
0408         if (rate_err < min_err) {
0409             *multiplier = O1 / parent_rate;
0410             if (rate_err == 0)
0411                 return 0;
0412 
0413             min_err = rate_err;
0414         }
0415     }
0416 
0417     if ((*multiplier < 3) || (*multiplier > 1023))
0418         return -EINVAL;
0419 
0420     pr_warn("%s: rate error is %lu\n", __func__, min_err);
0421 
0422     return 0;
0423 }
0424 
0425 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
0426 {
0427     /* calculate frequency (MHz) after pre-divisor */
0428     u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
0429 
0430     if ((freq < 10) || (freq > 200))
0431         pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
0432                 __func__, freq);
0433 
0434     if (freq >= 166)
0435         return 7;
0436     else if (freq >= 104)
0437         return 6;
0438     else if (freq >= 65)
0439         return 5;
0440     else if (freq >= 42)
0441         return 4;
0442     else if (freq >= 26)
0443         return 3;
0444     else if (freq >= 16)
0445         return 2;
0446     else if (freq >= 10)
0447         return 1;
0448 
0449     return 0;
0450 }
0451 
0452 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
0453                 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
0454 {
0455     u32 mul;
0456     int div1, div2;
0457     unsigned long tclk, rate_err, best_err;
0458 
0459     best_err = (unsigned long)-1;
0460 
0461     /* Find the closest match (lower or equal to requested) */
0462     for (div1 = 1; div1 >= 0; div1--)
0463         for (div2 = 7; div2 >= 0; div2--)
0464             for (mul = 0; mul <= 255; mul++) {
0465                 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
0466                 if (tclk > rate)
0467                     continue;
0468                 /* error will always be +ve */
0469                 rate_err = rate - tclk;
0470                 if (rate_err == 0) {
0471                     *filter = wm8750_get_filter(parent_rate, div1);
0472                     *multiplier = mul;
0473                     *divisor1 = div1;
0474                     *divisor2 = div2;
0475                     return 0;
0476                 }
0477 
0478                 if (rate_err < best_err) {
0479                     best_err = rate_err;
0480                     *multiplier = mul;
0481                     *divisor1 = div1;
0482                     *divisor2 = div2;
0483                 }
0484             }
0485 
0486     if (best_err == (unsigned long)-1) {
0487         pr_warn("%s: impossible rate %lu\n", __func__, rate);
0488         return -EINVAL;
0489     }
0490 
0491     /* if we got here, it wasn't an exact match */
0492     pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
0493                             rate - best_err);
0494 
0495     *filter = wm8750_get_filter(parent_rate, *divisor1);
0496 
0497     return 0;
0498 }
0499 
0500 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
0501                 u32 *multiplier, u32 *divisor1, u32 *divisor2)
0502 {
0503     u32 mul;
0504     int div1, div2;
0505     unsigned long tclk, rate_err, best_err;
0506 
0507     best_err = (unsigned long)-1;
0508 
0509     /* Find the closest match (lower or equal to requested) */
0510     for (div1 = 1; div1 >= 0; div1--)
0511         for (div2 = 3; div2 >= 0; div2--)
0512             for (mul = 0; mul <= 127; mul++) {
0513                 tclk = parent_rate * ((mul + 1) * 2) /
0514                         ((div1 + 1) * (1 << div2));
0515                 if (tclk > rate)
0516                     continue;
0517                 /* error will always be +ve */
0518                 rate_err = rate - tclk;
0519                 if (rate_err == 0) {
0520                     *multiplier = mul;
0521                     *divisor1 = div1;
0522                     *divisor2 = div2;
0523                     return 0;
0524                 }
0525 
0526                 if (rate_err < best_err) {
0527                     best_err = rate_err;
0528                     *multiplier = mul;
0529                     *divisor1 = div1;
0530                     *divisor2 = div2;
0531                 }
0532             }
0533 
0534     if (best_err == (unsigned long)-1) {
0535         pr_warn("%s: impossible rate %lu\n", __func__, rate);
0536         return -EINVAL;
0537     }
0538 
0539     /* if we got here, it wasn't an exact match */
0540     pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
0541                             rate - best_err);
0542 
0543     return 0;
0544 }
0545 
0546 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
0547                 unsigned long parent_rate)
0548 {
0549     struct clk_pll *pll = to_clk_pll(hw);
0550     u32 filter, mul, div1, div2;
0551     u32 pll_val;
0552     unsigned long flags = 0;
0553     int ret;
0554 
0555     /* sanity check */
0556 
0557     switch (pll->type) {
0558     case PLL_TYPE_VT8500:
0559         ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
0560         if (!ret)
0561             pll_val = VT8500_BITS_TO_VAL(mul, div1);
0562         break;
0563     case PLL_TYPE_WM8650:
0564         ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
0565         if (!ret)
0566             pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
0567         break;
0568     case PLL_TYPE_WM8750:
0569         ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
0570         if (!ret)
0571             pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
0572         break;
0573     case PLL_TYPE_WM8850:
0574         ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
0575         if (!ret)
0576             pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
0577         break;
0578     default:
0579         pr_err("%s: invalid pll type\n", __func__);
0580         ret = -EINVAL;
0581     }
0582 
0583     if (ret)
0584         return ret;
0585 
0586     spin_lock_irqsave(pll->lock, flags);
0587 
0588     vt8500_pmc_wait_busy();
0589     writel(pll_val, pll->reg);
0590     vt8500_pmc_wait_busy();
0591 
0592     spin_unlock_irqrestore(pll->lock, flags);
0593 
0594     return 0;
0595 }
0596 
0597 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
0598                 unsigned long *prate)
0599 {
0600     struct clk_pll *pll = to_clk_pll(hw);
0601     u32 filter, mul, div1, div2;
0602     long round_rate;
0603     int ret;
0604 
0605     switch (pll->type) {
0606     case PLL_TYPE_VT8500:
0607         ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1);
0608         if (!ret)
0609             round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
0610         break;
0611     case PLL_TYPE_WM8650:
0612         ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
0613         if (!ret)
0614             round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
0615         break;
0616     case PLL_TYPE_WM8750:
0617         ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
0618         if (!ret)
0619             round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
0620         break;
0621     case PLL_TYPE_WM8850:
0622         ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
0623         if (!ret)
0624             round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
0625         break;
0626     default:
0627         ret = -EINVAL;
0628     }
0629 
0630     if (ret)
0631         return ret;
0632 
0633     return round_rate;
0634 }
0635 
0636 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
0637                 unsigned long parent_rate)
0638 {
0639     struct clk_pll *pll = to_clk_pll(hw);
0640     u32 pll_val = readl(pll->reg);
0641     unsigned long pll_freq;
0642 
0643     switch (pll->type) {
0644     case PLL_TYPE_VT8500:
0645         pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
0646         pll_freq /= VT8500_PLL_DIV(pll_val);
0647         break;
0648     case PLL_TYPE_WM8650:
0649         pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
0650         pll_freq /= WM8650_PLL_DIV(pll_val);
0651         break;
0652     case PLL_TYPE_WM8750:
0653         pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
0654         pll_freq /= WM8750_PLL_DIV(pll_val);
0655         break;
0656     case PLL_TYPE_WM8850:
0657         pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
0658         pll_freq /= WM8850_PLL_DIV(pll_val);
0659         break;
0660     default:
0661         pll_freq = 0;
0662     }
0663 
0664     return pll_freq;
0665 }
0666 
0667 static const struct clk_ops vtwm_pll_ops = {
0668     .round_rate = vtwm_pll_round_rate,
0669     .set_rate = vtwm_pll_set_rate,
0670     .recalc_rate = vtwm_pll_recalc_rate,
0671 };
0672 
0673 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
0674 {
0675     u32 reg;
0676     struct clk_hw *hw;
0677     struct clk_pll *pll_clk;
0678     const char *clk_name = node->name;
0679     const char *parent_name;
0680     struct clk_init_data init;
0681     int rc;
0682 
0683     if (!pmc_base)
0684         vtwm_set_pmc_base();
0685 
0686     rc = of_property_read_u32(node, "reg", &reg);
0687     if (WARN_ON(rc))
0688         return;
0689 
0690     pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
0691     if (WARN_ON(!pll_clk))
0692         return;
0693 
0694     pll_clk->reg = pmc_base + reg;
0695     pll_clk->lock = &_lock;
0696     pll_clk->type = pll_type;
0697 
0698     of_property_read_string(node, "clock-output-names", &clk_name);
0699 
0700     init.name = clk_name;
0701     init.ops = &vtwm_pll_ops;
0702     init.flags = 0;
0703     parent_name = of_clk_get_parent_name(node, 0);
0704     init.parent_names = &parent_name;
0705     init.num_parents = 1;
0706 
0707     pll_clk->hw.init = &init;
0708 
0709     hw = &pll_clk->hw;
0710     rc = clk_hw_register(NULL, &pll_clk->hw);
0711     if (WARN_ON(rc)) {
0712         kfree(pll_clk);
0713         return;
0714     }
0715     rc = of_clk_add_hw_provider(node, of_clk_hw_simple_get, hw);
0716     clk_hw_register_clkdev(hw, clk_name, NULL);
0717 }
0718 
0719 
0720 /* Wrappers for initialization functions */
0721 
0722 static void __init vt8500_pll_init(struct device_node *node)
0723 {
0724     vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
0725 }
0726 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
0727 
0728 static void __init wm8650_pll_init(struct device_node *node)
0729 {
0730     vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
0731 }
0732 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
0733 
0734 static void __init wm8750_pll_init(struct device_node *node)
0735 {
0736     vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
0737 }
0738 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
0739 
0740 static void __init wm8850_pll_init(struct device_node *node)
0741 {
0742     vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
0743 }
0744 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
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